Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a management processor configured to initiate a communication arrangement between a first endpoint device coupled to a communication fabric and a second endpoint device coupled to the communication fabric. The communication arrangement is configured to redirect a transfer from the first endpoint device based on an address corresponding to an address range of the second endpoint device without passing the transfer through a host processor coupled to the communication fabric that executes an application initiating the transfer.

Abstract: The invention includes systems and methods for routing data packets in a robot. The method comprises routing, using a first switching device, data packets between a first host processor and a first electronic device of the robot, and routing, using the first switching device, data packets between a second host processor and a second electronic device of the robot.

Abstract: A method for addressing power outage of an arithmetic logic apparatus including an arithmetic logic part, a power supply port to which power is externally supplied, and a battery, the arithmetic logic part including a primary system device and a secondary system device, the method includes detection processing of detecting disruption of power in the power supply port, supplying processing of supplying power from the battery to the arithmetic logic part when the disruption is detected in the detection processing, end processing of performing processing of ending the secondary system device to reduce power consumption of the secondary system device when the supplying processing is performed, and backup processing of performing data backup using the primary system device upon completion of the end processing.

Abstract: A method includes transmitting first data with a first priority through a first dedicated interface on a transmit side of a PCIe system. The method also includes transmitting second data with a second priority through a second dedicated interface on the transmit side of the PCIe system. The method includes transmitting the first data and the second data to a receive side of the PCIe system using two or more virtual channels over a PCIe link, where the first data uses a first virtual channel and the second data uses a second virtual channel.

Abstract: A multi-format graphics process unit (GPU) docking board is disclosed. The multi-format GPU docking board includes a first switch to enable communication between a first format (GPU) board and a second format GPU board, and a second switch to enable communication between a central processing unit (CPU) and the first format GPU board and between the CPU and the second format GPU board.

Abstract: The present disclosure relates to a communication apparatus, a communication method, and a program that enable more reliable communication. An I3C master transmits a parameter having been changed to an I3C slave during communication in Sync Mode with the I3C slave, and gives an instruction on a timing at which the parameter having been changed is reflected in the I3C slave by transmitting a predetermined command. The I3C slave holds the parameter having been changed, the parameter being received during communication in Sync Mode with the I3C master, and determines to reflect the parameter having been changed at a timing at which the predetermined command is transmitted from the I3C master. The present technology can be applied to, for example, an I3C bus.

Abstract: Providing deterministic frequency and voltage enhancements for a processor is disclosed. In an embodiment, a microcontroller on a processor identifies a plurality of parameters related to a processor, the plurality of parameters including at least a current supplied to the processor; determines, in dependence upon the plurality of parameters, one or more frequency scaling indexes including determining an effective switching capacitance ratio; identifies, in dependence upon the one or more frequency scaling indexes, a predetermined frequency parameter for the processor; and transitions, based on the frequency parameter, the processor to a target clock frequency.

Abstract: An example method for prioritizing deployment of nodes in a cluster comprises: determining, at a first time and by a first node of a plurality of nodes in a cluster of a distributed storage system, that a second node having a higher priority than the first node is in a startup phase of the second node; determining, at a second time subsequent to the first time and by the first node, that the second node has completed the startup phase of the second node; and initiating, based on the determining that the second node has completed the startup phase and by the first node, a startup phase of the first node.

Abstract: The present disclosure relates to a secondary device comprising a first port receiving a clock signal from a first port of a primary device and a second port connected to a second port of the primary device. The clock signal determines, for each bit transmission, first, second, third and fourth successive phases. The secondary device puts its second port in a high impedance state during the first, second and fourth phases of each bit transmission. During the third phase of each transmission of a bit of data from the secondary device to the primary device, the secondary device discharges its second port when the transmitted bit has a first value and leaves its second port in a high impedance state when the transmitted bit has a second value.

Abstract: An information handling system polls telemetry data from sensors associated with a central processing unit, and determines current offsets for each one of the sensors based on the telemetry data. The system may also determine a domain current offset associated with a calibration domain, determine a voltage regulator offset based on the domain current offset, and adjust power provided by the voltage regulator to the central processing unit based on the voltage regulator offset.

Abstract: Examples are disclosed that relate to computing devices and methods for authenticating a user. In one example, a method for authenticating a user at a computing device comprises activating a fingerprint reader integrated into a power key of the computing device, and activating a visual indicator at the power key to indicate a status of the fingerprint reader. Based at least in part on activating the fingerprint reader, a standby function of the power key is disabled. A fingerprint of the user is received via the fingerprint reader and used to authenticate the user. After authenticating the user, the visual indicator is deactivated and the standby function of the power key is re-enabled.

Abstract: A power saving apparatus and method for a host system to proactively decide to save power and increase battery life when bus powered peripheral devices are connected to the System's USB TYPE-C ports. The Host (or Host System) decides if a Bus Powered Device (BPD), hub or a peripheral device requires application services, or a device-initiated wake based on wake policies of a respective Universal Serial Bus (USB) 3.2, THUNDERBOLT 3 (TBT3), USB4, DISPLAYPORT (DP) Protocol. Thereafter, the Host decides based on S0, Low Power System standby entry—wake time latency requirement along with USB TYPE-C IO Protocol policies, to trigger the system power delivery (PD) Controller to remove power to the BPD. To save power, the Host System Wake logic power partition is also powered off.

Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

Abstract: A power management system including a management apparatus configured to assign divided computation processing constituting at least a part of predetermined computation processing to a distributed computing device placed in a facility, wherein the management apparatus includes a receiver configured to receive a message including an information element indicating a type of corresponding computation processing that the distributed computing device is capable of handling, and a controller configured to perform assignment processing to assign the divided computation processing to the distributed computing device based on the type of the corresponding computation processing.

Abstract: The present disclosure discloses a high-bandwidth double data rate (DDR) dual-in-line memory module (DIMM), a memory system, and an operation method of the memory system.

Abstract: A voltage regulator system of an information handling system includes a Smart Power Stage (SPS) and a voltage regulator controller. The SPS includes a high-side transistor and a low-side transistor. The voltage regulator controller detects a normal power down of the information handling system and sets bleed state for the SPS to a first state. Based on the bleed state being set to the first state, the voltage regulator controller provides a first control voltage to the low-side transistor and a second control voltage to the high-side transistor. The first control voltage causes the low-side transistor to be fully turned on, and the second control voltage causes the high-side transistor to be in a linear region. In response to a predetermined amount of time expiring, the voltage regulator controller enters the SPS in an idle mode.

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

Abstract: A method for power management of a computing system having two or more physical servers for hosting virtual machines of a virtual system and one or more uninterruptible power supplies for supplying at least a subset of the physical servers with power, each of the one or more uninterruptible power supplies being connected to a phase of a multiple phase power supply, is disclosed. The method comprises receiving an action input for the computing system, which may impact the power consumption of the physical servers, processing the received action input with a predictive model of power consumption of the physical servers with regard to the battery autonomy of the one or more uninterruptible power supplies and/or the load balancing of the several phases of the multiple phase power supply, and optimizing the utilization of the physical servers based on the result of the processing.

Abstract: An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (P0nMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.

Abstract: Methods and systems for providing computer implemented services using configurable hardware components are disclosed. To update operation of a configurable hardware component, a large amount of data may be provided to a single input/output pin of the configurable hardware component. The large amount of data may be encoded in a complex waveform corresponding with at least eleven bits of digital data. The complex waveform may be interpreted by the configurable hardware component to obtain the large amount of data. Using the large amount of data, the configurable hardware component may update its operation to be in condition for providing the computer implemented services.