Patents Examined by Glenn A. Auve
  • Patent number: 10782758
    Abstract: A framework for system power control of a dual-port non-volatile memory storage device is provided. The electronic system includes a storage device, two hosts and a control circuit within each of the two hosts. Each host filters signals for shortly turning off a power supply of the storage device during a process of boot and reboot of the host. When one of the hosts enters a turn-off state, it is detected whether another one of the hosts is running, and the one of the hosts does not control the power supply if the another one of the hosts is running. Two control signals of the two hosts control the power supply of the storage device through an AND gate.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 22, 2020
    Assignee: Wistron Corporation
    Inventors: Syu-Siang Lee, Zh-Wei Zhang
  • Patent number: 10776302
    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Patent number: 10771081
    Abstract: In one example, a mixed signaling socket includes a set of central processing unit (CPU) cores coupled via an inter-core link and a set of analog circuits having an analog input, each analog circuit coupled to a respective CPU core via a separate private bus. A field programmable gate array (FPGA) control circuit is coupled to the inter-core link and the set of analog circuits to provide predicable clock timing to the set of analog circuits and control signals to the set of CPU cores. An analog to digital module in at least one CPU core includes instructions to perform an analog to digital conversion to create a digital representation of the analog input using the predictable clock timing and control signals from the FPGA.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: September 8, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Rachid Kadri
  • Patent number: 10768940
    Abstract: A computing device includes an accessory containing an option ROM, a first processor adapted to boot the computing device and to execute the option ROM, and a second processor adapted to be activated by the first processor to monitor execution of the option ROM by the first processor. The second processor is adapted to restore the first processor to a state prior to execution of the option ROM in response to the first processor becoming hung during execution of the option ROM. A computer program product includes program instructions executable by a processor to monitor execution of the option ROM by a first processor of a computing device, determine whether the first processor has become hung during execution of the option ROM, and restore the first processor to an execution environment that the first processor had prior to execution of the option ROM.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: September 8, 2020
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Zhijun Liu, Yun Yun Lou, Xuefeng Sun
  • Patent number: 10769269
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for gathering configuration information of a computer system during a system management mode of the computer system and exposing the gathered configuration information to securely attest to the configuration of the system.
    Type: Grant
    Filed: June 30, 2018
    Date of Patent: September 8, 2020
    Assignee: INTEL CORPORATION
    Inventor: Kirk D. Brannock
  • Patent number: 10754956
    Abstract: A method for executing a security stack can include executing a bootloader included in a memory resource of an electronic device in response to the bootloader receiving a prompt. The method can include performing a verification function, with the bootloader, on data stored in a programmable memory included in the memory resource of the electronic device, wherein the verification function includes comparing security data stored in a configuration area of the memory resource with a signature that accompanies the data stored in the programmable memory. The method can include determining whether the security data stored in the configuration area matches the signature that accompanies the data stored in the programmable memory.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: August 25, 2020
    Assignee: Andium Inc.
    Inventors: James Dooley, Jory Schwach
  • Patent number: 10747704
    Abstract: An electronic unit includes a USB host and a USB device. After the USB host and the USB device are connected to each other by a USB cable, a signal requesting for a connection permission is transmitted from the USB device to the USB host, and the USB host determines whether to permit a connection based on the signal. The electronic unit further includes a power supply configured to supply power to the USB device, and an additional GND pattern different from a GND pattern of the USB cable is electrically connected to a GND of the USB port of at least one of the USB host and the USB device. An area of the additional GND pattern is 2000 mm2 or more.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: August 18, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Ui Yamaguchi
  • Patent number: 10747369
    Abstract: Embodiments of the present disclosure disclose a method and an apparatus for responding to a touch operation, a storage medium and a terminal. The method includes: when a plurality of touch points are detected on a touch screen of a terminal, determining whether the terminal is in a charging mode currently; when the terminal is in the charging mode, determining a trip point from the plurality of touch points; and preventing the trip point from being responsive and allowing touch points other than the trip point in the plurality of touch points to be responsive.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 18, 2020
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Qiang Zhang, Mingqiang Guo, Tong Han, Hao Wang, Rendong Shi
  • Patent number: 10747699
    Abstract: A bus control circuit configured to transfer access commands for performing exclusive access between a first bus specification and a second bus specification by converting from a first exclusive access command applying to the first bus specification which deals with exclusive access, into a second exclusive access command of the second bus specification which doesn't deal with the exclusive access.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 18, 2020
    Assignee: SOCIONEXT INC
    Inventors: Takayuki Otani, Teruhiko Kamigata, Takashi Kawasaki, Eiichi Nimoda
  • Patent number: 10733127
    Abstract: A data transmission apparatus that transmits transmission data from a first memory to a second memory through a communication channel, the first memory storing data in units of a first data block of a first data size, and the communication channel having a width of a second data size, includes: a storage that stores the transmission data read from the first memory; and a transmission controller that transmits the transmission data stored in the storage from the first memory to the second memory in units of an integral multiple of the second data size, such that data transmission from the first memory to the second memory is efficiently performed.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 4, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiko Suzuki, Shinya Miyata
  • Patent number: 10719118
    Abstract: In one embodiment, power level management in accordance with the present description, is provided in a storage unit having both a disk storage drive, and another non-volatile, non-disk memory or storage such as a solid state drive, for storing metadata. The metadata storage provides direct access to the metadata stored in the non-disk storage even though the disk storage drive may be in a low power mode in which the data storage media disk of the disk storage drive is stopped or spinning at a reduced rate of rotation. As a result, power consumption and cooling requirements associated with disk storage drives, may be reduced in a low power level mode of storage unit operation for input/output operations limited to metadata stored in the metadata storage. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: July 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hans-Joachim Tannenberger, Richard Hutzler, William K. Morse, Bradley Bernhardt, Mitchell Montanez, Karl A. Nielsen, Thomas J. Fleischman
  • Patent number: 10712778
    Abstract: A docking board removably coupled to a processor board that does not function when not operatively coupled to the docking board. The docking board sends power to and receive a control signal from the processor board when operatively coupled to the processor board and does not send power and does not receive a control signal when not operatively coupled to the processor board. The docking board is removably coupled to an expansion board that performs a computer function that is not performed by the processor board and the docking board. The docking board sends power and a control signal to the expansion board when the docking board is operatively coupled to the processor board and the expansion board, and does not send power and does not send a control signal to the expansion board when the docking board is not operatively coupled to the processor board and the expansion board.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: July 14, 2020
    Assignee: Management Services Group, Inc.
    Inventor: Thomas S. Morgan
  • Patent number: 10705857
    Abstract: In an example, a method includes, in initialising an operations support system providing a common access point to a plurality of data services, accessing a list of modules, each module relating to at least one of the plurality of data services to be accessed via the common access point. A list of at least one processed modules data file may also be accessed, wherein each processed modules data file comprises bundled modules. The processed modules data files may be requested and a first module from the list of modules which is not part of a processed modules data file may be identified. At least one processed modules data file and the first module may be loaded to provide the operations support system.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: July 7, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jean-Charles Picard, Nicolas Donato
  • Patent number: 10684904
    Abstract: Embodiments of information handling systems and methods are provided herein to selectively control ownership of a hardware watchdog timer (WDT) provided on a system platform of an information handling system (IHS), which is configured to store and execute boot firmware, an operating system (OS) and one or more user applications. One embodiment of a method disclosed herein may include receiving user input in a boot setup utility of the boot firmware to select between OS-ownership and user application-ownership of the hardware WDT during OS runtime, and controlling ownership of the hardware WDT during OS runtime based on the user input received in the boot setup utility. Another embodiment of a method disclosed herein may authorize one or more user applications prior to controlling ownership of the hardware WDT during OS runtime, so that only authorized user applications are enabled to use the hardware WDT.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 16, 2020
    Assignee: Dell Products L.P.
    Inventors: Manuel Novoa, Wai Ming R. Chan
  • Patent number: 10686283
    Abstract: A semiconductor device for determining whether a foreign substance (e.g., water) is present and a method of operating the same are provided. The semiconductor device includes a receptacle including a plurality of pins according to a USB type-C receptacle interface; a first current source providing first current to a CC1 signal pin or a CC2 signal pin among the plurality of pins in a first operation mode; a second current source providing second current to the CC1 signal pin or the CC2 signal pin in a second operation mode; a third current source providing third current to at least two pins of other pins excluding the CC1 signal pin and the CC2 signal pin; and a power delivery integrated circuit (PDIC) controlling the first current source, the second current source and the third current source and detecting the voltage level of a signal outputted to the plurality of pins.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je Kook Kim
  • Patent number: 10678726
    Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 9, 2020
    Assignees: STMICROELECTRONICS APPLICATION GMBH, STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.
    Inventors: Fred Rennig, Ludek Beran
  • Patent number: 10671148
    Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system including multiple nodes utilizes a non-uniform memory access (NUMA) architecture. A first node receives a broadcast probe from a second node. The first node spoofs a miss response for a powered down third node, which prevents the third node from waking up to respond to the broadcast probe. Prior to powering down, the third node flushed its probe filter and caches, and updated its system memory with the received dirty cache lines. The computing system includes a master node for storing interrupt priorities of the multiple cores in the computing system for arbitrated interrupts. The cores store indications of fixed interrupt identifiers for each core in the computing system. Arbitrated and fixed interrupts are handled by cores with point-to-point unicast messages, rather than broadcast messages.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 2, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Bryan P. Broussard, Vydhyanathan Kalyanasundharam
  • Patent number: 10673648
    Abstract: A network device includes a Network Interface Device (NID) and multiple servers. Each server is coupled to the NID via a corresponding PCIe bus. The NID has a network port through which it receives packets. The packets are destined for one of the servers. The NID detects a PCIe congestion condition regarding the PCIe bus to the server. Rather than transferring the packet across the bus, the NID buffers the packet and places a pointer to the packet in an overflow queue. If the level of bus congestion is high, the NID sets the packet's ECN-CE bit. When PCIe bus congestion subsides, the packet passes to the server. The server responds by returning an ACK whose ECE bit is set. The originating TCP endpoint in turn reduces the rate at which it sends data to the destination server, thereby reducing congestion at the PCIe bus interface within the network device.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: June 2, 2020
    Assignee: Netronome Systems, Inc.
    Inventors: Nicolaas J. Viljoen, Johan Moraal, Michael J. Rapson
  • Patent number: 10664005
    Abstract: The invention provides a system and method for detecting clock frequency offset of fan chip. The system comprises a fan chip and a control unit. A target pulse width is defined in the fan chip and the control unit. When the control unit executes a detection process of clock frequency offset for the fan chip, it will generate a specific pattern pulse signal and send the specific pattern pulse signal to the fan chip. The fan chip enters a detection mode of clock frequency offset according to the specific pattern pulse signal, generates a response signal including an actual target pulse width based on referring to the defined target pulse width, and send the response signal to the control unit. The control unit compares a difference between the actual target pulse width and the defined target pulse width to detect a clock frequency offset value of the fan chip.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 26, 2020
    Assignee: Sentelic Corporation
    Inventors: Wen-Ting Lee, Chung-Chih Fang, Li-Wei Lin
  • Patent number: 10664438
    Abstract: Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: May 26, 2020
    Assignee: NeuroBlade, Ltd.
    Inventors: Elad Sity, Eliad Hillel