Patents Examined by Glenn A. Auve
  • Patent number: 10346345
    Abstract: The disclosed technology is generally directed to peripheral access. In one example of the technology, stored configuration information is read. The stored configuration information is associated with mapping a plurality of independent execution environments to a plurality of peripherals such that the peripherals of the plurality of peripherals have corresponding independent execution environments of the plurality of independent execution environments. A configurable interrupt routing table is programmed based on the configuration information. An interrupt is received from a peripheral. The interrupt is routed to the corresponding independent execution environment based on the configurable interrupt routing table.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 9, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: George Thomas Letey, Douglas L. Stiles, Edmund B. Nightingale
  • Patent number: 10346344
    Abstract: The present invention discloses a method, a client device, and a data forwarding device for transmitting data through a serial port. The method comprises providing at least two virtual logical serial ports mapped to a physical serial port, providing a main serial port connected to the physical serial port and extended serial ports which correspond to the logical serial ports one by one; encapsulating first data and a specified logical serial port according to a preset serial port protocol to obtain a first data frame; transmitting the first data frame to the data forwarding device through the physical serial port; receiving the first data frame through the main serial port, and decapsulating the first data frame according to the serial port protocol to obtain the first data and the specified logical serial port; and transmitting the first data to the extended serial port corresponding to the specified logical serial port.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: July 9, 2019
    Assignee: Goertek Inc.
    Inventor: Guoliang Shi
  • Patent number: 10346041
    Abstract: A proxy device that may query other devices for their configurations is disclosed. The proxy device may include a device communication logic to communicate with the devices over a control plane. The proxy device may also include reception logic 440 that may receive a query from a host. The query may request information from the proxy device about the configurations of the devices. The proxy device may also include a transmission logic to send the device configurations to the host.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sompong Paul Olarig, Son T. Pham
  • Patent number: 10339082
    Abstract: Technologies for secure channel identifier mapping include a computing device having an I/O controller that may connect to one or more I/O devices. The computing device determines a device path to an I/O device that may be used to identify the I/O device. The computing device identifies a firmware method as a function of the device path and invokes the firmware method. In response, the firmware method determines a channel identifier as a function of the device path. The firmware method may determine a pre-determined channel identifier for static or undiscoverable I/O devices. For dynamic I/O devices, the firmware method may determine the channel identifier using a stable algorithm. The I/O controller may assign the channel identifier to the dynamic I/O device using the same stable algorithm. The computing device establishes a secure channel to the I/O device using the channel identifier. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 2, 2019
    Assignee: Intel IP Corporation
    Inventors: Bin Xing, Pradeep Pappachan, Reshma Lal, Siddhartha Chhabra, Mark Shanahan
  • Patent number: 10331564
    Abstract: Technologies for secure I/O with MIPI camera devices include a computing device having a camera controller coupled to a camera and a channel identifier filter. The channel identifier filter detects DMA transactions issued by the camera controller and related to the camera. The channel identifier filter determines whether a DMA transaction includes a secure channel identifier or a non-secure channel identifier. If the DMA transaction includes the non-secure channel identifier, the channel identifier filter allows the DMA transaction. If the DMA transaction includes the secure channel identifier, the channel identifier filter determines whether the DMA transaction is targeted to a memory address in a protected memory range associated with the secure channel identifier. If so, the channel identifier filter allows the DMA transaction. If not, the channel identifier filter blocks the DMA transaction. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Gideon Gerzon, Pradeep Pappachan, Reshma Lal, Siddhartha Chhabra, Bin Xing
  • Patent number: 10324868
    Abstract: The invention relates to a counting unit (100) configured to count an amount of traffic events of a data packet traffic. The counting unit comprises a counting element (131) configured to store a value representing the amount of traffic events.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: June 18, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Gabor Sandor Enyedi, László Molnár, Gergely Pongrácz
  • Patent number: 10318334
    Abstract: A VIRTIO Relay Program allows packets to be transferred from a Network Interface Device (NID), across a PCIe bus to a host, and to a virtual machine executing on the host. Rather than an OvS switch subsystem of the host making packet switching decisions, switching rules are transferred to the NID and the NID makes packet switching decisions. Transfer of a packet from the NID to the host occurs across an SR-IOV compliant PCIe virtual function and into host memory. Transfer from that memory and into memory space of the virtual machine is a VIRTIO transfer. This relaying of the packet occurs in no more than two read/write transfers without the host making any packet steering decision based on any packet header. Packet counts/statistics for the switched flow are maintained by the OvS switch subsystem just as if it were the subsystem that had performed the packet switching.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: June 11, 2019
    Assignee: Netronome Systems, Inc.
    Inventors: Gysbert Floris van Beek van Leeuwen, Johann Heinrich Tönsing
  • Patent number: 10289580
    Abstract: This system determines the operation of data transfer means by direct memory access by a task scheduler in charge of process context changes, the system including deterministic means for establishing and suspending the data transfers of memory data initiated before, but not terminated during, the contextual changes, and for resuming the data transfers during the return to the corresponding initial context, in order to give each process full and exclusive access to the means of transfer.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: May 14, 2019
    Assignee: THALES
    Inventors: Philippe Jean-Pierre Louis Grossi, Dominique David, Fredéric Jacques Jean-Marie Berthoz
  • Patent number: 10282319
    Abstract: Method and system are disclosed for arbitration of parallel multi-event processing. In one embodiment, a parallel multi-event processing system includes a plurality of hardware components, where each hardware component in the plurality of hardware components is assigned with a unique range of addresses, a plurality of hardware engines, where the plurality of hardware engines are configured to access the plurality of hardware components, a controller configured to perform arbitration on one or more requested transactions among the plurality of hardware engines and the plurality of hardware components based on one or more hardware components in the plurality of hardware components to be accessed, and the plurality of hardware components, the plurality of hardware engines, and the controller are configured to perform the one or more requested transactions according to the arbitration.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: May 7, 2019
    Assignee: X-Drive Technology, Inc.
    Inventor: Darder Chang
  • Patent number: 10268617
    Abstract: An integrated circuit includes a transmitting circuit configured to be coupled to a physical serial interface having a bit width. The transmitting circuit is configured to transmit, via the physical serial interface, a frame including multiple aligned flits all of an equal fixed length that is an integer multiple of the bit width of the physical serial interface. The multiple flits include both a control flit specifying at least a command to be performed by a recipient of the command and a data flit providing data to be operated upon through performance of the command. The control flit includes a data protection code computed over the control flit and a data flit of a previously transmitted frame.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lonny Lambrecht, Michael S. Siegel, William S. Starke, Jeffrey A. Stuecheli
  • Patent number: 10248431
    Abstract: The present disclosure relates to a system and method for enabling implementation of a secondary function of a universal serial bus (USB) device on a computer that the USB device is communicating with, wherein an operating system of the computer does not have a required driver which needs to be mapped to the USB device to enable implementation of the secondary function. The system involves a USB device which has the required driver for implementing the secondary function stored therein. The required driver can be supplied to the computer from the USB device using a control which selects the secondary function of the USB device.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: April 2, 2019
    Assignee: VERTIV IT SYSTEMS, INC.
    Inventors: James R. Mataya, Christopher R. Hinshaw, Karl S. Mills
  • Patent number: 10241951
    Abstract: A method of transferring data between a host and a PCI device is disclosed. The method comprises mapping a fixed memory-mapping control block in a host memory of the host to a control register of a memory-mapping unit of the PCI device; mapping a dynamic data-access memory block in the host memory to a default memory block in a memory of the PCI device, wherein the memory-mapping unit translates an address between the dynamic data-access memory block and a memory block in the memory of the PCI device; and dynamically modifying a value in the control register of the memory-mapping unit through the fixed memory-mapping control block such that an address of the dynamic data-access memory block in the host memory is translated to a different address in the memory of the PCI device based on the modified value in the control register of the memory-mapping unit.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 26, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Hani Ayoub, Adi Habusha, Ronen Shitrit
  • Patent number: 10235318
    Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 19, 2019
    Assignee: INPHI CORPORATION
    Inventors: Sreenivas Krishnan, Nirmal Raj Saxena
  • Patent number: 10224118
    Abstract: A compatibility checking mechanism can include a reader, a checking mechanism, a writer and an approver. The reader can read out memory content from a memory of a first device component. The checking mechanism can check whether the first device component can be used together with a second device component based on the read-out memory content, and supply a result of the checking whether the first device component can be used together with a second device component. The writer can induce writing of a component identifier of the second device component in the memory of the first device component if checking of the read-out memory content indicates that the first device component can be used together with the second device component. The approver can approve or block use of the first device component as a function of the result of the checking of the read-out memory content.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: March 5, 2019
    Assignee: Siemens Healthcare GmbH
    Inventor: Peter Haeuser
  • Patent number: 10216653
    Abstract: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: February 26, 2019
    Assignee: International Busiess Machines Corporation
    Inventors: Lakshminarayana Baba Arimilli, Yiftach Benjamini, Bartholomew Blaner, Daniel M. Dreps, John David Irish, David J. Krolak, Lonny Lambrecht, Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Kenneth M. Valk, Curtis C. Wollbrink
  • Patent number: 10216967
    Abstract: A USB-style data-transfer device employs volatile memory that is connected to an onboard power-storage device for data storage. Through this design, any data stored on the memory can be physically cleared by interrupting the supply of electrical power from the onboard power-storage device to the memory. Enhanced security relative to conventional USB flash devices is provided by the volatile memory-based USB-style data-transfer device as the memory can be physically cleared without being plugged into a computer system either automatically when the onboard power storage device runs out of electrical power to supply to the volatile memory, or by user initiation through either a programmed instruction to interrupt the supply of electric power after a set time period or the operation of a manual switch which interrupts the supply of electric power.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: February 26, 2019
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Jeffrey M. Lloyd, Michael Tall, Alex G. Phipps
  • Patent number: 10216423
    Abstract: A processing device of a storage server that manages a plurality of SSDs receives a request to write data. The processing device determines one or more attributes associated with the request, generates a stream tag for the request based on the one or more attributes, and sends a first write command to a first SSD of the plurality of SSDs. The first write command comprises at least a portion of the data and the stream tag that causes the first SSD to write the portion of the data to a first stream block of the first SSD.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: February 26, 2019
    Assignee: Pavilion Data Systems, Inc.
    Inventors: Kiron Balkrishna Malwankar, Karagada Ramarao Kishore, Sundar Kanthadai
  • Patent number: 10206626
    Abstract: A biosignal measurement and transmission apparatus having a simplified signal slot as provided is configurable for receiving signals from a biosignal detection apparatus and a biosignal detection correction unit and for performing signal transfer and analysis operations.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: February 19, 2019
    Inventor: Chuen Wei Lu
  • Patent number: 10210126
    Abstract: A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: February 19, 2019
    Assignee: RAMBUS INC.
    Inventor: Michael J. Sobelman
  • Patent number: 10198058
    Abstract: An arithmetic operation device configuring a control apparatus includes: a communication circuit that is used for exchanging data with functional units through a communication line; a processor that is used for executing a user program executing at least one of an arithmetic operation process using data acquired from the functional units and a generating process of data to be transmitted to the functional units; and a monitoring circuit that is connected to the communication circuit and the processor. The monitoring circuit gives a notification from the communication circuit to the functional units on the basis of at least one of detection of shutoff of power supplied to the arithmetic operation device and reception of a preliminary notification before the shutoff of the power supplied to the arithmetic operation device, and the notification is used for executing a process according to shutoff of power supply to the arithmetic operation device.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: February 5, 2019
    Assignee: OMRON Corporation
    Inventors: Yasunori Fukuda, Masaichi Takai, Shigeyuki Eguchi, Yasuhiro Nishimura