Abstract: A system is disclosed that includes two or more network elements, each comprising a Precision Time Protocol (PTP) Hardware Clock (PHC) that is adjustable based, at least in part, on physical layer frequency information.

Abstract: Embodiments include herein are directed towards a system and method for monitoring compliance patterns. Embodiments may include a re-timer device-under-test configured to transmit a truncated compliance pattern associated with a PCIe compliance mode. Embodiments may further include a BFM monitor configured to receive the truncated compliance pattern and to identify a communication signal associated with the truncated compliance pattern. The BFM monitor may be further configured to discard at least one unexpected symbol on at least one lane associated with the communication signal and to collect compliance patterns on all lanes of the communication signal. The BFM monitor may be further configured to align one or more lane FIFOs based upon skew and to enable one or more compliance pattern checkers.

Abstract: A handshake protocol circuit, a chip and a computer device. In the present handshake protocol circuit, according to level signals of a first protocol signal input end, a first protocol signal output end, a second protocol signal input end and a second protocol signal output end, a control circuit controls a data storage circuit to store and output operation data, which is equivalent to caching the operation data by the storage circuit. Therefore, when the number of functional module circuits is relatively large, the continuity of combination logic of handshake protocols between the module circuits is relatively reduced, thereby relatively ensuring the normal communication of data between the functional module circuits. In addition, the present disclosure further provides a handshake protocol chip and a computer device.

Abstract: Systems, apparatuses and methods may provide for technology that stores first hardware related data to a basic input output system (BIOS) memory area and generates a mailbox data structure, wherein the mailbox data structure includes a first identifier-pointer pair associated with the first hardware related data. Additionally, the technology may generate an operating system (OS) interface table, wherein the OS interface table includes a pointer to the mailbox data structure. In one example, the technology also stores second hardware related data to the BIOS memory area at runtime and adds a second identifier-pointer pair to the mailbox data structure at runtime, wherein the second identifier-pointer pair is associated with the second hardware related data.

Abstract: In view of defects in the prior art, the present disclosure provides a controller in a high-speed serial peripheral interface (SPI) master mode, where clock signals are provided by a phase locked loop (PLL), and the entire controller includes: a low-speed clock domain and a high-speed clock domain, where the PLL provides two main clock signals by different clock frequency dividers, provides a low-speed clock signal to the low-speed clock domain, and provides a high-speed source clock signal to the high-speed clock domain. By such technical solutions in the present disclosure, functions of different clock domains are divided through asynchronization of a high-speed SPI controller, and the function of a high-speed SPI flash access is implemented, thereby saving a read/write time. Especially in an application scenario of an SPI flash boot, the controller can greatly optimize a startup time.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device includes a PCIe layer and a PCIe controller. The PCIe layer performs communication between a host and a Direct Memory Access (DMA) device. The PCIe controller switches an operating clock from a PCIe clock generated based on a reference clock to an internal clock, processes data of the PCIe layer on the basis of the internal clock, and recovers a link with respect to the host, when a reset signal received from the host is asserted or the reference clock is off.

Abstract: Examples described herein provide a hardware-software interface solution reads the boot code in segments into a buffer. A given boot code segment is stored in the buffer. A second buffer can be written-to with another boot code segment while the boot code segment in the buffer is read-from. A central processing unit (CPU) socket provides coordination such that one or more CPU sockets have copied the segment before permitting the segment to be overwritten in the buffer.

Abstract: A PCIe device setting, when a fail lane is detected during a link setting operation, a link by using remaining lanes includes a plurality of lanes comprising a plurality of ports, and a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes remaining lanes, except for a fail lane from among the plurality of lanes, wherein the fail lane from among the plurality of lanes has a state in which the fail lane is unable to form a link with remaining lanes that have not failed from among the plurality of lanes.

Abstract: A clock control method, apparatus, and device, and a storage medium. By the method, timing optimization of bidirectional data communication between a server mainboard and a Peripheral Component Interconnect express (PCIe) expansion board is relatively implemented, and the occurrence of a situation where in any data communication direction between the server mainboard and the PCIe expansion board, data transmitted by the initiating end at a given high-level moment does not reach the receiving end at a next high-level moment may be prevented, thus ensuring the reliability of communication between the server mainboard and the PCIe expansion board. In addition, the present application further provides a clock control apparatus and device, and a storage medium, and the beneficial effects are as stated above.

Abstract: An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases that are synchronized by generating a common clock signal from a clock generator of the first SoC and simultaneously applying the common clock signal to a first counter of the first SoC and a second counter of the second SoC whereby the first counter and the second counter count clock edges of the common clock. The clock counts are shared through an interface between the first SoC and the second SoC and compared to each other. When the clock counts are different, a clock count of the first counter or the second counter is adjusted to cause the clock counts to match each other. The adjusted clock count is synchronized to the respective clocks of the first and second SoCs, thus synchronizing the first and second SoCs to each other.

Abstract: Examples disclosed herein relate to performing a verification check in response to receiving notification. A computing system includes a host processor, memory coupled to the host processor, and a device separate from the host processor capable of accessing the memory. The host processor has a page table base register. The host processor is configured to send a notification to the device when the page table base register changes. The device performs a verification check in response to receiving the notification.

Abstract: A method includes transmitting first data with a first priority through a first dedicated interface on a transmit side of a PCIe system. The method also includes transmitting second data with a second priority through a second dedicated interface on the transmit side of the PCIe system. The method includes transmitting the first data and the second data to a receive side of the PCIe system using two or more virtual channels over a PCIe link, where the first data uses a first virtual channel and the second data uses a second virtual channel.

Abstract: An interface for coupling an agent to a fabric supports a load/store interconnect protocol and includes a header channel implemented on a first subset of a plurality of physical lanes, the first subset of lanes including first lanes to carry a header of a packet based on the interconnect protocol and second lanes to carry metadata for the header. The interface additionally includes a data channel implemented on a separate second subset of the plurality of physical lanes, the second subset of lanes including third lanes to carry a payload of the packet and fourth lanes to carry metadata for the payload.

Abstract: A fan device may include a an expansion card, a fan, and a mounting mechanism. The expansion card may mechanically and communicatively connect to a computing system. The mounting mechanism mounts the fan within an opening in the expansion card. The mounting mechanism further permits the fan to move relative to the expansion card.

Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.

Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Abstract: A semiconductor device for determining whether a foreign substance (e.g., water) is present and a method of operating the same are provided. The semiconductor device includes a receptacle including a plurality of pins according to a USB type-C receptacle interface; a first current source providing first current to a CC1 signal pin or a CC2 signal pin among the plurality of pins in a first operation mode; a second current source providing second current to the CC1 signal pin or the CC2 signal pin in a second operation mode; a third current source providing third current to at least two pins of other pins excluding the CC1 signal pin and the CC2 signal pin; and a power delivery integrated circuit (PDIC) controlling the first current source, the second current source and the third current source and detecting the voltage level of a signal outputted to the plurality of pins.

Abstract: A method for increasing power supply voltage in an information handling system in a normal mode with a first peak voltage comprises, in response to receiving a request for a higher peak voltage, an embedded controller (EC) receiving information associated with the application including a request for power at a higher peak voltage, a housekeeping IC communicating a signal to a PWM IC to increase voltage supplied to the information handling system to the higher peak voltage, the PWM IC converting from the PSU to the higher peak voltage and starting a timer with a defined time period. If no additional requests for operating at the higher peak voltage are received before the time period expires, the PWM IC communicates a signal that power will stop being supplied at the higher peak voltage, and the information handling system returns to operating in the normal mode at the first peak voltage.

Abstract: An information handling system bus port above a subject information handling system bus device may host an information handling system bus out of band message access control list of information handling system bus target device identifiers of other information handling system bus connected devices that the subject device is permitted to communicate with. The port may compare an information handling system bus target device identification field in out of band messages from the subject device to the list and route only out of band messages from the subject device in which the target device identification in the target device identification field is on the access control list through the information handling system bus. The port may discard (and generate error notifications, statuses, etc.) for out of band messages in which the target device identification in the target device identification field is not on the access control list.