Patents Examined by Glenn A. Auve
  • Patent number: 11573895
    Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Peng Li, Jawad B. Khan, Sanjeev N. Trika
  • Patent number: 11561920
    Abstract: A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 24, 2023
    Assignee: RAMBUS INC.
    Inventor: Michael J. Sobelman
  • Patent number: 11561571
    Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: January 24, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwanwoo Noh, Sungho Seo, Yongwoo Jeong, Dongwoo Nam, Myungsub Shin, Hyunkyu Jang
  • Patent number: 11556492
    Abstract: A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: January 17, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ganapathi Hegde, Krushal Shah, Mayank Garg, Luis Eduardo Ossa, Vashist Bist
  • Patent number: 11550744
    Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: January 10, 2023
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Jawad Benhammadi, Sylvain Meyer
  • Patent number: 11543965
    Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: January 3, 2023
    Inventors: Sompong Paul Olarig, Son T. Pham
  • Patent number: 11546187
    Abstract: A communication system for an industrial process includes multiple slave modules connected in series with a master controller. The master controller stores a communication schedule that defines an ordered sequence of messages and identifiers associated with each message. The master controller transmits messages downstream through the slave modules to a terminal one of the slave modules. The terminal slave module generates a return message that is transmitted upstream to the master controller. Each slave module receives each downstream message, identifies based on the message identifier whether the message is associated with response information from the slave module, and inserts the response information into corresponding upstream messages.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 3, 2023
    Assignee: Graco Minnesota Inc.
    Inventors: Morgan O. LaMoore, Pavel V. Tysyachuk, Adriana F. Mickols, Nicholas T. Fritz
  • Patent number: 11544073
    Abstract: Software configuration deployment techniques for disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes presenting a user interface configured to receive instructions related to deployment of software to compute units, and receiving user selections of a software element for deployment to a compute unit comprising a processing element and a storage element.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: January 3, 2023
    Assignee: Liqid Inc.
    Inventors: Henry Lee Harris, James Scott Cannata
  • Patent number: 11537761
    Abstract: An apparatus to facilitate transparent network access controls for spatial accelerator device multi-tenancy is disclosed. The apparatus includes a secure device manager (SDM) to: establish a network-on-chip (NoC) communication path in the apparatus, the NoC communication path comprising a plurality of NoC nodes for ingress and egress of communications on the NoC communication path; for each NoC node of the NoC communication path, configure a programmable register of the NoC node to indicate a node group that the NoC node is assigned, the node group corresponding to a persona configured on the apparatus; determine whether a prefix of received data at the NoC node matches the node group indicated by the programmable register of the NoC; and responsive to determining that the prefix does not match the node group, discard the data from the NoC node.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: December 27, 2022
    Assignee: Intel Corporation
    Inventors: Steffen Schulz, Alpa Trivedi, Patrick Koeberl
  • Patent number: 11531633
    Abstract: System and method for implementing accelerated memory transfers in an integrated circuit includes identifying memory access parameters for configuring memory access instructions for accessing a target corpus of data from within a defined region of an n-dimensional memory; converting the memory access parameters to direct memory access (DMA) controller-executable instructions, wherein the converting includes: (i) defining dimensions of a data access tile based on a first parameter of the memory access parameters; (ii) generating multi-directional data accessing instructions that, when executed, automatically moves the data access tile along multiple distinct axes within the defined region of the n-dimensional memory based at least on a second parameter of the memory access parameters; transferring a corpus of data from the n-dimensional memory to a target memory based on executing the DMA controller-executable instructions.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: December 20, 2022
    Assignee: quadric.io, Inc.
    Inventors: Aman Sikka, Marian Petre, Nigel Drego, Veerbhan Kheterpal
  • Patent number: 11513987
    Abstract: A system includes a memory including a plurality of rings, an endpoint associated with a ring of the plurality of rings, and a gateway. The gateway is configured to receive a notification from the endpoint regarding a packet made available in the ring associated with the endpoint, access the ring with an RDMA read request, retrieve the packet made available in the ring, and forward the packet on an external network.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: November 29, 2022
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 11507394
    Abstract: Changing accelerator card images without rebooting a host system includes receiving, within an integrated circuit (IC) of an accelerator card, an address of a platform image stored in a non-volatile memory of the accelerator card. The address is received over a communication link between the host system and the accelerator card while the communication link is connected. Changing accelerator card images includes detecting, within a register of the IC, that a warm boot enable flag is set and that the communication link with the host system is disconnected. In response to detecting that the warm boot enable flag is set and that the communication link is disconnected, loading of the platform image from the address of the non-volatile memory into the integrated circuit is initiated.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: November 22, 2022
    Assignee: Xilinx, Inc.
    Inventors: Siva Santosh Kumar Pyla, Ravinder Sharma, Gokul Kavungal Nechikott, Saifuddin Kaijar, Brian S. Martin, Suraj Patel, Rishabh Gupta, Ch Vamshi Krishna, Kaustuv Manji
  • Patent number: 11487678
    Abstract: A memory system includes a plurality of memory dies and a controller coupled with the plurality of memory dies via a plurality of channels. The controller is configured to perform a correlation operation on at least some read requests among a plurality of read requests inputted from an external device so that the plurality of memory dies outputs plural pieces of data corresponding to the plurality of read requests via the plurality of channels in an interleaving way. The controller is configured to determine when to perform the correlation operation based on the number of the plurality of read requests.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 11489723
    Abstract: Multicast Domain Name System (mDNS)-based pull registration systems and methods facilitate discovery in communication networks, such as Storage Area Networks (SANs) that operate in non-volatile memory express over Fabric (NVMe-oF) environments. In various embodiments, this is accomplished by allowing a network entity (e.g., a Centralized Discovery Controller (CDC)) to use a pull registration to exchange discovery information with a storage subsystem (e.g., a storage array), advantageously, without requiring storage subsystem to possess complex functionalities present in existing designs.
    Type: Grant
    Filed: March 14, 2021
    Date of Patent: November 1, 2022
    Assignee: DELL PRODUCTS L.P.
    Inventors: Erik Smith, Joseph LaSalle White
  • Patent number: 11489921
    Abstract: Multicast Domain Name System (mDNS)-based pull registration systems and methods facilitate discovery in communication networks, such as Storage Area Networks (SANs) that operate in non-volatile memory express over Fabric (NVMe-oF) environments. In various embodiments, this is accomplished by allowing a network entity (e.g., a Centralized Discovery Controller (CDC)) to use a pull registration to exchange discovery information with a storage subsystem (e.g., a storage array), advantageously, without requiring storage subsystem to possess complex functionalities present in existing designs.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: November 1, 2022
    Assignee: DELL PRODUCTS L.P.
    Inventors: Erik Smith, Joseph LaSalle White, Pawan Kumar Singal
  • Patent number: 11474554
    Abstract: A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: October 18, 2022
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hao Wang, Ting-Chin Cho, Hui-Ting Yang, Yung-Sheng Fang, Igor Elkanovich, Amnon Parnass, Chiung-Chi Lin, Ming-Fu Tsai
  • Patent number: 11468169
    Abstract: An information handling system includes a host processing system, first and second data storage devices having respective first and second data storage capacities, and a license manager. The license manager implements a first license, receives a second license, and implements the second license without rebooting the information handling system. The first license defines a first configuration where the first data storage device is visible and the first data storage capacity is available to the host processing system, and the second data storage device is not visible and the second data storage capacity is not available to the host processing system. The second license defines a second configuration where both data storage devices are and both data storage capacities are available to the host processing system.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: October 11, 2022
    Assignee: Dell Products L.P.
    Inventors: Wei G Liu, Austin Bolen
  • Patent number: 11467654
    Abstract: A power management integrated circuit (PMIC) is described for providing system management bus (SMB) isolation, along with memory sub-systems which include such a PMIC and methods of operating such devices. In one embodiment, a PMIC comprises a voltage supply input, power management circuitry, and elements of a SMB. The SMB elements can include an SMB input, an SMB hot swap controller coupled to the SMB input, one or more SMBs, and one or more SMB outputs. When integrated with a memory sub-system, one SMB output can be connected to a memory controller and another SMB output to a microcontroller. During different power states (e.g., normal or low power states), certain outputs can be isolated in order to manage communications on the SMB during the different power states of the memory sub-system using the PMIC.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Matthew D. Rowley
  • Patent number: 11463275
    Abstract: An electronic control unit (ECU) is provided. The ECU is connected to a first network in an onboard network system. The onboard network system includes the first network and a second network. In the first network, first-type frames are transmitted following a first communication protocol. In the second network, second-type frames are transmitted following a second communication protocol. The first-type frame includes first information serving as a base for the second-type frame to be transmitted to the second network, and second information indicating that the first-type frame includes information that is to be transmitted to the second network. The ECU includes a generator that generates the first-type frame following the first communication protocol, and a transmitter that transmits, to the first network, the first-type frame generated by the generator.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: October 4, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Manabu Maeda, Tomoyuki Haga, Takamitsu Sasaki, Hideki Matsushima
  • Patent number: 11461128
    Abstract: An apparatus and method are provided for managing use of capabilities. The apparatus has processing circuitry to execute instructions, and a plurality of capability storage elements accessible to the processing circuitry and arranged to store capabilities used to constrain operations performed by the processing circuitry when executing instructions. The processing circuitry is operable at a plurality of exception levels, each exception level having different software execution privilege. Further, capability configuration storage is provided to identify capability configuration information for each of the plurality of exception levels. For each exception level, the capability configuration information identifies at least whether the operations performed by the processing circuitry when executing instructions at that exception level are constrained by capabilities.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 4, 2022
    Assignee: Arm Limited
    Inventor: Graeme Peter Barnes