Patents Examined by Glenn Gossage
  • Patent number: 10909043
    Abstract: A direct memory access controller, configured to be used in a computing node of a system on chip (SoC), includes: (1) an input buffer for receiving packets of data coming from an input/output interface of the computing node; (2) a write control module for controlling writing of data extracted from each packet to a local memory of the computing node shared by at least one processor other than the direct memory access controller; and (3) an arithmetic logic unit for executing microprograms. The write control module is configured to control the execution by the arithmetic logic unit of at least one microprogram including instruction lines for arithmetic and/or logical calculation concerning only storage addresses for storing the data received by the input buffer for a reorganization of the data in the shared local memory. Optionally, at least one microprogram may be stored in a register, and at least two operating modes (e.g.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 2, 2021
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Yves Durand, Christian Bernard
  • Patent number: 10892012
    Abstract: An apparatus, vision processing unit, and method are provided for clustering motion events in a content addressable memory. A motion event is received including coordinates in an image frame that have experienced a change and a timestamp of the change. A determination is made as to whether determine whether there is a valid entry in the memory having coordinates within a predefined range of coordinates included in the motion event. In response to a determination that there is the valid entry having the coordinates within the predefined range of coordinates included in the motion event, write to the valid entry the coordinates and the timestamp in the motion event.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: January 12, 2021
    Assignee: INTEL CORPORATION
    Inventors: Turbo Majumder, Somnath Paul, Charles Augustine, Muhammad M. Khellah
  • Patent number: 10871909
    Abstract: A block management method, a memory control circuit unit and a memory storage apparatus for managing a plurality of physical blocks are provided. The method includes writing test data to a first physical block among the plurality of physical blocks, reading the test data from the first physical block among the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block; grouping the first physical block into a first block group or a second block group according to the plurality of parameters corresponding to the first physical block and a rule between the plurality of parameters and grouping of the plurality of physical blocks; establishing first and second block mapping tables; and mapping logical addresses of the first and second block mapping tables to the plurality of physical blocks belonging to the first and second block groups.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Siu-Tung Lam, Ming-Yen Lee, Kuo-Lung Lee
  • Patent number: 10866758
    Abstract: A data storage apparatus, storage medium and method for controlling the data storage apparatus are disclosed in which duplicates of a plurality of data blocks, which are stored in two or more media in a first arrangement and classified according to a plurality of pieces of dimension information, are stored into two or more other media in a second arrangement different from the first arrangement. A data block may be classified into first class data or second class data of a first dimension information or a second dimension information. A processor may store duplicates of first and third data blocks into a third medium, and duplicates of second and forth data blocks into a fourth medium. This can reduce the number of times of changing a medium, and suppress lowering in the capacity efficiency. Dimension information may be an axis of obtaining data.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: December 15, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Satoshi Iwata
  • Patent number: 10866875
    Abstract: A storage apparatus includes a controller unit and output unit. The controller receives cyclic information that is cycled within a specific group of storage apparatuses with properties close to a relevant storage apparatus. The cyclic information includes performance information of each storage apparatus in the specific group and evaluation information indicative of an evaluation result of the performance information of each storage apparatus. The controller acquires the performance information including the evaluation results, combines it with the cyclic information, and transmits the cyclic information to a storage apparatus which is a next cycling destination. A similarity level may be calculated based on configuration information and a predetermined weight. A specific group may be formed by checking whether storage apparatuses are capable of communicating with each other, so a cyclic path can be formed. The output unit may transmit performance information as information to be displayed on a user terminal.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: December 15, 2020
    Assignee: HITACHI, LTD.
    Inventors: Hibiki Saito, Tetsuya Maita, Nobuyoshi Sakai, Yuusuke Asai, Naoki Ogawa, Tatsuya Kimura
  • Patent number: 10852996
    Abstract: A slave storage is provisioned using metadata of a master B-tree and updates to references (e.g., offsets) pertaining to data operations of the master B-tree. Master-slave pairs can be used to provide data redundancy, and a master copy can include the master B-tree with references to corresponding data. When provisioning a slave copy, the master sends a B-tree copy to the slave, which stores the slave B-tree copy, allocates the necessary space on local storage, and updates respective offsets of the slave B-tree copy to point to the local storage. Data from the master can then be transferred to the slave and stored according to a note and commit process that ensures operational sequence of the data. Operations received to the master during the process can be committed to the slave copy until the slave is consistent with the master and able to take over as master in the event of a failure.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: December 1, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Jianhua Fan, Benjamin Arthur Hawks, Norbert Paul Kusters, Nachiappan Arumugam, Danny Wei, John Luther Guthrie, II
  • Patent number: 10831669
    Abstract: Systems, methods and computer program products using multi-tag storage to enable efficient data compression in caches without increasing a tag/data area overhead. One method can comprise storing compressed versions of data elements in a data array of a cache, with tags for the compressed versions respectively appended to the compressed versions as stored in the data array, and storing hashed versions of the tags in a tag array of the cache, wherein the hashed versions of the tags respectively have fewer bits than the tags. A tag block may store hashed versions of tags corresponding to first and second compressed data elements stored in a cacheline of the cache. Hashed tag entries may be compared with full versions of the tags appended to compressed versions of data elements stored in the data array to prevent false positive cache reads. A compressed identifier (CID) may be stored with the hashed versions of tags in the tag array.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prashant Jayaprakash Nair, Seokin Hong, Alper Buyuktosunoglu, Michael B. Healy, Bulent Abali
  • Patent number: 10824560
    Abstract: A data processing system and method for protecting a memory from unauthorized accesses are provided. The data processing system includes a system bus, a memory coupled to the system bus through a memory controller, and a processing core including a cache system. The memory controller is coupled to the system bus for controlling accesses to the memory that are requested by the processing core. A memory protection circuit uses one or more memory safety violation (MSV) indicators stored in out-of-bounds areas of the memory for detecting when the processing core attempts to access an out-of-bounds area of the memory. The processing core generates an error signal, such as an interrupt, when an attempt to access the out-of-bounds area is detected. The out-of-bounds area may be an unallocated area of the memory. The MSV indicator may be written to the memory by executing a flush instruction of the cache system, and may include the same number of bits as a cache line of the cache system.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Jan Hoogerbrugge, Marcel Medwed, Ventzislav Nikov, Asier Goikoetxea Yanci
  • Patent number: 10817326
    Abstract: Hypervisor-independent block-level live browse is used for directly accessing backed up virtual machine (VM) data. Hypervisor-free file-level recovery (block-level pseudo-mount) from backed up VMs also is disclosed. Backed up virtual machine (“VM”) data can be browsed without needing or using a hypervisor. Individual backed up VM files can be requested and restored to anywhere without a hypervisor and without the need to restore the rest of the backed up virtual disk. Hypervisor-agnostic VM backups can be browsed and recovered without a hypervisor and from anywhere, and individual backed up VM files can be restored to anywhere, e.g., to a different VM platform, to a non-VM environment, without restoring an entire virtual disk, and without a recovery data agent at the destination.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 27, 2020
    Assignee: Commvault Systems, Inc.
    Inventors: Henry Wallace Dornemann, Rahul S. Pawar, Amit Mitkar, Sunil Kumar Gutta, Sumedh Pramod Degaonkar, Jianwei Chen
  • Patent number: 10817354
    Abstract: A computer program product, system, and method are provided for upgrading a kernel or kernel module with a configured persistent memory. A persistent memory space is configured in the memory to store application data from applications in user mode. A kernel executing in the memory is prevented from accessing the persistent memory space. A service is called to load an updated kernel in the memory to replace the kernel, wherein the applications have access to the persistent memory space after the updated kernel is loaded. The service may comprise a kernel execution mechanism that directly loads the updated kernel into the memory without a full reboot of the computer system. An extended memory kernel service may be loaded during a boot operation to reserve the persistent memory space as an extended memory space for use by the applications and prevent the kernel from accessing the persistent memory space.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: October 27, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lior Chen, Alex Friedman, Constantine Gavrilov, Aharon Novogrodski, Alex Snast
  • Patent number: 10817415
    Abstract: A data storage device and method for operating a non-volatile memory including device based space allocation and host-based mapping table searching. In response to a write command from a host that indicates a write logical address in metadata in the write command, a controller at the device end determines a write physical address and allocates the non-volatile memory to provide a space to store write data at the write physical address. The controller transmits the write physical address to the host so the host can establish a mapping table on the host. When filling a completion queue in the host to inform the host of the finishing or completion of the write command, the controller also returns the write physical address to the completion queue for the host to update the mapping table on the host in real time. The metadata programmed at the device end is read back with the read data for read data verification at the host end.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 27, 2020
    Assignee: SHANNON SYSTEMS LTD.
    Inventor: Zhen Zhou
  • Patent number: 10809922
    Abstract: A data protection technique involves, based on a first set of policies on a first storage array, generating a second set of policies on a second storage array to track the first set. The first array maintains a first storage object, and the second array maintains a second storage object as a replica of the first storage object. The technique further includes detecting assignment of the first set of policies to the first storage object and, in response to such detection, assigning the second set of policies to the second storage object. Application of a set of storage policies to a storage object may be delayed if the storage object is a replication destination. A policy group may identify multiple data protection rules or policies, which may include a snapshot rule and/or replication rule, and a user may be prevented from directly making a rule modification to a policy group. An orphan policy group cleanup operation may be performed to delete orphan policy groups.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 20, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Tianming Zhang, Girish Sheelvant, Qi Jin, Nagasimha Haravu, Michael Zeldich, Sathish Janamanchi
  • Patent number: 10802921
    Abstract: Systems and methods for provisioning a slave copy for redundant data storage and for writing data to persistent storage in a block-based storage system using sequential operation numbers are provided. In one embodiment, the method includes maintaining a master copy and a slave copy of a data volume, the master copy including data generated by a plurality of operations having respective sequential operation numbers, receiving a write instruction for second data to be added to the master copy, and recording the second data as a note that is not readable. The method may further include sending a copy of the note from the master copy to the slave copy, committing the note to the master copy with a sequential operation number, and committing the copy of the note to the slave copy based in part on the sequential operation number. A B-tree may be created based at least in part on an offset for a write instruction associated with the second data, a length, and an operation number included in the note.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 13, 2020
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Jianhua Fan, Benjamin Arthur Hawks, Norbert Paul Kusters, Nachiappan Arumugam, Danny Wei, John Luther Guthrie
  • Patent number: 10802729
    Abstract: A data processing system comprises ownership circuitry to enforce ownership rights of memory regions within a physical memory address space. A given memory region has a given owning process specified from among a plurality of processes and independently of privilege level. The given owning process has rights to control access to the given memory region. The given owning process designates the given memory region as one of: private to the given owning process and shared between the given owning process and at least one further source of memory access requests. A given owning process may deny access to the given memory region to a process having a greater level of privilege than the given owning process. Data stored within the given memory region may be destructively overwritten, and completion of the overwriting may be tracked by overwrite tracking hardware to ensure completion of the overwriting before the new owner obtains rights to control access.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: October 13, 2020
    Assignee: ARM Limited
    Inventors: Jason Parker, Richard Roy Grisenthwaite, Andrew Christopher Rose
  • Patent number: 10795591
    Abstract: A device access system includes a memory having a supervisor memory, a processor, an input output memory management unit (IOMMU), and a supervisor. The supervisor includes a supervisor driver, which executes on the processor to allocate the supervisor memory and reserve a range of application virtual addresses. The supervisor driver programs the IOMMU to map the supervisor memory to the reserved range. A device is granted access to the reserved range, which is protected in host page table entries such that an application cannot modify data within the range. The supervisor driver configures the device to use the supervisor memory and receive a request including a virtual address and length from the application to use the device. The supervisor driver validates the request by verifying that the virtual address and length do not overlap the range reserved by the supervisor, and responsive to validating the request, submits the request to the device.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 6, 2020
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 10795592
    Abstract: An information handling system includes a processing unit that is coupled to a memory device by a communication channel. The processing unit includes a memory controller and is configured to host a basic input output system (BIOS). The memory device, which may include a dual in-line memory module (DIMM), stores serial presence detect (SPD) information. In an embodiment, the BIOS obtains the SPD information and parameters of the communication channel, such as channel impedance and channel length. In this embodiment, the BIOS uses a look-up table to determine an equalization of the communication channel based on the obtained SPD information and the obtained parameters of the communication channel, and utilizes the memory controller to set the equalization of the communication channel, such as by setting or controlling settings of transmission and reception components of the memory controller.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: October 6, 2020
    Assignee: Dell Products, L.P.
    Inventors: Bhyrav M. Mutnury, Stuart Allen Berke
  • Patent number: 10776275
    Abstract: A method comprises a cache manager receiving reference attributes associated with network data and selecting a replacement data location of a cache to store cache-line data associated with the network data. The replacement data location is selected based on the reference attributes and an order of reference states stored in a replacement stack of the cache. The stored reference states are associated with respective cached-data stored in the cache and based on reference attributes associated with respective cached-data. The reference states are stored in the replacement stack based on a set of the reference attributes and the stored reference states. In response to receiving reference attributes, the cache manager can modify a stored reference state, determine a second order of the state locations, and store a reference state in the replacement stack based on the second order. A system can comprise a network computing element having a cache, a cache manager, and a replacement stack.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Thompto, Bernard C. Drerup, Mohit S. Karve
  • Patent number: 10769063
    Abstract: Computer-implemented methods, program storage devices, and systems are provided for object copying in a computer performing parallel copying garbage collection on deques using work stealing. A method includes acquiring, for original objects in a source deque space, a destination deque space to copy the original objects to, and copying, from the source deque space to the destination deque space, any original objects in the source deque space having a reference to other ones of the original objects, or having a pre-known structure for estimating copy overhead. The method also includes registering, together with an address to copy to, any original objects in the source deque space lacking the reference to the other ones of the original objects, or lacking the pre-known structure for estimating copy overhead. The method additionally includes setting, in the source space, forwarding pointers to copied ones of the original objects in the destination deque place.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michihiro Horie, Hiroshi Horii, Kazunori Ogata
  • Patent number: 10761755
    Abstract: A method, apparatus, and computer program product for reclaiming one or more chunks in a snapshot storage space, are disclosed. The method comprises detecting one or more unused chunks in the snapshot storage space in response to a predefined trigger event, and reclaiming one or more detected unused chunks by providing the one or more detected unused chunks to a storage pool for reuse. One or more unused chunks may be detected by scanning a first mapping table that records a storage state of a plurality of chunks in the snapshot storage space, and a determination made whether the one or more detected unused chunks have been reclaimed. If the one or more detected unused chunks have not been reclaimed, the one or more detected unused chunks may be provided to the storage pool and a second mapping table updated to record a reclaiming state of the one or more unused chunks. A new snapshot may be stored using a chunk in the snapshot storage space that has not been used and has not been reclaimed yet.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: September 1, 2020
    Assignee: EMC IP Holding Company, LLC
    Inventors: Chen Gong, Junping Frank Zhao, Lester Ming Zhang, Joe Jian Liu, Denny Dengyu Wang, Walter Lei Wang
  • Patent number: 10740008
    Abstract: A data reading method includes receiving, by a controller of a memory, a read operation request carrying a first address; performing, by the controller, N read operations on the first address, and obtaining N pieces of data read by the N read operations; and determining, by the controller, whether the N pieces of data are consistent. The method further includes sending, by the controller, response information used to respond to the read operation request if the controller determines that the N pieces of data are consistent, where the response information includes any one of the N pieces of data. The controller may perform T random read operations between any two consecutive read operations of the N read operations to avoid data leakage during reading. If the N pieces of data obtained by performing the N read operations are inconsistent, the memory may send abnormal alarm information to respond to the read operation request to avoid data tampering.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 11, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mingguang Wang, Yu Liu, Jie Chen