Abstract: A dispersed storage (DS) processing unit and method for quality of service (QoS) management in a dispersed or distributed storage network (DSN) are disclosed. The method includes receiving a request to access a set of encoded data slices from a first user computing device of a plurality of user computing devices of the DSN, where the set of encoded data slices is stored in a set of storage units of the DSN, and where a first storage container of a plurality of storage containers of the DSN includes the set of storage units and supports a first group of logical storage vaults of a plurality of logical storage vaults of the DSN, and the first user computing device is affiliated with a first logical storage vault of the first group of logical storage vaults. The method further includes determining a quality of service (QoS) matrix regarding the request when QoS issues exists.

Abstract: Methods and apparatus such as a processor platform to manage a process under a memory constraint are disclosed herein. An example method includes detecting that a process is to transition from a foreground mode of operation to a background mode of operation. Without transitioning the process to the background mode of operation, a projected out of memory score is calculated. The projected out of memory score is compared to a score threshold, and the process is terminated when the projected out of memory score is greater than the score threshold. When the projected out of memory score is less than or equal to the score threshold, the process is allowed to transition to the background mode of operation. A priority adjustor may determine a projected adjustment value, for example by determining a default adjustment value, or by performing a lookup of an adjustment value currently associated with a second process operating in the background mode.

Abstract: A processing system server and methods for performing asynchronous data store operations. The server includes a processor which maintains a cache of objects in communication with the server. The processor executes an asynchronous computation to determine the value of a first object. In response to a request for the first object occurring before the asynchronous computation has determined the value of the first object, a value of the first object is returned from the cache. In response to a request for the first object occurring after the asynchronous computation has determined the value of the first object, a value of the first object determined by the asynchronous computation is returned. The asynchronous computation may comprise at least one future, such as a ListenableFuture, or at least one process or thread. Execution of an asynchronous computation may occur with a frequency correlated with how frequently the object changes or how important it is to have a current value of the object.

Abstract: A data storage method and a solid state disk (SSD) are provided. The method comprises: obtaining, by the SSD, target data; determining a target buffer for storing the target data between a first buffer and a second buffer based on a data type of the target data, wherein the first buffer is a buffer preset in a memory of an electronic device which includes the SSD, and the second buffer is an inherent buffer in the SSD; and caching the target data into the target buffer.

Abstract: Methods and apparatuses relating to memory compression and decompression are described, including a memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match. When indices for multiple sections are the same, an entry in the dictionary may be updated with the value of the section that is most recent, in the same order as in the block of data.

Abstract: A method and information handling system, including a solid state drive (SSD) memory device having NAND flash memory and an SSD controller to execute instructions of an SSD adaptive profiling engine for random access memory (RAM) cache optimization, are disclosed. The SSD controller is configured to cache a partial flash translation layer (FTL) table in RAM including look-up addresses corresponding to LBA segments in the NAND flash memory having access counts reflecting SSD I/O operations. The SSD controller is further configured to detect an outlier LBA segment having look-up addresses in the cached, partial FTL table, wherein the outlier LBA segment has an I/O access counts at a threshold level below the mean of access counts of other LBA segments represented in the partial FTL table, and to evict the LBA segment look-up address of the outlier LBA segment from the cached portion of the FTL table.

Abstract: Systems and methods for integrating the lifecycle of nonvolatile memory blocks with the transactional guarantees of a database are disclosed. One method includes creating a first fragment of a first database column in a volatile memory system, receiving a first pointer to a first block of a second non-volatile memory (NVM) system, the first block associated with the first fragment of the first database column, and populating the first block of the second non-volatile memory system using the first pointer. The method further includes committing the first block of the second non-volatile memory system and associating a first block identifier of the first block of the second non-volatile memory system with the first fragment of the first database column, while blocking creation of a database savepoint, and then unblocking creation of the database savepoint. A block key associated with a first fragment may comprise various identifiers such as block, column, table and partition identifiers.

Abstract: A computer-implemented method and a system for ensuring right-to-erasure compliance during data recovery are disclosed. The method may include intercepting a request to perform a recovery process to restore backup data, automatically comparing a backup image of requested data with a record of right-to-erasure orders, and determining, based on the comparison, that the backup image includes individual data related to at least one right-to-erasure order. The record of right-to-erasure orders may include at least one of an identity of an individual, at least one creation and/or execution date of a right-to-erasure order, and/or a list of backup images associated with a right-to-erasure order. The method may further include erasing the individual data to comply with the at least one right-to-erasure order, recording the erasure of the individual data in an audit log, and completing the recovery process for the requested data.

Abstract: A data storage device and a method of operating the same are provided. The data storage device includes a first non-volatile memory device, a second non-volatile memory device, and a management module. The management module receives, from a host, an external multi-access command including first and second physical addresses which are different from each other, generates and sends a first access command including the first physical address to the first non-volatile memory device, and generates and sends a second access command including the second physical address to the second non-volatile memory device. The data management module performs operations on the first and second non-volatile memory devices based on the first and second access commands and the first and second physical addresses, respectively. The data storage device may be a solid state drive (SSD) including NAND flash memory, and the multi-access command may be a multi-write, multi-read, or multi-erase command.

Abstract: A circuit includes a memory and an address generator configured to generate a write address signal and a read address signal, where the write address signal has a first delay relative to the read address signal. The memory is configured to receive a first plurality of write addresses, from the write address signal, including a first plurality of addresses of the memory in a first order, and write, to the first plurality of write addresses, a first plurality of data words during a first time period. The memory is further configured to receive a first plurality of read addresses, from the read address signal, including the first plurality of addresses in a second order, and read, from the first plurality of read addresses, the first plurality of data words during a second time period. The first and second time periods partially overlap.

Abstract: Systems, apparatuses, and methods for implementing virtualized process isolation are disclosed. A system includes a kernel and multiple guest virtual machines (VMs) executing on the system's processing hardware. Each guest VM includes a vShim layer for managing kernel accesses to user space and guest accesses to kernel space. The vShim layer also maintains a set of page tables separate from the kernel page tables. In one embodiment, data in the user space is encrypted and the kernel goes through the vShim layer to access user space data. When the kernel attempts to access a user space address, the kernel exits and the vShim layer is launched to process the request. If the kernel has permission to access the user space address, the vShim layer copies the data to a region in kernel space and then returns execution to the kernel. The vShim layer prevents the kernel from accessing the user space address if the kernel does not have permission to access the user space address.

Abstract: A processor may include a programmable memory prefetcher that includes a programmable hardware prefetch engine and a prefetch engine control register.

Abstract: Apparatuses and methods related to memory bank power coordination in a memory device are disclosed. A method for memory bank power coordination may include concurrently performing a memory operation by a threshold number of memory regions, such as banks or subarrays, and executing a command to cause a power budget operation associated with the memory operation to be performed, based at least in part on information stored in a budget area, such as a register. The threshold number of memory regions may be set based at least in part on a threshold power consumption value, and the number of memory regions to concurrently perform an operation may be controlled by a bank arbiter. A counter having a value representing the threshold number of memory regions may be decremented while performing an operation, or incremented upon completion of an operation, associated with one of the memory regions. A number of the memory regions may be selected to perform a processing-in-memory (PIM) operation.

Abstract: A processing system server, computer program product, and methods for performing asynchronous data store operations. The server includes a processor which maintains a cache of objects in memory of the server. The processor executes an asynchronous computation to determine the value of an object. In response to receiving a request for the object occurring before the asynchronous computation has determined the value of the object, a value of the object is returned from the cache. In response to receiving a request for the object occurring after the asynchronous computation has determined the value of the object, a value of the object determined by the asynchronous computation is returned. The asynchronous computation may comprise at least one future, such as a ListenableFuture, or a process or thread. The asynchronous computation may determine the value of the object by querying at least one additional server.

Abstract: A semiconductor device that writes, into respective memory spaces of a plurality of separate memories constituting a search memory mat, an entry address corresponding to key data to be written. In this semiconductor device, pieces of divided data are assigned respectively to the separate memories, and, by employing each divided data as an address, entry addresses corresponding to the divided data are written sequentially into memory spaces specified by memory addresses of the separate memories (first writing process). In this first writing process, if another entry address is already written in an accessed memory space, no entry address is written into that memory space. If an entry address corresponding to a single one of the plurality of pieces of divided data is successfully written into a memory space, the first writing process is ended. Second write processing to a verification memory may also be performed. Key data may be written to a backup memory when a whole collision occurs.

Abstract: A memory storage device, a memory control circuit unit and a data storage method for a rewritable non-volatile memory module are disclosed. The method includes: receiving first data; mapping a logical unit of the first data to a first physical unit in a first management unit and not storing the first data to the rewritable nonvolatile memory module if a data content of the first data is identical to a data content of second data stored in the first physical unit. The method also includes storing logical-to-physical bit map information to a second physical unit in the first management unit, wherein the logical-to-physical bit map information corresponds to at least one logical-to-physical mapping table and is configured for identifying valid data in the first management unit. Identifiers or symbols of data content may be compared to determine if first and second data are identical.

Abstract: A secure element and method for backup of data stored in a non-volatile memory of the secure element. The method for backup of data includes de-fragmenting an area of the non-volatile memory so as to form, in the area, an occupied region and a free region. The method further includes compressing the portion of data contained in the occupied region, after de-fragmentation, and compressing the contents of the free region using a compression algorithm that is different from the one used for compressing the portion of data contained in the occupied region. In one embodiment, the occupied region is compressed using a dictionary, and the free region is compressed by applying run-length encoding (RLE). The method also includes generating a backup image containing the compressed portion of data and the compressed contents of the free region, and writing the backup image into the nonvolatile memory. The area may contain objects to be handled by a program coded in an object language.

Abstract: To ensure that the contents of a non-volatile memory device cache may be relied upon as accurately reflecting data stored on disk storage, it may be determined whether the cache contents and/or disk contents are modified during a power transition, causing cache contents to no longer accurately reflect data stored in disk storage. The cache device may be removable from the computer, and unexpected removal of the cache device may cause cache contents to no longer accurately reflect data stored in disk storage. Cache metadata may be managed during normal operations and across power transitions, ensuring that cache metadata may be efficiently accessed and reliably saved and restored across power transitions. A state of a log used by a file system may be determined prior to and subsequent to reboot of an operating system in order to determine whether data stored on a cache device may be reliably used.

Abstract: A computer implemented method, system, and computer program product for data replication and restoration. The method includes downloading a plurality of hashes from a cloud corresponding to a set of backed up hashes for a set of chunks, wherein each chunk corresponds to a portion of a LUN at a production site at a point in time, determining a second plurality of hashes for the LUN at the production site, and comparing each of the second plurality of hashes for the LUN at the production site with the plurality of hashes downloaded from the cloud. The method further includes downloading data corresponding to one or more non-matching hashes from the cloud, and restoring the data that was downloaded to the LUN on the production site. Once the LUN has been validated, interception of IOs by a splitter may be stopped.

Abstract: A storage controller includes a processor and a memory to store first management information indicating data writing to each of a plurality of logical blocks, corresponding to a plurality of physical blocks of a storage device. The processor is configured to receive a write request to write data to a first logical block and assign a first physical block to the first logical block. The processor is also configured to record in the first management information that data has been written in the first logical block, identify a second logical block in which data has been written, write the addresses of the plurality of physical blocks as second management information, read an address of a second physical block assigned to the second logical block from the second management information, and release the second physical block.