Abstract: A thermal package for electronic components, such as semiconducting chips, is disclosed. Each chip is connected to a printed circuit interconnect substrate by flexible Tape Automated Bonding leads, and a pliant foam pad is attached to the surface of each chip adjacent the printed circuit interconnect substrate. A heat spreader is attached to the major surface of each chip above the printed circuit interconnect substrate. The heat exchangers are mounted to a support plate that is disposed above the printed circuit interconnect substrate. An external heat exchanger is attached to the exposed major surface of the support plate. The heat spreaders are secured to the support plate so they are urged upwards against the external heat sink. Heat generated by the chips is conducted through the heat spreaders to the external heat sink. Conductors on the support plate and the heat sink are used to provide a voltage to the chips.

Abstract: A mounting pad means for use in combination with solid-state semiconductive translating devices and including a base pad with flange walls extending from said base pad, and with device mounting pad means being secured to the surface of the base pad and comprising a thin layer of silicone base rubber. The base pad an flange walls are formed of a generally rigid laminate with a core having outer metal foil layers disposed on opposite surfaces thereof, and wherein the core is composed of a thin layer of silicone base rubber.

Abstract: Metal contacts and interconnections for integrated circuits utilize copper as the primary conductor, with the copper being totally encased in refractory metal layers on both top and bottom surfaces and also sidewalls. The contact hole in silicon oxide may be filled with a plug of refractory metal before the copper is deposited, or the first refractory metal layer may be conformally deposited to coat the sidewalls of the hole.

Abstract: A semiconductor integrated circuit of standard-cell type or gate-array type includes a plurality of first cells arranged in a plurality of parallel lines, the first cells having first wirings for supplying power, the first wirings being extended over a plurality of the first cells arranged in the same line in a direction of the same line of the first cells, a second cell disposed in the neighbourhood of some of the first cells and having a dimension larger than the first cells, said second cell having second wirings on a periphery thereof to surround circuit portion of the second cell and means for connecting the second wirings with the first wirings in the first cells in the neighbourhood of the second cell.

Abstract: In a semicondur device comprising a semiconductor element, a pair of electrodes provided on the opposite sides of the semiconductor element, and a cylindrical member provided to surround the semiconductor element and to be in engagement with the pair of electrodes, each of the electrodes has a thread portion on its outer perphery, and the cylindrical member has a thread portion on its inner periheral surface screwed onto each of the thread portions of the electrodes, thereby to provide a hermetic seal for the semiconductor element.

Abstract: In a semiconductor array having a plastic casing and a cooling portion which is at least partly not embedded in the plastic, an insulating portion is provided which is designed to slide onto the cooling portion and to provide at least partial electrical insulation of the cooling portion when slid on.

Abstract: A hybrid thick film chip device comprising two or more electrical components mounted in parallel on a single substrate and having common terminals for electrical interconnection to other devices or to circuit boards or the like. In one embodiment, the components comprise a resistor and a capacitor disposed on one surface of the substrate. In another embodiment the resistor is on one surface of the substrate and the capacitor is on the opposite surface. The device is particularly advantageous in forming networks.

Abstract: In a lateral transistor having a first semiconductor region of one conductivity type, and an emitter region and a collector region both having the opposite conductivity type and disposed in the first semiconductor region; a second semiconductor region having the opposite conductivity type is disposed opposite to the emitter region with respect to the collector region. The thus obtained lateral transistor has a characteristic that a current flowing to the substrate is prevented under a saturation operation state and is suitably used to form, e.g., a current-mirror type constant-current circuit constituting a switching device having improved threshold characteristics.

Abstract: A lead frame for mounting a semiconductor chip in an integrated circuit package incorporates a deformation absorbing member as an integral part of the paddle support arm so that the initial, desired physical and electrical characteristics are unaltered after a forming operation such as paddle downsetting.

Abstract: The invention is a semiconductor device assembly and method of making the same. A mounting plate has positioning means for positioning the plate relative to a header, a first mounting surface of the plate is attached to the header and a semiconductor device is attached to a second mounting surface of the mounting plate. The assembly is made by forming the mounting plate, positioning the mounting plate relative to the header by the positioning means, attaching the first mounting surface to the header and the semiconductor device to the second mounting surface. Another method of making the assembly is by defining and etching a mounting plate and attaching the first mounting surface to the header and the semiconductor device to the second mounting surface. This assembly and process provides an efficient means for mounting semiconductor devices and in particular electro-optic devices such as lasers.

Abstract: An electronic assembly having a semiconductor device back bonded to a first lead frame. An adhesive insulative tape is placed on the first lead frame and the device. A second lead frame is mounted on the adhesive tape. Electrical contacts by wire bonds are established between the device and the first and second lead frames.

Abstract: A plastic semiconductor package suitable for high frequency operation includes an internal ground plane connected to a ground ring formed on the packaged semiconductor device. The ground plane is included as a portion of a lead frame strip adjacent to the individual lead frames. The ground plane is first folded underneath the paddle support of the lead frame, and the semiconductor die subsequently mounted on the paddle. The ground plane includes a plurality of bumps which protect upward between adjacent lead fingers of the lead frame when the ground frame is folded. A ground frame on the semiconductor die is connected to the bumps, and the signal bonding pads connected to the lead fingers, typically by wire or tape bonding. The package is then encapsulated in plastic by conventional means, and the package trimmed to its final desired configuration.

Abstract: A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnection metallization which serves to connect various chips and chip pads within the interconnection pads disposed on the chips. A significant advantage of the packaging method and configuration of the present invention is the ability for the polymer film to be removed. This significantly improves testability and effectively provides wafer scale integration circuit packages which are free of problems associated with yield and testability.

Abstract: Construction of a novel multilayer conductive interconnection for an integrated circuit having more than one conductive layer is disclosed comprising a lower barrier layer which may be in contact with an underlying silicon substrate and comprising a material selected from the class consisting of TiW and TiN; an intermediate layer of conductive metal such as an aluminum base metal; and an upper barrier layer which may be in contact with a second aluminum base metal layer and which is selected from the class consisting of TiW, TiN, MoSi.sub.x and TaSi where x equals 2 or more.

Abstract: A semiconductor device with a circuit including a fuse wiring which comprises a step portion provided on a first insulating film which is provided on a substrate; a fuse wiring provided on the step portion via a second insulating film so that the central portion of the fuse wiring traverses the step portion; the central portion of the fuse wiring being positioned at a higher position than both the side portions thereof by a distance equal to the thickness of the step portion; and a third insulating film having a flat surface provided on the fuse wiring.

Abstract: At least one annular region (11,12, . . . ) extends around an active device region (10) and is located within the spread of a depletion layer (25) from a reverse-biased p-n junction (20) formed by the device region (10) to increase the breakdown voltage of the junction (20). The device region (10) and/or at least one inner annular region (11,12, . . . ) includes at least one shallower portion (10b,11b, . . . ) which extends laterally outwards from a deep portion (10a,11a,12a, . . . ) and faces the surrounding annular region to change the spacing and depth relationship of these regions. This permits high punch-through voltages to be achieved between the regions (10,11,12, . . . ) while reducing peak fields at the bottom outer corners of the regions (10,11,12, . . . ). Inwardly-extending shallow portions (11c,12c, . . . ) may also be included. The shallow portions (10b,11b,11c,12c . . .

Abstract: An integrated circuit devicer package includes a rigid frame and flexible tape assembly having wire leads between the die attach pad, conductive lead fingers, and the I.C. chip. A dam structure prevents resin flow to ensure proper wire bonding and a wedge prevents electrical shorting. A recognition pattern enables precise wire bonding. A epoxy molding compound is interposed in cavities formed in a Kapton layer to preclude delamination.

Abstract: Special absorbers or getters are incorporated in hermetically sealed electronic circuits with organic components, for example, with parylene passivations, silver conductive adhesives, and sealing materials. The getter material, preferably BaAl.sub.4, is dispersed as an extremely fine-grained powder in a gas permeable, inert silicone rubber having a composition which varies according to the application. In short- or long-term thermal loading, for example in power hybrid systems, the proposed getters make it possible to intercept any corrosive fission products such as CO, CO.sub.2, NO/NO.sub.2, and water of reaction to avoid premature aging.

Abstract: A power semiconductor module includes a multi-layered substrate formed of a first ceramic bottom plate, at least one second ceramic plate disposed above and parallel to the first ceramic bottom plate, a metal foil in the form of a textured metallization located between and directly bonded to the ceramic plates, the second ceramic plate having cutouts formed therein, and assembly elements soldered in the cutouts.

Abstract: A complementary Silicon-On-Insulator (SOI) Lateral Insulated Gate Rectifier (LIGR) is fabricated in a monocrystalline silicon layer provided on a major surface of a substantially insulating substrate. The monocrystalline silicon layer includes a number of adjacent, doped coplanar layer portions, with the complementary SOI LIGR device being formed of adjacent, contacting layer portions forming two complementary LIGR elements with a common source region. The common source region, as well as both of the drain regions of the device, are composed of regions of both the first and second conductivity types. In this manner, a simple, easily fabricated, balanced, high performance complementary LIGR structure is obtained in which undesired substrate currents are substantially eliminated.