Abstract: An electronic assembly having a semiconductor device back bonded to a first lead frame. An adhesive insulative tape is placed on the first lead frame and the device. A second lead frame is mounted on the adhesive tape. Electrical contacts by wire bonds are established between the device and the first and second lead frames.

Abstract: A plastic semiconductor package suitable for high frequency operation includes an internal ground plane connected to a ground ring formed on the packaged semiconductor device. The ground plane is included as a portion of a lead frame strip adjacent to the individual lead frames. The ground plane is first folded underneath the paddle support of the lead frame, and the semiconductor die subsequently mounted on the paddle. The ground plane includes a plurality of bumps which protect upward between adjacent lead fingers of the lead frame when the ground frame is folded. A ground frame on the semiconductor die is connected to the bumps, and the signal bonding pads connected to the lead fingers, typically by wire or tape bonding. The package is then encapsulated in plastic by conventional means, and the package trimmed to its final desired configuration.

Abstract: A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnection metallization which serves to connect various chips and chip pads within the interconnection pads disposed on the chips. A significant advantage of the packaging method and configuration of the present invention is the ability for the polymer film to be removed. This significantly improves testability and effectively provides wafer scale integration circuit packages which are free of problems associated with yield and testability.

Abstract: Construction of a novel multilayer conductive interconnection for an integrated circuit having more than one conductive layer is disclosed comprising a lower barrier layer which may be in contact with an underlying silicon substrate and comprising a material selected from the class consisting of TiW and TiN; an intermediate layer of conductive metal such as an aluminum base metal; and an upper barrier layer which may be in contact with a second aluminum base metal layer and which is selected from the class consisting of TiW, TiN, MoSi.sub.x and TaSi where x equals 2 or more.

Abstract: A semiconductor device with a circuit including a fuse wiring which comprises a step portion provided on a first insulating film which is provided on a substrate; a fuse wiring provided on the step portion via a second insulating film so that the central portion of the fuse wiring traverses the step portion; the central portion of the fuse wiring being positioned at a higher position than both the side portions thereof by a distance equal to the thickness of the step portion; and a third insulating film having a flat surface provided on the fuse wiring.

Abstract: At least one annular region (11,12, . . . ) extends around an active device region (10) and is located within the spread of a depletion layer (25) from a reverse-biased p-n junction (20) formed by the device region (10) to increase the breakdown voltage of the junction (20). The device region (10) and/or at least one inner annular region (11,12, . . . ) includes at least one shallower portion (10b,11b, . . . ) which extends laterally outwards from a deep portion (10a,11a,12a, . . . ) and faces the surrounding annular region to change the spacing and depth relationship of these regions. This permits high punch-through voltages to be achieved between the regions (10,11,12, . . . ) while reducing peak fields at the bottom outer corners of the regions (10,11,12, . . . ). Inwardly-extending shallow portions (11c,12c, . . . ) may also be included. The shallow portions (10b,11b,11c,12c . . .

Abstract: An integrated circuit devicer package includes a rigid frame and flexible tape assembly having wire leads between the die attach pad, conductive lead fingers, and the I.C. chip. A dam structure prevents resin flow to ensure proper wire bonding and a wedge prevents electrical shorting. A recognition pattern enables precise wire bonding. A epoxy molding compound is interposed in cavities formed in a Kapton layer to preclude delamination.

Abstract: Special absorbers or getters are incorporated in hermetically sealed electronic circuits with organic components, for example, with parylene passivations, silver conductive adhesives, and sealing materials. The getter material, preferably BaAl.sub.4, is dispersed as an extremely fine-grained powder in a gas permeable, inert silicone rubber having a composition which varies according to the application. In short- or long-term thermal loading, for example in power hybrid systems, the proposed getters make it possible to intercept any corrosive fission products such as CO, CO.sub.2, NO/NO.sub.2, and water of reaction to avoid premature aging.

Abstract: A power semiconductor module includes a multi-layered substrate formed of a first ceramic bottom plate, at least one second ceramic plate disposed above and parallel to the first ceramic bottom plate, a metal foil in the form of a textured metallization located between and directly bonded to the ceramic plates, the second ceramic plate having cutouts formed therein, and assembly elements soldered in the cutouts.

Abstract: A complementary Silicon-On-Insulator (SOI) Lateral Insulated Gate Rectifier (LIGR) is fabricated in a monocrystalline silicon layer provided on a major surface of a substantially insulating substrate. The monocrystalline silicon layer includes a number of adjacent, doped coplanar layer portions, with the complementary SOI LIGR device being formed of adjacent, contacting layer portions forming two complementary LIGR elements with a common source region. The common source region, as well as both of the drain regions of the device, are composed of regions of both the first and second conductivity types. In this manner, a simple, easily fabricated, balanced, high performance complementary LIGR structure is obtained in which undesired substrate currents are substantially eliminated.

Abstract: A thermal protective device for semiconductor devices and the like comprises a housing of electrically insulative plastic material made in cup form having at the open end a seat for lodging a bimetallic disc and means for applying the cup to the semiconductor device with the bimetallic disc in direct heat exchange relation therewith. One or more electric terminals is incorporated in the housing at the time of molding and is connected in power supply circuits of the semiconductor device and/or alarm and signaling circuits. The bimetallic disc acts on said electric terminals so as to interrupt or modify the power supply to the semiconductor device or to actuate an alarm signal.

Abstract: A peaking capacitor for use with a differential input stage in an integrated circuit. The stage includes emitter degeneration resistors and a peaking capacitor coupled between the emitters. The capacitor is formed of MOS capacitors located over thinned oxide portions that lie within the confines of doped regions forming PN junctions with the semiconductor substrate. The doped regions are spaced apart by a distance that will result in depletion region reach-through at a voltage that is lower than the thinned oxide breakdown voltage. Thus, the structure is self-protecting and therefore resistant to electrostatic discharge damage. The capacitor that is formed has a value that is determined accurately by the area of the thinned oxide. It also has a low stray capacitance which makes it useful as a peaking capacitor.

Abstract: Heat producing components such as semiconductor chips are arranged with a major heat transfer surface at an angle of about 10 degrees to the vertical. A film of a dielectric liquid flows downward across this surface from a catch pan located above the component. The film evaporates and thereby removes heat from the component and the vapor is condensed and returned to the catch pan. The angle of the heat transfer surface helps to prevent separation of the film as it flows downward across the surface. In one embodiment the slanting surface is formed by slanted grooves in an otherwise vertical surface of a semiconductor chip. In other embodiments, a slanting surface or a vertical surface with slanting grooves is formed in place on the chip or is formed separately and attached to the chip or is formed as part of a local enclosure for the chip.

Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer formed on the substrate, a conductive body formed on the first insulating layer, a second insulating layer formed on the first insulating layer and the conductive body and having a contact hole formed at a contact area to reach the conductive body, and a first conductive layer formed on the second insulating layer and the conductive body. The conductive body has a conductive member formed on the first insulating layer in the contact area, and a second conductive layer formed on the first insulating layer and the conductive member.

Abstract: A lead frame has a plurality of metallic heat radiating plates, leads connected to each metallic heat radiating plate, other leads separated from the metallic heat radiating plates and a common insulator web attached to the metallic heat radiating plates. When the lead frame is placed in the cavity of a mold, the metallic heat radiating plates are correctly positioned in the mold cavity by the insulating web and the connected leads. By effecting a resin molding under this condition, the metallic heat radiating plates are molded in resin such that a layer of resin with a uniform thickness cover the back surface of the respective metallic heat radiating plates.

Abstract: For uniform distribution of power to integrated circuit chips arranged on a substrate, a multichip package comprises a plurality of power feed contact pads on an outer portion of the substrate for coupling to an external power source and a pair of power feed pins on an inner portion of the substrate for coupling to the external power source. A conductive means is provided on the substrate for distributing power from the power feed contact pads and the power feed pins to the integrated circuit chips.

Abstract: A semiconductor device provided with signal lines which connect a chip, provided at a top portion of a package, with external terminals provided at a bottom portion of the package. The signal lines have portions formed along side surfaces of the package. Ground surfaces are formed at predetermined distances on two sides of the high-speed signal lines. A coplanar waveguide is formed by the high-speed signal lines and the ground surfaces, so the impedance of vertical portions of the high-speed signal lines is matched to the circuits connected thereto.

Abstract: An electronic device made by the method of connecting a circuit member (18) having a plurality of laterally spaced electrically conductive terminals (20) to a substrate (12) including a mounting surface (14) having a plurality of laterally spaced conductive paths (16) wherein the method includes the steps of applying an adhesive (22) including a resin having a twenty to twenty-five percent by weight content of conductive metal particles over the mounting surface (14) of the substrate (12) having the conductive paths (16) wherein the resin is a dielectric preventing conductivity between the spaced metal particles therein and mounting the circuit member (18) on the adhesive (22) while vertically aligning the conductive terminals (20) over preselected ones of the conductive paths (16).