Abstract: A method, comprising: retrieving a VDG definition; processing the VDG definition to identify a primary storage system and one or more secondary storage systems; detecting a consistency formation event; transmitting a first instruction to initialize one or more data structures for a first snapshot of a volume that is stored in the primary storage system; transmitting, to each of the secondary storage systems, a respective second instruction to initialize one or more data structures for a respective snapshot of a copy of the volume that is stored in that secondary storage system; suspending servicing of input-output (I/O) by the primary storage system; transmitting to the primary storage system a third instruction to complete the first snapshot of the volume; transmitting to each of the secondary storage systems a respective fourth instruction to complete a respective snapshot of the copy of the volume; and resuming servicing of I/O.

Abstract: A system and method for managing tables in a storage system is described.

Abstract: A method for direct addressing in virtual addressed systems includes obtaining, by a system including a processor and in response to receiving a request to access a data item stored by a storage system, address information for the data item from a data structure. The address information includes a first physical storage address of the storage system, a first generation number associated the first physical storage address in the data structure, and an address redirector. The method also includes accessing, by the system and in response to the first generation number being determined to be different from a second generation number associated with the first physical storage address, the data item at a second physical storage address of the storage system instead of the first physical storage address, the second physical storage address being determined based on the address redirector.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.

Abstract: A data storage device includes a memory device and a memory controller. In response to a write command received from a host device, the memory controller performs a write operation to write predetermined data into the memory device. In the write operation, the memory controller selects one from multiple superblocks as a first target superblock of the write operation and sequentially writes the portions of the predetermined data into the pages of the first target superblock in a cyclic manner among memory dies according to an order of plane indices. Each memory die includes at least a first plane and a second plane. In the write operation corresponding to the predetermined data, corresponding write operations performed on a first page on the first plane of all memory dies are earlier than corresponding write operations performed on a first page on the second plane of all memory dies.

Abstract: A processor for performing a predetermined computational operation in which one or multiple data element(s) is/are used to determine a result. The processor includes one or more processor core(s) and at least one buffer memory, connectable to a main memory, and if the main memory is connected, it is designed to access the main memory. Each processor core is designed to execute instructions. The at least one buffer memory includes a calculation circuit which is designed to perform the computational operation in response to an execution signal if the one or the multiple data element(s) is/are stored in the buffer memory, the result being stored in the buffer memory. The processor is designed to perform the computational operation optionally using one of the processor cores with the aid of the instructions or to perform it in the at least one buffer memory using the respective calculation circuit.

Abstract: In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.

Abstract: A storage device, including a printed circuit board including a connector including a plurality of pins capable of being coupled to an external host device, a controller socket, a first slot, a second slot, a third slot, and a fourth slot; a first universal flash storage (UFS) device, a second UFS device, a third UFS device, and a fourth UFS device, wherein each UFS device of the first to fourth UFS devices is removably installed in a corresponding slot of the first to fourth slots; and a storage controller mounted in the controller socket, and configured to control the first to fourth UFS devices, wherein the first UFS device and the second UFS device are configured to communicate with the storage controller through a first channel, and the third UFS device and the fourth UFS device are configured to communicate with the storage controller through a second channel.

Abstract: An operation method of a host device configured to control a storage device includes receiving initial mapping information from the storage device, performing initial migration based on the initial mapping information such that source data present in a first region of the storage device migrate to a second region, receiving first dirty information about first dirty data of the source data from the storage device, performing first migration on the first dirty data based on the first dirty information, receiving second dirty information about second dirty data of the source data from the storage device, and performing second migration on the second dirty data based on the second dirty information, and a size of the first dirty information is different from a size of the second dirty information.

Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

Abstract: Methods, systems, and devices for distributed power up for a memory system are described. The method may include a memory system receiving, from a host system, a command to initialize a set of memory devices included in a memory system. Upon receiving the command, the memory system may select a first memory device from the set of memory devices and read, from a second memory device in a controller separate from the set of memory devices, a first operational parameter corresponding to the first memory device. The memory system may then read, from the first memory device, a set of second operational parameters, each second operational parameter of the set of second operational parameters corresponding to a respective memory device of the set of memory devices.

Abstract: An autonomous compute storage device system includes a computing device and a storage device that is coupled to the computing device. The storage device identifies a storage operation for a storage subsystem that is included in the storage device and, in response, performs the storage operation and stores data in a memory subsystem that is accessible to the storage device as part of the performance of the storage operation. If the storage device determines that an autonomous compute signature matches the data that was stored in the memory subsystem, it executes an autonomous compute application to perform compute operations that are associated with the data that was stored in the memory subsystem and generate at least one compute operation result.

Abstract: A memory system includes a memory device including a first memory block used for power-loss data protection and a controller coupled to the memory device. The controller includes a hardware layer and a firmware layer. The hardware layer checks whether at least one write data entry belongs to a programmable range in the memory device after power loss occurs, determines whether a logical address associated with the at least one write data entry is repeated, and programs the at least one write data entry in the first memory block.

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

Abstract: In at least one embodiment, processing can include: recording, in a metadata (MD) log, a metadata (MD) update to a MD page having a logical address LA1; flushing MD updates, including the MD update, from the MD log; applying at least the MD update to the MD page to generate an updated version; storing the updated version of the MD page at a storage location PA2 different from a first location of the MD page prior to updating; recording, in a translation table (TT) log, a TT update that updates entry E1 of a TT to map LA1 of the MD page to PA2 rather than the first location; flushing TT updates from the TT log; applying at least the TT update to the TT to generate an updated version; and storing the updated TT version at a storage location different from a prior location of the TT prior to updating.

Abstract: A frontend interface of a controller according to the present invention includes a plurality of corresponding queueing interfaces for each processor of the controller, and an enqueueing destination of a host I/O command can be switched in response to an instruction from a processor. When a controller OS restarts, the controller waits for completion of a host I/O and executes controller blocking and restarting during setup. Therefore, to determine whether or not this process is possible, the processor gives an instruction to switch a queue and waits until a switch source queue is empty.

Abstract: Disclosed in implementations of the present disclosure include memory controllers and operating methods thereof, memory systems, and electronic devices. The memory controller is coupled to a memory. In one example, the operating method includes: determining whether write commands for the memory are continuous, and generating a first determination result; and entering a bypass write mode when the first determination result indicates that the write commands are continuous, wherein, in the bypass write mode, the memory controller updates a first mapping relationship between a logical address and a physical address of buffered data. Other examples are disclosed.

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

Abstract: A storage device may select N number of candidate memory blocks among a plurality of memory blocks according to whether a target operation is garbage collection or wear leveling. The storage device may determine one or more victim memory blocks for the target operation among the candidate memory blocks, on the basis of a deviation in a reference factor among the candidate memory blocks.