Patents Examined by Gurtej Bansal
  • Patent number: 10545685
    Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kulachet Tanpairoj, Sebastien Andre Jean, Kishore Kumar Muchherla, Ashutosh Malshe, Jianmin Huang
  • Patent number: 10545688
    Abstract: Remote copy operations are performed to copy data from a primary storage controller to a secondary storage controller, wherein input/output (I/O) requests are received at the primary storage controller from a host both via a bus interface and a network interface while the remote copy operations are in progress, and wherein consistency groups are formed during the remote copy operations to copy the data consistently. Quiescing of I/O operations performed via the bus interface are performed while a current consistency group is being replaced by a next consistency group during the remote copy operations.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Ward, Matthew J. Kalos, Joshua J. Crawford, Carol S. Mellgren, Matthew R. Craig
  • Patent number: 10540287
    Abstract: Apparatuses and methods of manufacturing same, systems, and methods for a spatial memory streaming (SMS) prefetch engine are described. In one aspect, the SMS prefetch engine includes a pattern history table (PHT), which has a table in which each entry has an offset list field comprising sub-fields for offset values from a base offset value within a region and a per-offset confidence field comprising sub-fields for per-offset confidence levels corresponding to each offset value. When a PHT entry is activated, the per-offset confidence values corresponding to each offset value in the offset list field of the PHT entry are updated by matching current accesses to the stored offset values in the offset list field of the activated PHT entry. Continuous learning may be provided to the SMS engine at least by the per-offset confidence levels.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: January 21, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Edward A Brekelbaum, Arun Radhakrishnan
  • Patent number: 10540343
    Abstract: System and methods for detecting events based on data object attributes in a storage system are described.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: January 21, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: John Colgrove, Joseph S. Hasbani, John Martin Hayes, Ethan L. Miller, Cary A. Sandvig
  • Patent number: 10534723
    Abstract: A system, method and computer program product are provided for conditionally eliminating a memory read request. In use, a memory read request is identified. Additionally, it is determined whether the memory read request is an unnecessary memory read request. Further, the memory read request is conditionally eliminated, based on the determination.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 14, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Nikhil Tripathi, Venky Ramachandran, Malay Haldar, Sumit Roy, Anmol Mathur, Abhishek Roy, Mohit Kumar
  • Patent number: 10521154
    Abstract: A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; switching the interface to a Single SPI mode in response to the write command and the AUDPD configuration bit being set; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: December 31, 2019
    Assignee: Adesto Technologies Corporation
    Inventor: Bard M. Pedersen
  • Patent number: 10509724
    Abstract: Implementations of this disclosure are directed to systems, methods and media for assessing the status of data being stored in distributed, cached databases that includes retrieving, from a data cache, variables which include a cache loss indicator and a non-null value. The variables are analyzed to determine a state of the cache loss indicator. If the cache loss indicator indicates an intentional cache loss state, the cache loss indicator is removed and the non-null value is provided to an application. Otherwise, a cache restore process is initiated.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 17, 2019
    Assignee: MZ IP HOLDINGS, LLC
    Inventors: Ajk Palikuqi, Garth Gillespie, Arya Bondarian, Jai Kim
  • Patent number: 10506042
    Abstract: A storage system includes a storage unit having a plurality of routing circuits electrically networked with each other, each of the routing circuits being locally connected to a plurality of node modules, each of which includes nonvolatile memory, the plurality of node modules forming at least first and second storage regions, and a plurality of connection units, each connected to one or more of the routing circuits, and access the first and second storage regions through one or more of the routing circuits in accordance with a command. When one of the connection units receives a command to write second data into the first storage region while first data are being read out from the first storage region, said one of the connection units writes the second data into both the first and second storage regions.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: December 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Ooba, Mototaka Kanematsu, Kenji Takahashi
  • Patent number: 10496554
    Abstract: A system on chip, comprising a processing unit for executing processes, a memory unit, and a memory control unit connected between the processing unit and the memory unit, is described. The memory control unit allocates a memory region to a process. The memory control unit comprises a process activity counter which counts a duration of the process or transactions by the process to or from the memory region and which maintains a process activity count representing the counted duration of the process or the counted transactions to or from the memory region. The memory control unit disables the memory region in response to the process activity count exceeding a maximum process activity count. Notably, it blocks the memory region against further transactions by the process and against transactions by any other processes. A method of operating a system on chip is also described.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: December 3, 2019
    Assignee: NXP USA, INC.
    Inventors: Michael Johnston, Alan Devine, Alistair Paul Robertson, Manfred Thanner
  • Patent number: 10496317
    Abstract: A memory system may include a first memory having a first operating speed, and a second memory having a second operating speed which is different from the first operating speed. A compression device may compress data of the first memory, and may transfer the compressed data to the second memory. The compression device may select a compression scheme among a plurality of compression schemes based on at least one characteristic of the data of the first memory and a data processing combination selected among a plurality of data processing combinations between a series of data processing units of the first memory and a series of data processing units of the second memory, and may compress the data of the first memory according to the selected compression scheme.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 3, 2019
    Assignee: SK hynix Inc.
    Inventors: Yong-Kee Kwon, Yong-Ju Kim, Hong-Sik Kim, Sang-Gu Jo, Do-Sun Hong
  • Patent number: 10489314
    Abstract: A memory module operable to communicate data with a memory controller via a data bus comprises a plurality of memory integrated circuits including first memory integrated circuits and second memory integrated circuits, a data buffer coupled between the first memory integrated circuits and the data bus, and between the second memory integrated circuits and the data bus, and logic coupled to the data buffer. The logic is configured to respond to a first memory command by providing first control signals to the data buffer to enable communication of at least one first data signal between the first memory integrated circuits and the memory controller through the data buffer, and is further configured to respond to a second memory command by providing second control signals to the data buffer to enable communication of at least one second data signal between the second memory integrated circuit and the memory controller through the data buffer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 26, 2019
    Assignee: Netlist, Inc.
    Inventors: Jefferey C. Solomon, Jayesh R. Bhakta
  • Patent number: 10474587
    Abstract: Smart weighted container data cache eviction preserves write evict units (WEUs) containing the most frequently and recently accessed blocks to maintain low latency data cache. Prior to performing cache eviction, the WEUs are weighted based on the page statistics maintained for each WEU. Page statistics include page hit/frequency and recency statistics associated with each WEU and data cache eviction is performed at the WEU level of granularity. Therefore, an entire WEU can be evicted based on page hit/frequency and recency statistics associated with the WEU.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 12, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Satish Kumar Kashi Visvanathan, Rahul Ugale
  • Patent number: 10474638
    Abstract: An illustrative pseudo-file-system driver uses deduplication functionality and resources in a storage management system to provide an application and/or a virtual machine with access to a locally-stored file system. From the perspective of the application/virtual machine, the file system appears to be of virtually unlimited capacity. The pseudo-file-system driver instantiates the file system in primary storage, e.g., configured on a local disk. The application/virtual machine requires no configured settings or limits for the file system's storage capacity, and may thus treat the file system as “infinite.” The pseudo-file-system driver intercepts write requests and may use the deduplication infrastructure in the storage management system to offload excess data from local primary storage to deduplicated secondary storage, based on a deduplication database.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 12, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Amit Mitkar, Paramasivam Kumarasamy, Rajiv Kottomtharayil
  • Patent number: 10467137
    Abstract: Provided are an apparatus, system, integrated circuit die, and method for caching data in a hierarchy of caches. A first cache line in a first level cache having modified data for an address is processed. Each cache line of cache lines in the first level cache store data for one of a plurality of addresses stored in multiple cache lines of a second level cache. A second cache line in the second level cache is selected and a determination is made of a number of corresponding bits in the first cache line and the second cache line that are different. Bits in the first cache line that are different from the corresponding bits in the second cache line are written to the corresponding bits in the second cache line in response to a determination that the number of corresponding bits that are different is less than a threshold.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: November 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Helia Naeimi, Qi Zeng
  • Patent number: 10452532
    Abstract: The present disclosure includes apparatuses and methods for directed sanitization of memory. One example method comprises, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory, wherein performing the deterministic garbage collection operation results in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey L. McVay, Daniel J. Hubbard, Robert W. Strong, Michael B. Danielson, Jonathan Tanguy
  • Patent number: 10452300
    Abstract: Each node includes a cache to store data of the storage shared by the plurality nodes. Time information when a process accessing to data migrates from one node to another node is recorded. The one node, after migration of the process to the other node, selectively invalidates data held in the cache of the one node with a time of last access thereto by the process on the one node being older than a time of migration of the process from the one node to the other node.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 22, 2019
    Assignee: NEC Corporation
    Inventor: Shugo Ogawa
  • Patent number: 10430331
    Abstract: A solid-state drive (SSD) is configured for dynamic resizing. When the SSD approaches the end of its useful life because the over-provisioning amount is nearing the minimum threshold as a result of an increasing number of bad blocks, the SSD is reformatted with a reduced logical capacity so that the over-provisioning amount may be maintained above the minimum threshold.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Daisuke Hashimoto
  • Patent number: 10430339
    Abstract: A memory management method includes determining a stride value for stride access by referring to a size of two-dimensional (2D) data, and allocating neighboring data in a vertical direction of the 2D data to a plurality of banks that are different from one another according to the determined stride value. Thus, the data in the vertical direction may be efficiently accessed by using a memory having a large data width.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-seok Kwon, Chul-soo Park, Suk-jin Kim
  • Patent number: 10423529
    Abstract: Implementations of this disclosure are directed to systems, methods and media for assessing the status of data being stored in distributed, cached databases that includes retrieving, from a data cache, variables which include a cache loss indicator and a non-null value. The variables are analyzed to determine a state of the cache loss indicator. If the cache loss indicator indicates an intentional cache loss state, the cache loss indicator is removed and the non-null value is provided to an application. Otherwise, a cache restore process is initiated.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: September 24, 2019
    Assignee: MZ IP HOLDINGS, LLC
    Inventors: Ajk Palikuqi, Garth Gillespie, Arya Bondarian, Jai Kim
  • Patent number: 10417045
    Abstract: An apparatus and a method is provided that comprises at least one first processing unit configured to run at least one first computer program application capable of receiving and processing signals received from at least one interface or device connected to said first processing unit, at least one second processing unit configured to run at least a second computer program application capable of further processing at least some information processed in said first processing unit.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: September 17, 2019
    Assignee: Amer Sports Digital Services Oy
    Inventors: Erik Lindman, Jyrki Uusitalo, Timo Eriksson, Tomi Lehto, Tero Aurto