Abstract: Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

Abstract: A system includes a memory including a plurality of memory pages, a processor in communication with the memory, and a supervisor. The supervisor is configured to locate at least two duplicate memory pages of the plurality of memory pages, write-protect the at least two duplicate memory pages, and add the at least two duplicate memory pages to a list. Responsive to a first page of the at least two duplicate memory pages changing, the supervisor is configured to remove the first page from the list. Responsive to a memory pressure-triggering event, the supervisor is configured to remove a second page of the at least two duplicate memory pages from the list. The second page is reused after removal from the list.

Abstract: A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

Abstract: Methods, systems, and devices for volatile register to detect power loss are described. The memory system may receive a command to enter a first power mode having a lower power consumption than a second power mode. The memory system may store data in a register associated with the memory system before entering the first power mode (e.g., a low-power mode). The memory system may receive a command to exit the first power mode. The memory system may determine whether the data stored in the register includes one or more errors. The memory system may select a reset operation to perform to exit the first power mode based on determining whether the data stored in the register includes one or more errors.

Abstract: Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit. The memory controller may also store an indication that the first storage sub-unit is invalid.

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

Abstract: Several embodiments of memory devices and systems having a variable logical memory capacity are disclosed herein. In one embodiment, a memory device can include a plurality of memory regions that collectively define a physical memory capacity and a controller operably coupled to the plurality of memory regions. The controller is configured to advertise a first logical memory capacity to a host device, determine that at least one of the memory regions is at or near end of life, and in response to the determination—send a notification to the host device that a logical memory capacity of the memory device will be reduced and then retire the at least one of the memory regions.

Abstract: An apparatus and method for tagged memory management.

Abstract: A system includes a memory device; a volatile memory comprising buffers; and a processing device to perform operations comprising: accessing a read command having a first command tag, the first command tag comprising a first logical transfer unit (LTU) value and a first buffer address for a first buffer, the first LTU value being mapped from a zone of a plurality of sequential logical block address (LBA) values to a first physical address, of the memory device, at which is stored first data; and generating a set of command tags that are to cause second data to be retrieved from the memory device and stored in a set of the buffers, wherein the set of command tags comprises at least a second command tag associated with a second physical address that sequentially follows the first physical address.

Abstract: A device for processing commands to manage non-volatile memory includes a controller configured to obtain address information from a command, read, based on the address information, an entry of a metadata table, and determine, based on the entry of the metadata table, whether a metadata page corresponding to the address information is being processed by the controller. In response to determining that the metadata page corresponding to the address information is being processed, the controller determines a processing status of the metadata page, among a plurality of processing statuses, based on the entry of the metadata table and processes the command according to the processing status of the first metadata page. In response to determining that the metadata page corresponding to first address information is not being processed, the controller reads the metadata page from the non-volatile memory based on the entry of the metadata table.

Abstract: Methods, systems, and devices for power supply control for non-volatile memory are described. A package containing a memory subsystem may include a controller, a volatile memory, and a non-volatile memory. The package may include one or more pins for receiving a supply voltage that may be distributed to the controller, the volatile memory, and the non-volatile memory using one or more power supply rails. The memory subsystem may include one or more switching components along one or more power supply rails to selectively decouple the non-volatile memory from the one or more power supply rails, thereby enabling the non-volatile memory to be powered down separately from the controller and volatile memory. The controller may determine whether to couple or uncouple the non-volatile memory from a power supply rail based on various criteria associated with accessing the non-volatile memory.

Abstract: A distributed agent for backup and restoration of virtual machines collects backup data and meta-data. The distributed agent includes an agent inside a virtual machine and an agent outside the virtual machine. The two kinds of agents communicate with each other to collect data of different types used to backup and restore virtual machines.

Abstract: Devices and techniques to avoid deadlock in a multi-SOC fabric are described herein. An apparatus comprises a network on chip (NOC) interface to receive on a first virtual channel, from a processor, a memory request for a memory controller; a fabric interface configured to include the first virtual channel and a second virtual channel, connected to a scale fabric; and circuitry to: transmit the memory request toward the memory controller on the first virtual channel via the scale fabric; receive a response from the memory controller over the second virtual channel via the scale fabric; and relay the response to the processor over the second virtual channel.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method of a memory system. According to embodiments of the present disclosure, the memory system, before updating a mapping table which includes mapping information between logical addresses and physical addresses, may assign a portion of a map cache area for caching a plurality of map segments in the mapping table as a map update area for updating the mapping table, and may load a subset of the plurality of map segments to the map update area. Accordingly, it is possible to quickly update a mapping table and to optimize update performance for a mapping table within a limit that guarantees caching performance to a predetermined level or higher.

Abstract: A memory device includes a page cache comprising a cache register, a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a cache release command indicating that data associated with a first subset of the plurality of memory planes and pertaining to a previous read command was received by the requestor. Responsive to the cache release command, the control logic returns to the requestor, data from the cache register and associated with a second subset of the plurality of memory planes and pertaining to the previous read command, while concurrently copying data associated with the first subset of the plurality of memory planes and pertaining to a subsequent read command into the cache register.

Abstract: Techniques for managing a storage system involve flushing a target page in a cache device to a persistent storage device of the storage system. The techniques further involve releasing a resource storing a page descriptor of the target page to a resource pool. The resource pool is configured to provide resources to store page descriptors of pages to be flushed in the cache device. The techniques further involve: if it is determined that an auxiliary descriptor of the target page is located at a tail of a queue of auxiliary descriptors of the pages to be flushed, removing the auxiliary descriptor of the target page from the queue. The auxiliary descriptors of the pages to be flushed are configured to describe the page descriptors of the pages to be flushed. Accordingly, the page flushing performance of the storage system can be improved, thereby improving the input/output performance.

Abstract: An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.

Abstract: An apparatus that includes a non-volatile semiconductor storage apparatus includes a controller configured to make a setting of an erase-by-overwriting function of issuing an instruction to erase data stored in the semiconductor storage apparatus by overwriting the stored data with different data, wherein, in a case where the semiconductor storage apparatus satisfies a predetermined condition, the controller enables the setting of the erase-by-overwriting function to be made, and wherein, in a case where the semiconductor storage apparatus does not satisfy the predetermined condition, the controller disables the setting of the erase-by-overwriting function to be made.

Abstract: An information processing device comprises: a memory comprising a cache for storing information related to an object from a plurality of objects, and a summary structure configured to store a summary for the object; a volume configured to store a merge file including the plurality of objects, and a set of dump-files, each dump-file being associated with a specific cache-dump operation of the cache; and a processor configured to assign, to the cache, a first identifier; perform a cache-dump operation based on generating a dump-file associated with the first identifier and storing the information related to the object from the cache to the generated dump-file; and assign, to the cache, a second identifier, wherein the second identifier is larger than the first identifier.

Abstract: A system and method for managing tables in a storage system is described.