Patents Examined by Gustavo A Rosario-Benitez
  • Patent number: 11121619
    Abstract: The disclosure discloses a bus voltage secondary ripple suppression method and a bus voltage secondary ripple suppression device. The method includes: determining a current working mode of an inverter Boost circuit; wherein the working mode includes a continuous current mode (CCM) and a discontinuous current mode (DCM); calculating an output compensation amount according to the current working mode of the inverter Boost circuit; superimposing the output compensation amount on a control output amount of the Boost circuit; and controlling the Boost circuit by a control output amount superimposed with an output compensation amount. According to the scheme of this embodiment, the third harmonic in the output current of the inverter is reduced, and the current output quality of the inverter is improved.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: September 14, 2021
    Assignee: SMA Solar Technology AG
    Inventors: Chengwei Shu, Jiayu Yao, Shijun Li, Jin Cheng
  • Patent number: 11121637
    Abstract: A power conversion system includes a first power converter and a second power converter which are capable of converting an alternating-current power into a direct-current power or converting a DC power into an AC power. The first power converter is interconnectable to a first AC system via a first AC circuit breaker. The second power converter is interconnectable to a second AC system via a second AC circuit breaker. A first DC terminal of the first power converter and a second DC terminal of the second power converter are connectable. The first power converter begins operation prior to the second power converter. A first control device controls a voltage of the first DC terminal, based on a status of the second power converter sent from a second control device.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 14, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi Kikuchi, Toshiyuki Fujii, Ryosuke Uda
  • Patent number: 11114940
    Abstract: A half-bridge electronic device comprises a high level switch and a low level switch in series that are connected at a central point, and a first and a second synchronization system: • the first system comprising a first detection circuit configured to interpret a variation, following a falling edge, of the voltage (Vm) at the central point, and the first system being configured to generate a first synchronization signal (ATON-LS) for activating the low level switch; • the second system comprising a second detection circuit configured to interpret a variation, following a rising edge, of the voltage (Vm) at the central point, and the second system being configured to generate a second synchronization signal (ATON-HS) for activating the high level switch.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 7, 2021
    Assignee: Exagan
    Inventors: Laurent Guillot, Thierry Sutto, Alain Bailly
  • Patent number: 11114945
    Abstract: Controlling an active clamp field effect transistor (FET) in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer, a secondary-side FET coupled to the transformer, and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET across a galvanic isolation barrier.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 7, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Rashed Ahmed, Hariom Rai
  • Patent number: 11095218
    Abstract: A low-power direct current-direct current (DC-DC) converter includes a capacitor, an inductor electrically connected to the capacitor, a first switch configured to be turned on for a first switching interval and supply energy from an input power source to the inductor for the first switching interval, a second switch configured to be turned on for a second switching interval and electrically connect the inductor and a ground terminal for the second switching interval, and a switching control circuit configured to generate first and second switching signals. The switching control circuit is further configured to generate a first sample signal by sampling the voltage level of a first node, and to determine, responding to the first sample signal in time domain, an pulse width adjustment adapted to adjust at least one of the length of a second switching interval and the length of a common blocking interval.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 17, 2021
    Assignee: ABOV SEMICONDUCTOR CO., LTD.
    Inventors: Hong Jin Kim, Suk Kyun Hong, Hyun Kyu Kim, Eung Oh, Suk Yun
  • Patent number: 11086349
    Abstract: A reference voltage generator includes an output terminal, a current source, a reference circuit, a protection circuit, and a control circuit. The output terminal outputs a reference voltage. The current source is coupled to the output terminal, and generates a reference current. The reference circuit is coupled to the output terminal, and generates a reference voltage according to the reference current. The protection circuit is coupled to the output terminal, and adjusts a voltage of the output terminal to an operating voltage. The control circuit is coupled to the reference circuit and the protection circuit. The control circuit controls the reference circuit and the protection circuit according to a start signal.
    Type: Grant
    Filed: September 1, 2019
    Date of Patent: August 10, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Jen-Yu Peng, Chun-Hung Lin, Cheng-Da Huang
  • Patent number: 11056981
    Abstract: For AC-DC conversion, signal is extracted, then sampled and held and released. Extraction element receives AC signal to generate extracted signal, then sample and hold and release element receives the extracted signal to generate DC signal. Extraction and/or sample and hold and release signal processing may use microprocessor or controller programmably to generate the extracted signal and/or DC signal. Extraction is configurable such that AC signal is received at extraction time or temporal window, whereby said extraction element generates the extracted signal having an extraction current or voltage value during at least one extraction time, and preferably said sample and hold and release element generates the DC signal having the same extraction current or voltage value.
    Type: Grant
    Filed: July 7, 2018
    Date of Patent: July 6, 2021
    Assignee: Intelesol, LLC
    Inventor: Mark Telefus
  • Patent number: 11050237
    Abstract: A circuit breaker failure protection relay includes an input circuit to which an opening command from a first circuit breaker is input, and a circuit breaker failure detection element configured to compare a magnitude of a current detection signal in a power system with a setting value to make a determination about an overcurrent. The circuit breaker failure detection element is capable of changing the setting value to a first value and a second value that is larger than the first value according to a switching signal. The circuit breaker failure protection relay is configured to, when the opening command is input and when the circuit breaker failure detection element determines that an overcurrent occurs, output an opening command for the second circuit breaker in a neighborhood of the first circuit breaker.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: June 29, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Satoshi Takemura, Shigetoo Oda
  • Patent number: 11038335
    Abstract: Systems and techniques are disclosed that monitor an area adjacent to power system components and detect objects that may pose a probable risk of causing a fault, for example, making contact with the power system component. Various embodiments initiate a preventative, a corrective, and/or a mitigative action in advance of the fault. Examples of possible actions include, but are not limited to, an audible alert, a visual alert, a tactile alert, a remote notification, a limiting of machinery motion, a stopping of machinery motion, a reversing of machinery motion, de-energization of the power system component, or combinations thereof.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 15, 2021
    Assignee: Avista Corporation
    Inventor: Greg Johnson
  • Patent number: 11038421
    Abstract: Timing circuitry causes: a first closed signal on a first switch control output before a signal on a second switch control output changes from a second closed signal to a first open signal; the first switch control output to provide a second open signal after a first selected time after the second switch control output changes from the second closed signal to the first open signal; and a third switch control output to provide a third closed signal a second selected time after the first switch control output changes from the first closed signal to a third open signal. A beginning of the first closed signal to a beginning of the first open signal is based on a later of: a current through a switch connected to the second switch control output exceeding a threshold current; and a clocked time after the beginning of the first closed signal.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: June 15, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas Matthew LaBella, Michael G. Amaro, Jeffrey Anthony Morroni
  • Patent number: 11031776
    Abstract: Embodiments of overvoltage protection devices and a method for operating an overvoltage protection device are disclosed. In an embodiment, an overvoltage protection device includes a switch circuit connected between an input terminal from which an input voltage is received and an output terminal from which an output voltage is output and including multiple NMOS transistors and multiple PMOS transistors connected in series between the input terminal and the output terminal, a first voltage generation circuit configured to, generate a first voltage that is applied to the NMOS transistors and a second voltage that is applied to a body of each of the PMOS transistors, in response to the input voltage and a supply voltage, and a second voltage generation circuit configured to generate a third voltage that is applied to the PMOS transistors in response to the input voltage and the first voltage.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: June 8, 2021
    Assignee: NXP B.V.
    Inventors: Siamak Delshadpour, Xiaoqun Liu
  • Patent number: 11024528
    Abstract: An electrostatic chuck device comprising: a placing table having a placing surface on which a plate-shaped sample is placed, an electrostatic attraction electrode, which is located on a lower side of the placing table in such a manner that the electrode is located on a surface side opposite to the placing surface of the placing table, a base part on which at least the placing table and the electrostatic attraction electrode are mounted, a focus ring which surrounds the placing table wherein the focus ring is a continuous ring or is divided into two or more portions, and a lift pin which is movable in an up-down direction and raises the entirety of or at least a part of the focus ring from the base part.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: June 1, 2021
    Assignee: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Yoshiaki Moriya, Keigo Maki, Hitoshi Kouno, Kazuto Ando, Yuuki Kinpara
  • Patent number: 11012000
    Abstract: A switching type control method based on a double loop predictive control is provided. A deadbeat control is adopted by the outer loop control. The switching type control method is adopted by the inner loop control. When the system is in the steady state, the deadbeat control by an inner loop is adopted to ensure the steady state accuracy of the system and to achieve the fixed switching frequency. When the system is in the transient state, it is switched to the finite control set model predictive control by the inner loop to ensure the rapid transition of the system to the steady state.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: May 18, 2021
    Assignee: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Guiping Du, Jiajian Li, Zhifei Liu
  • Patent number: 11005388
    Abstract: A multi-level inverter includes a coupling to a DC power source and a coupling to an AC power source, a plurality of capacitors arranged to create a set of nodes, and a plurality of switches located between the capacitors and the AC power source. Switches are configured to create an AC bypass in which the capacitors coupled to the DC power source may be isolated from the AC power source. The AC bypass is utilized as one of the switching states in a switching sequence that provides enhanced performance including but not limited to reduced electromagnetic interference and ripple.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 11, 2021
    Assignee: sonnen, Inc.
    Inventors: Alberto Berzoy Llerena, Andres Salazar-Llinas, Carlos Restrepo
  • Patent number: 10998716
    Abstract: Various embodiments of the present invention are directed to a first trip unit that is configured to be coupled to a power distribution system arranged in a Zone Selective Interlocking (ZSI) arrangement. The first trip unit includes an Input/Output circuit including a ZSI input terminal and a ZSI output terminal, a heartbeat signaling module configured to transmit a second signal to a second trip unit in a lower-level zone than the first trip unit, responsive to the normal condition, a first monitoring module configured to monitor a first signal received by the first trip from a third trip unit in a higher-level zone, responsive to the normal condition, and a second monitoring module configured to detect the fault condition. Related systems, devices, and methods are also described.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: May 4, 2021
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Zhi Gao, Daniel A. Hosko, Randy P. Shvach, James Leo Lagree, Paul Richard Rakus, Ronald Dale Hartzel
  • Patent number: 10992233
    Abstract: A DC to DC power converter is described that includes a transformer, a primary side connected to a primary transformer winding, and a secondary side connected to a secondary transformer winding. The secondary side comprises inductor-capacitor (LC) circuitry at an input, and a plurality of diodes providing uncontrolled rectification. A controller controls switching of the switching circuitry to apply voltage pulses to the primary transformer winding. The voltage pulses are separated by zero-voltage periods. A switching frequency of the switching circuitry is less than the resonant frequency of the LC circuitry.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: April 27, 2021
    Assignee: VESTAS WIND SYSTEMS A/S
    Inventors: Catalin Gabriel Dincan, Philip Carne Kjær
  • Patent number: 10985649
    Abstract: A power conversion device including: a reactor formed such that a DC winding and a plurality of coupled windings are wound around one magnetic body, one end of the DC winding is connected to a voltage source, one end of each of the plurality of coupled windings is connected to another end of the DC winding, another end of each of the plurality of coupled windings is connected to each intermediate connection point between a plurality of upper and lower arms composed of switching elements, and magnetic fluxes generated by currents flowing through the DC winding and the coupled windings merge with each other in the same direction; and a control device for controlling the switching elements, wherein the upper arms or the lower arms are controlled by in-phase driving or interleave driving on the basis of the duty of switching operation.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 20, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Satoshi Murakami, Ryota Kondo, Takaaki Takahara
  • Patent number: 10971926
    Abstract: An apparatus for controlling and monitoring the lifetime of a superconducting fault current limiter. The apparatus may include a processor; and a memory unit coupled to the processor, including a lifetime routine, where the lifetime routine is operative on the processor to monitor the superconducting fault current limiter. The lifetime routine may include a lifetime estimation processor to receive a set of fault information for a fault event of a superconductor tape of the superconducting fault current limiter, determine a present state of the superconductor tape based upon the set of fault information, and determine an estimated lifetime of the superconductor tape based upon the present state. The present state may be determined from additional information such as fault history on the superconducting fault current limiter, as well as a database of superconductor tape behavior with respect to various faults.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: April 6, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Saeed Jazebi, John Evans
  • Patent number: 10965118
    Abstract: An EOS/ESD protection apparatus includes a voltage detection circuit, a controlling circuit having a switch unit, an inverter circuit, and a clamp transistor. The voltage detection circuit is configured to detect whether an over voltage event occurs in a power supply line to generate a switch control signal. The switch unit is turned on/off to generate a voltage control signal according to the switch control signal. The inverter circuit has an output and an input coupled to the voltage control signal transmitted from the controlling circuit. The clamp transistor has a control terminal coupled to the output of the inverter and is configured to be turned on when the over voltage event occurs in the power supply line.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: March 30, 2021
    Assignee: MEDIATEK INC.
    Inventor: Wei-Yu Ma
  • Patent number: 10958174
    Abstract: A power converter and method to detect a light load condition at an output of the power converter are presented. The power converter may have an inductor and a resistive element connected between an input of the power converter and an input of the inductor. The power converter may have a first chopping unit to generate a chopped voltage signal at an output of said first chopping unit, wherein the chopped voltage signal is generated by chopping an inductor voltage at the input of said inductor based on a duty cycle of the power converter. The power converter may have a reference current source, wherein the reference current source and a replica resistive element are arranged in series. The power converter may have a comparator unit to generate, based on the reference potential and based on the chopped voltage signal, a signal indicative of said light load condition.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: March 23, 2021
    Assignee: Dialog Semiconductor Inc.
    Inventors: Manmeet Singh, Pietro Gallina, Rosario Pagano, Vijay Choudhary, Vivek Parasuram, John Kesterson