Abstract: A method for embedding a dopant into a glass substrate is provided. The method may include the steps of applying the dopant to a surface of the glass substrate, positioning the glass substrate adjacent to a catalyst such that the dopant is intermediate the catalyst and the glass substrate, heating the glass substrate to a first temperature, operating a directed thermal energy source so as to generate thermal energy incident upon the dopant, reducing the temperature of the glass substrate to a second temperature below the first temperature, and holding the glass substrate at the second temperature for at least a period of time.

Abstract: Methods of forming solder balls for semiconductor packages using film-assisted molding include providing a substrate, forming a plurality of solder balls on the substrate where each solder ball has an initial profile, and coupling a substantially planar film to the solder balls. As an encapsulation is deposited over the substrate and around the solder balls, the substantially planar film and the encapsulation, along with the molding process, can cause each solder ball to morph from its initial profile to a final profile, where the final profile is generally different from the initial profile.

Abstract: A metal contact of a solar cell is formed by electroplating copper using an electroplating seed that is formed on a dielectric layer. The electroplating seed includes an aluminum layer that connects to a diffusion region of the solar cell through a contact hole in the dielectric layer. A nickel layer is formed on the aluminum layer, with the nickel layer-aluminum layer stack forming the electroplating seed. The copper is electroplated in a copper plating bath that has methanesulfonic acid instead of sulfuric acid as the supporting electrolyte.

Abstract: A CMOS image sensor includes an active pixel structure suitable for sensing light incident from outside and converting a sensed light into an electrical signal, and an optical block structure suitable for blocking a visible light and passing a UV light to check and evaluate an electrical characteristic of the active pixel area. The UV pass filter includes first and second insulation layers comprising an insulator, and a metal layer formed between the first and second insulation layers.

Abstract: A method for fabricating a semiconductor device with mini-SONOS cell is disclosed. The method includes: providing a semiconductor substrate having a first MOS region and a second MOS region; forming a first trench in the semiconductor substrate between the first MOS region and the second MOS region; depositing a oxide liner and a nitride liner in the first trench; forming a STI in the first trench; removing a portion of the nitride liner for forming a second trench between the first MOS region of the semiconductor substrate and the STI and a third trench between the STI and the second MOS region of the semiconductor substrate; and forming a first conductive type nitride layer in the second trench.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.

Abstract: Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.

Abstract: A method for producing an OLED illuminating device includes steps of: (a) forming metal lines and power transmission lines on a substrate; (b) forming a patterned insulating layer to cover the metal lines and the power transmission lines; (c) forming a patterned first electrode layer on the insulating layer; (d) forming an organic light-emitting membrane structure on the first electrode layer; (e) forming a second electrode layer on the organic light-emitting membrane structure so that a plurality of luminescent pixels are formed; and (f) when one of the luminescent pixels is defective, cutting one of the power transmission lines that is connected to the defective one of the luminescent pixels using an energy beam.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: The present invention generally relates to a MEMS device in which silicon residues from the adhesion promoter material are reduced or even eliminated from the cavity floor. The adhesion promoter is typically used to adhere sacrificial material to material above the substrate. The adhesion promoter is the removed along with then sacrificial material. However, the adhesion promoter leaves silicon based residues within the cavity upon removal. The inventors have discovered that the adhesion promoter can be removed from the cavity area prior to depositing the sacrificial material. The adhesion promoter which remains over the remainder of the substrate is sufficient to adhere the sacrificial material to the substrate without fear of the sacrificial material delaminating. Because no adhesion promoter is used in the cavity area of the device, no silicon residues will be present within the cavity after the switching element of the MEMS device is freed.

Abstract: A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer.

Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.

Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.

Abstract: The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.

Abstract: Methods and apparatus for a sensor are disclosed. An oxide layer is formed on a substrate, followed by a spacer layer and a buffer layer. A photoresist layer is formed on the buffer layer over a pixel region, with an opening exposing a first part of the buffer layer. A first etching is performed to remove the first part of the buffer layer to expose a first part of the spacer layer. A second etching is performed to remove the first part of the spacer layer, the remaining buffer layer, and partially remove a second part of the spacer layer so that the result spacer layer will have an end with a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end.

Abstract: Described are embodiments of apparatuses and systems including photonic devices having a conductive shunt layer, and methods for making such apparatuses and systems. A photonic device may include a device substrate, a photo-active region disposed on a first region of the device substrate, an isolation region in the device substrate, a contact disposed on a second region of the substrate such that the isolation region is located between the contact and the photo-active region, and a conductive material overlying the isolation region to shunt the first region with the second region. Other embodiments may be described and/or claimed.

Abstract: A method of detecting the circular uniformity of semiconductor circular contact holes. Several detection circuit structures are disposed on the semiconductor wafer: N-type active regions and P-type active regions; silicon dioxide layers separate the N-type active regions from the P-type active regions; the N-type active regions are formed in the P well and the P-type active regions are formed in the N well; polysilicon gates bridge the N-type active regions and the P-type active regions; gate oxide layers insulate the P-type regions and the N-type regions from the polysilicon gates, so that the P-type regions and the N-type regions are independent; the N-type active regions connect with circular contact holes while the P-type active regions and the polysilicon gates connect with oval contact holes; a electron beam scanner detects the circular uniformity of the contact holes. This invention advantageously reflects effectively and comprehensively the circular uniformity of the contact holes.

Abstract: According to an embodiment of present disclosure, a film formation method is provided. The film formation method includes supplying a first process gas as a source gas for obtaining a reaction product to a substrate while rotating a turntable and revolving the substrate, and supplying a second process gas as a gas for nitriding the first process gas adsorbed to the substrate to the substrate in a position spaced apart along a circumferential direction of the turntable from a position where the first process gas is supplied to the substrate. Further, the film formation method includes providing a separation region along the circumferential direction of the turntable between a first process gas supply position and a second process gas supply position, and irradiating ultraviolet rays on a molecular layer of the reaction product formed on the substrate placed on the turntable to control stresses generated in a thin film.

Abstract: Disclosed is a method for manufacturing an oxide thin film transistor, including: forming a gate electrode on a substrate on which a buffer layer is formed; forming a gate insulation layer on an entire surface of the substrate on which the gate electrode is formed; forming an oxide semiconductor layer on the gate insulation layer; forming a first etch stop layer on the oxide semiconductor layer; forming a second etch stop layer on the first etch stop layer by an atomic layer deposition method; patterning the first etch stop layer and the second etch stop layer, or forming a contact hole, through which a part of the oxide semiconductor layer is exposed, in the first etch stop layer and the second etch stop layer; forming a source electrode and a drain electrode on the first etch stop layer and the second etch stop layer; and forming a passivation layer on the entire surface of the substrate on which the source electrode and the drain electrode are formed.