Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon carbide (SiC), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract: The present invention relates to a hybrid layer including an oxide layer or organic layer, and organic polymer layer, an insulating layer including the hybrid layer, and an electronic device such as an organic field-effect transistor. A hybrid layer according to the present invention may include an oxide layer or an organic layer, and an organic polymer layer chemically combined with the oxide layer or the organic layer.

Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate and a refractory metal layer. Then, an etch mask layer is deposited on the refractory layer, followed by selective etching of the refractory metal layer with a dry-etch tool with high selectivity to the etch mask layer. Then, the refractory metal layer is oxidized to form an oxidized refractory metal region, and a top cladding layer made of a second low refractive index material to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.

Abstract: A thin film transistor and a fabrication method thereof are provided. A metal patterning layer is formed on the metal oxide semiconductor layer of a thin film transistor to shield the metal oxide semiconductor layer from the water, oxygen and light in the environment.

Abstract: The present application provides an electronic apparatus including a substrate including a first electrode pad, a second electrode pad and an intermediate pad each disposed on one surface of the substrate and separated from one another. An electronic device is disposed on the substrate and including a first electrode unit and a second electrode unit. The first electrode unit has an adhesion surface facing the first electrode pad and the intermediate pad. The second electrode unit has an adhesion surface facing the second electrode pad.

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. In detail, according to a preferred embodiment of the present invention, the printed circuit board includes: an insulating layer; and a metal layer formed on the insulating layer, wherein in the metal layer, a ratio occupied by crystal orientations of (110) and (112) is 20 to 80%. By doing so, the preferred embodiment of the present invention provides a printed circuit board including the metal layer having different crystal orientations to minimize factors of hindering electrical characteristics such as electric conductivity and improve isotropy of mechanical properties and a method of manufacturing the printed circuit board.

Abstract: In an aspect, a composition including an acrylate monomer, and aromatic aryl amine compound, an organic light emitting display apparatus including the composition and a method of manufacturing an organic light emitting display apparatus including the composition are provided.

Abstract: One embodiment is a method for semiconductor processing. In this method, a precursor film is provided over a semiconductor substrate, where the precursor film is made of a structural former and porogen. Prior to cross-linking, the porogen is removed by exposure to UV radiation having one or more wavelengths in the range of 150 nm to 300 nm, while a temperature of 300° C. to 500° C. is applied to the semiconductor substrate. Meanwhile, a Argon:Helium flow rate of 80>Ar>10 slm, 80>He>10 slm is set for the ambient substrate environment where the ratio of Ar:He ranges from 0:1 to 1:0 by volume or molality.

Abstract: A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.

Abstract: Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface.

Abstract: An optoelectronic semiconductor device includes an optoelectronic semiconductor layer sequence on a metal carrier element, which includes as a first component silver and as a second component a material having a lower coefficient of thermal expansion than silver, wherein the first and second components are intermixed in the metal carrier element.

Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract: A method of fabricating a nonpolar gallium nitride-based semiconductor layer is provided. The method is a method of fabricating a nonpolar gallium nitride layer using metal organic chemical vapor deposition, and includes disposing a gallium nitride substrate with an m-plane growth surface within a chamber, raising a substrate temperature to a GaN growth temperature by heating the substrate, and growing a gallium nitride layer on the gallium nitride substrate by supplying a Ga source gas, an N source gas, and an ambient gas into the chamber at the growth temperature. The supplied ambient gas contains N2 and does not contain H2.

Abstract: The pixel structure includes a scan line, a data line, a thin-film transistor, a first electrode layer, a protective layer and a second electrode layer. The thin-film transistor is electrically connected to the scan line and the data line, and includes a gate, an oxide semiconductor layer, an insulating layer, a source and a drain. The first electrode layer is in the same layer as the oxide semiconductor layer, and is surrounded by the scan line and the data line. The second electrode layer is located on the first electrode layer, and the protective layer is located between the first electrode layer and the second electrode layer, wherein one of the first and second electrode layers is electrically connected to the thin-film transistor, and the other is connected to a common voltage. The second electrode layer includes a plurality of slits exposing an area of the first electrode layer.

Abstract: In a preferred embodiment, a wiring board with embedded device and electromagnetic shielding includes a semiconductor device, a core layer, a shielding lid, shielding slots and build-up circuitry. The build-up circuitry covers the semiconductor device and the core layer. The shielding slots and the shielding lid are electrically connected to at least one ground contact pad of the semiconductor device by the build-up circuitry and can respectively serve as effective horizontal and vertical electromagnetic shields for the semiconductor devices.

Abstract: A substrate processing apparatus capable of suppressing generation of by-products in a buffer space in even a single-wafer apparatus using the buffer space, and a method of manufacturing a semiconductor device are provided. The substrate processing apparatus includes a process chamber including a placement unit having a placing surface whereon a substrate is placed, a shower head including a buffer chamber and installed at upstream side of the process chamber, a gas supply system configured to alternately supply at least two types of gases into the process chamber via the buffer chamber of the shower head, and a heating unit configured to heat the buffer chamber to a first temperature and the process chamber to a second temperature which is higher than the first temperature while the at least two types of gases are supplied via the gas supply system.

Abstract: High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an insulator layer of varying depth over a drift region and a body of a substrate. The method further includes forming a control gate and a split gate region by patterning a layer of material on the insulator layer. The split gate region is formed on a first portion of the insulator layer and the control gate is formed on a second portion of the insulator layer, which is thinner than the first portion.

Abstract: According to embodiments of the invention, a TFT array substrate, a manufacturing method of the TFT array substrate and a display device are provided. The method comprises: depositing a metal film on a substrate, and forming a gate electrode and a gate line; forming a gate insulating layer and a passivation layer on the substrate; depositing a transparent conductive layer, a first source/drain metal layer and a first ohmic contact layer, and forming a drain electrode, a pixel electrode, a data line, and a first ohmic contact layer pattern provided on the drain electrode; and depositing a semiconductor layer, a second ohmic contact layer and a second source/drain metal layer, and forming a source electrode, a second ohmic contact layer pattern provided below the source electrode, and a semiconductor channel between the source electrode and the drain electrode.

Abstract: A method of fabricating a fin field effect transistor (FinFET) comprises providing a substrate comprising a major surface, forming a first and second fin extending upward from the substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, wherein a portion of the first and second fin extend beyond the top surface of the insulation layer. The method also includes selectively growing an epitaxial layer covering each fin, annealing the substrate to have each fin covered by a bulbous epitaxial layer defining an hourglass shaped cavity between adjacent fins, wherein the cavity comprises an upper and lower portion. The method includes forming a metal material over the bulbous epitaxial layer and annealing the substrate to convert the bulbous epitaxial layer bordering the lower portion of the cavity to silicide.