Abstract: A method for fabricating a capacitor for a semiconductor device is disclosed, which comprises the steps of: forming a storage node electrode on a semiconductor wafer, forming a dielectric layer made of a cyclic silicon nitride layer on the surface of the storage node electrode, and forming an upper electrode on the dielectric layer; lowering the thickness Teff of the dielectric layer and improving leakage current characteristics through use of a cyclic Si3N4 or a cyclic SiOxNy (wherein x falls between 0.1 and 0.9 and y falls between 0.1 and 2), having a large oxidation resistance and high dielectric ratio, as a dielectric.

Abstract: According to embodiments of the invention, a first gate insulating pattern and a mask pattern are sequentially stacked on a semiconductor substrate. Subsequently an impurity region is formed in the semiconductor substrate. Next, the mask pattern is removed to expose the first gate insulating pattern and a second gate insulating layer is formed on the entire surface thereof. The mask pattern is preferably formed of an anti-reflecting pattern and a photoresist pattern that are sequentially stacked. The anti-reflecting pattern is preferably formed of a material layer without etching selectivity with respect to the photoresist pattern. For this, the anti-reflecting pattern is preferably formed of organic materials including hydrocarbonic compounds. In addition, removing a mask pattern is performed with an etch recipe having an etch selectivity with respect to the first gate insulating pattern.

Abstract: A semiconductor device without any peel off from the insulation film and without any fracture that becomes the cause of a short circuit is obtained even if a metal such as Ru is employed for the storage node. On the semiconductor substrate are provided an underlying interlayer insulation film located over both a capacitor region and a peripheral region, an interlayer insulation film located above the underlying interlayer insulation film, and a tubular metal film having a bottom end portion in contact with the underlying interlayer insulation film, and piercing the interlayer insulation film with the opening side located at the upper side in the capacitor region and the peripheral region. The opening side of the tubular metal film is formed only of a portion extending along the sidewall of a throughhole in the interlayer insulation film.

Abstract: The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff1) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff2), which is less than the first differential resistance (Rdiff1).

Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.

Abstract: A manufacturing method of a thin-film structural body, capable of preparing a thin-film structural body by using a sacrifice film without any protruding part on its surface, thereby preparing a thin-film structural body having high strength and reliability. After a sacrifice film is formed with a film thickness greater than a predetermined value, the surface of the sacrifice film is ground so that the surface of the sacrifice film is flattened with the film thickness of the sacrifice film being adjusted to the predetermined value. Thus, the influence of the surface irregularity of a substrate is eliminated and the surface of the sacrifice film is flattened. Thereby, a mass body, beams and fixed electrodes of a semiconductor acceleration sensor are prepared by using the sacrifice film.

Abstract: Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A method for fabricating a semiconductor device is provided. A ruthenium layer is formed on a semiconductor substrate in a processing chamber. A barrier layer is formed on the ruthenium layer supplying a halide-free precursor in the processing chamber. A metal layer such as an aluminum layer, an aluminum alloy layer, a tungsten layer, or a copper layer is formed on the barrier layer. The barrier layer is one of a TiN layer, a TaN layer, a WN layer, and an MoN layer. The TiN layer is one of formed by using an MOCVD process and an ALD process, and the halide-free precursor is a titanium compound selected from the group consisting of pentakis(diethylamino) titanium, tetrakis(diethylamino) titanium, tetrakis(dimethylamino)titanium, and pentakis(dimethylamino)titanium.

Abstract: An improved dopant application system and method for the manufacture of microelectronic devices accurately places dopant on and within a dielectric or semiconductor surface. Diffusing and activating p-type and n-type dopants in dielectric or semiconductor substrates is achieved by means of electron beam irradiation.

Abstract: In a semiconductor pressure sensor manufacturing method of disposing an etching mask (50) at one-face (11) side of a monocrystal silicon substrate 10 in which the face-direction of the one face 11 corresponds to the (110)-face, and then carrying out anisotropic etching to form a recess portion (20) and a diaphragm (30) at the bottom surface side of the recess portion (20), the etching mask (51) is designed to have a cross-shaped opening portion (51) at which a first area extending along the <110> crystal axis direction and a second area extending along the <100> crystal axis direction cross each other, the area of the opening portion (51a) of the overlap area between the first and second areas in the opening portion (51) being set to be smaller than the area of the diaphragm (30).

Abstract: A method for providing conductive paths into a hermetically sealed cavity is described. The sealed cavity is formed utilizing a silicon-glass micro-electromechanical structure (MEMS) process and the method includes forming recesses on a glass substrate everywhere that a conductive path is to pass into the cavity, and forming conductive leads in and around the recesses. A glass layer is deposited over the substrate, into the recesses, and over the conductive leads and then planarized to expose portions of the conductive leads. A sealing surface is formed on at least a portion of the glass layer. Silicon is then bonded to the sealing surface of the planarized glass layer, the wafer being configured such that a portion of each lead is within the sealed cavity and a portion of each lead is outside the sealed cavity.

Abstract: The invention provides a method for manufacturing a piezoelectric element including a coating step of coating a substrate with a coating liquid for forming the piezoelectric element thereby forming a coated film, a drying step of drying the coated film, a preliminary sintering step of preliminarily sintering the coated film thereby forming an oxide film, a final sintering step of finally sintering the oxide film thereby forming a piezoelectric film, and a cooling step of cooling the piezoelectric film, wherein the steps are executed in the presence of a moisture-containing gas; in the coating step the substrate has a temperature equal to or less than 50° C. and the moisture-containing gas has a relative humidity of 60% RH or less at 25° C.; in the drying step, the substrate has a temperature equal to or less than 200° C. and the relative humidity is 10 to 70% RH; in the preliminary sintering step the substrate has a temperature of 200 to 450° C.

Abstract: A method of forming a capacitor with reduced leakage current on a substrate in a semiconductor device is set forth. A first layer of a conductive material is formed over the substrate, and a second layer of a dielectric is formed over the first layer. The second layer is contacted with hydrogen, oxygen and nitrous oxide gases to form an oxidation layer over the second layer. A third layer of a conductive material is formed over the second layer to thereby form the capacitor. While the capacitor exhibits an improved leakage current reduction, overall capacitance is substantially unaffected, as compared to a similar capacitor having an oxidation layer built from a combination of oxygen and hydrogen gases only.

Abstract: In order to provide a silicon wafer break pattern that stabilizes the location and shape of the breaks at weak spots of the break pattern and that reduces waste, the through-holes of the break pattern is disposed along a scribe line, a first group of the through-holes are substantially disposed on only a first side of the scribe line, and a second group of the through-holes are substantially disposed on only a second side of the scribe line.

Abstract: In order to perform a measurement operation of a pattern and a processing operation in parallel while the positions of two substrate stages are accurately measured and wire/hose units are prevented from becoming tangled, a substrate processing apparatus includes an alignment system for measuring the pattern arrangements of the substrates, a processing system disposed separately from the alignment system and used for processing the substrates, substrate stages which are able to support the substrates and move in an xy plane, and position measurement systems which measure the positions of the substrate stages. Four position measurement systems are arranged for the measurement in the x direction, and three position measurement systems are arranged for the measurement in the y direction. One of the position measurement systems for the measurement in the y direction is disposed at a side opposite to the remaining positioning measurement systems across the substrate stages.

Abstract: An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (?m)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

Abstract: A method of code programming a mask read only memory (ROM) is disclosed. According to the method, a first photoresist layer is formed over word lines and a gate oxide layer of a substrate already having implanted bit lines. The first photoresist layer is patterned to develop pre-code openings over all of the memory cells, which correspond to intersecting word and bit lines. The first photoresist layer is then hardened using either a treatment implant or a treatment plasma. Subsequently, a second photoresist layer is formed over the first photoresist layer and patterned to develop real-code openings over memory cells which are actually to be coded with a logic “0” value. Each memory cell to be coded is then implanted with implants passing through the pre-code openings and the real code openings and into the memory cell.

Abstract: A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second conducting film, covering the edge of the second conducting film, a third conducting film 34 formed above the second dielectric film, covering a part of the second dielectric film covering the edge of the second conducting film. The capacitor further comprises an insulation film 28 covering the edge of the second conducing film or the part of the second dielectric film. An effective thickness of the insulation film between the second conducting film and the third conducing film in the region near the edge of the second conducting film can be increased, whereby concentration of electric fields in the region near the edge of the second conducting film. Consequently, the capacitor can have large capacitance without lowering voltage resistance.

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line.

Abstract: Disclosed is a method of manufacturing an image sensor having light sensitivity over a photodiode equal in area to that of a unit pixel. The image sensor includes an image sensor comprising: a first semiconductor substrate doped with a first conductive dopant; a first diffusion layer formed in the semiconductor substrate and doped with a second conductive dopant; a second diffusion layer formed in the semiconductor substrate adjacent the first diffusion layer and having a width wider than a width of the first diffusion layer; a third diffusion layer doped with the first conductive dopant and formed at an exposed surface of the semiconductor substrate in the first diffusion layer; a gate electrode formed on the exposed surface and having a first edge adjacent to the third diffusion layer; and a fourth diffusion layer doped with the second conductive dopant and formed at the exposed surface adjacent a second edge of the gate electrode, the fourth diffusion layer defining a gap with the second diffusion layer.