Abstract: Disclosed are an inductor for a semiconductor integrated circuit, which provides a wider cross-sectional area, significantly reduces the resistance to improve the Q value and has a highly uniform film thickness, and a method of fabricating the inductor. A spiral inductor is formed on a topmost interconnection layer of a multilayer interconnection layer formed by a damascene method. This inductor is formed by patterning a barrier metal layer on an insulation film, on which a topmost interconnection is formed, in such a way that the barrier metal layer contacts the topmost interconnection, then forming a protective insulation film on an entire surface of the barrier metal layer, forming an opening in that portion of the protective insulation film which lies over the barrier metal layer, forming a thick Cu film with the barrier metal layer serving as a plating electrode, and performing wet etching of the Cu film. This process can allow the inductor to be so formed as to be thick and have a wide line width.

Abstract: A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.

Abstract: Metallic reservoirs in the form of passive or dummy vias are used on interconnects as a source or sink for electromigration material, slowing the build up of electromigration-induced mechanical stress. The passive or dummy vias are disposed in a vertical direction from the interconnect (perpendicular to the plane of the interconnect) to so that the reservoirs do not occupy additional space in the interconnect layer. Both apparatus and method embodiments are described.

Abstract: To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.

Abstract: The present invention relates to a method for manufacturing a flash memory device and a flash memory device manufactured by the same. In the present invention, an annealing process of a tunnel insulating film is performed at a relatively low temperature to optimize the threshold voltage of a NHVN transistor. Furthermore, in case of portions not compensated through the annealing process of the tunnel insulating film, the quality of the tunnel insulating film is compensated through a subsequent liner oxide film deposition process and a HDP oxide film annealing process. Therefore, the present invention can improve reliability of the tunnel insulating film and thus provide a flash memory device having good properties.

Abstract: A method of fabricating a CMOS (complementary metal oxide semiconductor) transistor includes manufacturing steps, by which adverse transistor characteristics can be prevented from being degraded by high-temperature annealing for hardening a screen oxide layer. The method includes steps of forming a gate on a semiconductor substrate with a gate oxide layer therebetween, forming a screen oxide layer on the substrate and the gate, forming a nitride layer on the screen oxide layer, forming LDD regions in the substrate substantially aligned with the gate, removing the nitride layer, forming a spacer on the screen oxide layer and on at least a portion of a sidewall of the gate, and forming in the substrate source/drain regions extending from the LDD regions respectively in the substrate substantially aligned with the spacer.

Abstract: A resistor structure is disclosed that is constructed out of two layers of polysilicon. The intrinsic device is made using the top layer which is either a dedicated deposition, or formed as part of an existing process step such as a base epi growth in a BiCMOS flow. This poly layer can be made with a relatively high (greater than 2000 ohms per square) sheet resistance by appropriate scaling of the implant dose or by insitu doping methods. In this invention this layer is arranged to be about 1000 A or less thick. Such a resistor form with this thickness has been shown to demonstrate a better standard deviation of resistance compared to resistors made with a thicker layer. Additionally, practical resistors made in elongated forms demonstrate better standard deviations of resistance when five bends were incorporated into the form. The resistor ends are formed by the addition of a bottom poly layer in a self aligned manner with a deposition that may already be part of the process sequence.

Abstract: A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions of the patterned gate region. Source-drain regions are formed in the first semiconductor layer. Recesses are formed in the first semiconductor layer that extends under the dielectric spacers. The first semiconductor layer has exposed surfaces that in part define sidewalls of the recesses. A nickel barrier layer is formed on each of the exposed surfaces of the first semiconductor layer. The nickel barrier layers are etched so that the nickel barriers remain only on portions of the exposed surfaces located under the dielectric spacers and not on remaining portions of the exposed surface. A silicon-containing layer is formed on the remaining exposed surfaces of the first semiconductor layer.

Abstract: Magnetoresistive devices are formed on the insulating surface of a substrate made of silicon. The devices are connected in series through an insulating film using a wiring layer formed on the surface of the substrate. An insulating film for passivation is formed to cover the devices and the wiring layer. A magnetic shield layer of Ni—Fe alloy is formed on the passivation insulating film through an organic film for relieving thermal stress to cover one of the devices. After removal of the sensor chip containing the magnetoresistive devices and other components from the wafer, the chip is bonded to a lead frame through an Ag paste layer by heat treatment. Preferably, the magnetic shield layer is made of a Ni—Fe alloy having a Ni content of 69% or less.

Abstract: In one embodiment, an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer. The interlayer insulation layer includes a conductive region formed therein. The mold layer is partially etched to expose a top surface of the etching stop layer. The exposed etching stop layer and an upper portion of the interlayer insulating layer are removed to form a first aperture part that exposes a portion of the conductive region. The conductive region exposed in the first aperture part is etched to form a second aperture part. A conductive layer for the capacitor storage node is deposited on the semiconductor substrate having the first and second aperture parts. The conductive layer provided on the mold layer is planarized to form separated capacitor storage nodes.

Abstract: There is provided a semiconductor device which is manufactured via steps of forming a capacitor which is obtained by forming in sequence an upper electrode, a dielectric film formed of ferroelectric material or high-dielectric material, and a lower electrode on a semiconductor substrate, then forming an interlayer insulating film on the capacitor, then planarizing a surface of the interlayer insulating film by the CMP polishing, then removing a moisture attached to a surface of the interlayer insulating film or a moisture contained in the interlayer insulating film by applying the plasma annealing using an N2O gas, and then forming a redeposited interlayer film on the interlayer insulating film.

Abstract: A semiconductor integrated circuit device includes a plurality of capacitor elements, which are separated from each other by a first insulating film on a plane. Each of the plurality of capacitor elements has a lower electrode, a dielectric film, and an upper electrode, and the lower electrode has a crown structure. At least one of the lower electrode and the upper electrode has a laminate structure composed of a plurality of conductive films. An outermost film of the laminate structure on a side of the dielectric film is a ruthenium film, and a portion of the laminate structure other than the outermost film has higher selective growth than the first insulating film with respect to the ruthenium film. Here, the first insulating film is desirably a tantalum oxide film.

Abstract: An MEMS device using an SOI wafer includes a first silicon layer, an insulation layer formed on the first insulation layer, a second silicon layer formed an the insulation layer, a protective layer formed on the second silicon layer, and a ground hole extending from an upper portion of the protective layer to the first silicon layer and having a conductive material therein. A handle wafer in the MEMS device is connected to the ground hole without performing any additional wiring or bonding process.

Abstract: Methods of fabricating a MIM capacitor and a dual damascene structure of a semiconductor device are disclosed.

Abstract: An imaging cell and a method of forming the imaging cell are disclosed. The imaging cell includes a first transistor that has source, a drain, and a gate, and a second transistor that has a source, a drain, and a gate connected to the source of the first transistor. In addition, the cell has a photodiode that is partially formed over the source of the second transistor.

Abstract: In a semiconductor device having a MOS transistor and a diffused resistor layer, a leakage current of a diffused resistor layer is suppressed. A film of gate electrode material is formed over the entire surface of an N-type well, a photoresist layer is formed to mask a region to form a gate electrode and portions of the diffused resistor layer and the gate electrode and a damage prevention films are formed by anisotropically etching the film of gate electrode material. After forming a CVD insulation film over the entire surface of the N-type well, sidewall spacers are formed on sidewalls of the gate electrode and the damage prevention films by anisotropically etching the CVD insulation film. A source layer and a drain layer of the MOS transistor and contact regions to the diff-used resistor layer are formed by doping portions of the N-type well and the diffused resistor layer with high concentration P-type impurities using the gate electrode, the damage prevention film and the sidewall spacers as a mask.

Abstract: A method of manufacturing a non-volatile memory cell includes forming a first dielectric layer on a substrate. A second dielectric layer having a trench is formed on the first dielectric layer. Thereafter, a pair of charge storage spacers is formed on sidewalls of the trench. A third dielectric layer is then formed over the substrate to cover the first dielectric layer, the charge storage spacers and second dielectric layer. A conductive structure is formed on the third dielectric layer over the charge storage spacers. Subsequently, portions of the third dielectric layer, the second dielectric layer and first dielectric layer not covered by the conductive structure are removed. Ultimately, source/drain regions are formed in the substrate at each side of the conductive structure.

Abstract: A method of manufacturing a ferroelectric film including: forming a ferroelectric initial nucleus layer by using a solution of a first ferroelectric material and electrodepositing the first ferroelectric material on an electrode by hydrothermal electrodeposition; electrically charging particles of a second ferroelectric material; forming a ferroelectric material film by electrodepositing the electrically-charged particles of the second ferroelectric material on the ferroelectric initial nucleus layer by electrophoretic deposition; and subjecting the ferroelectric material film to a heat treatment.

Abstract: The reduction in size, noise and voltage is realized in a MOS solid-state imaging device. A gate electrode in a pixel part is formed in a two-level structure. An amplifier gate of an amplifier transistor is formed in the first level while a select gate of a select transistor is formed in the second level. The both are structurally partly overlapped. With the first-level amplifier gate as self-alignment, ions are implanted for a select gate in the second level. Although the gate electrode if formed in one level as in the conventional requires a space of nearly a design rule between the amplifier gate and the select gate, the structure of the invention can eliminate such a dead space. Meanwhile, because the diffusion layer does not exist between the amplifier gate and the select gate, the diffusion layer is eliminated of sheet resistance and voltage drop.

Abstract: An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) has a tunneling barrier layer of substantially uniform and homogeneous Al2O3 stoichiometry. The barrier layer is formed by depositing Al on a CoFe layer or a CoFe—NiFe bilayer having an oxygen surfactant layer formed thereon, then oxidizing the Al by radical oxidation. The underlying surfactant layer contributes oxygen to the bottom surface of the Al, forming an initial amorphous Al2O3 layer. This layer produces small, uniform grains in the remaining Al layer, which promotes a uniform oxidation of the Al between its upper and lower surfaces by the subsequent radical oxidation. A final annealing process to set a pinned layer magnetization enhances the homogeneous oxidation of the layer.