Abstract: An Ethernet adapter card for automatically switching a workstation into a network is provided. The adapter card utilizes a current circuit to sense current drawn by an external communications network and a circuit for automatically switching between a card-mounted internal transceiver and the network's external transceiver whenever the external network is coupled to the workstation via an AUI port. The adapter card provides for default selection of the internal transceiver when the external communication network is disconnected from the workstation AUI port.

Abstract: A digital data communications apparatus includes first and second processing groups, each made up of a plurality of processing cells interconnected by an associated bus. An element (RRC) transfers information packets generated by the processing cells between the first and second processing groups. The RRC includes an input for receiving packets from the bus of the first processing group, as well as first and second outputs for outputting packets to the buses of the first and second groups, respectively. A control element routes packets received at the input to a selected one of the outputs based upon a prior history of routings of the datum referenced in that information packet (or requests for that data) between said first and second processing groups.

Abstract: A process for fairly allocating resources in a multiport packet switch is disclosed. Each port is connected to a station and comprises a transmit FIFO buffer and a receive FIFO buffer. The ports are connected by a broadcast transmission medium. A transmit buffer of a specific port gains access to the transmission medium when the port possesses a token which is passed from port to port in a round-robin fashion. When a port recognizes that a transmitted packet is addressed to it, the port uses a local processor to determine whether or not to accept the packet. The determination is based on (1) information in the packet header, e.g., priority and address of the transmitting port, (2) the status of the receive buffer (full or not), and (3) other locally recorded information regarding past history of the acceptance or rejection of packets from particular ports and of particular priority classes needed to achieve fairness among packets of the same class and priority among different classes.

Abstract: Broadband ATM switches for switching ATM packetized data in timeslots are disclosed. In one embodiment, the switch includes input buffer, a space switch for connecting input ports and output ports at successive timeslots and a system scheduler. The timeslot utilization processing is carried out by using a content addressable memory. A bit map is provided for registering the timeslot utilization of the input ports and the output ports. An encoder determines the earliest commonly available timeslot for connecting input ports and their requested output ports. There is further disclosed an architecture in which groups of input ports share common buffer memories and in which the system scheduler processes grouped inputs, thus taking advantage of the architecture's similar characteristics and advantages to those of the common memory switch.

Abstract: The converter comprises a memory (SRAM) having first and second ports, a first port management circuit (SPM) connected to the first port, to an incoming synchronous multiplex line (ME) and to an outgoing synchronous multiples line (MS), and a second port management circuit (APM) connected to the second port, to an incoming asynchronous link (LE) via an FIFO type packet memory (M) and to an outgoing asynchronous link (LS). An external command (MF) applied to the port management circuits selects the converter operating mode; in a first mode (M32) each time slot of a frame of a synchronous multiplexed signal is assigned to one communication channel and in a second mode (M1) all the time slots of a synchronous frame are assigned to one channel.

Abstract: Test pulses representing bits combined in bursts are generated, defined in form and amplitude, and jittered, defined by reading curve shaped characteristic data and jitter identification data from digital memories, for the purpose of simulating defined cable types and lengths and are transmitted to a unit to be tested. In a receiver, the test pulse is received and forwarded by the unit under test are accepted for the purpose of a test and are compared to the test pulses transmitted by the transmitter.

Abstract: In a digital summing process that sums non-linear digital signals by converting them to linear signals, computing their two's complement, summing the two's complements together and converting the resultant into a non-linear resultant, the fidelity of the summing process may be verified in the following manner. When only one non-linear digital signal is being summed, an algorithm determines whether the one non-linear digital signal being summed is equivalent to a predetermined value which, when passed through the summing process, will yield a different value than the one inputted. If the algorithm determines that the one non-linear digital signal is equivalent to a predetermined value, it sets a flag which indicates that the resultant over written with the predetermined value. Once the resultant is overwritten with the predetermined value, the flag is reset.

Abstract: In a communication system network that includes a processing multiplexer, a plurality of communication units, and a plurality of communication systems, each of the plurality of communication systems includes a base interface modules for interfacing the communication system with a limited number of repeaters that transceive information amongst the plurality of communication units and a processing multiplexer interface module for interfacing the communication system with the processing multiplexer. Each processing multiplexer interface module includes a base interface database that stores base interface status information of the base interface module of each of the plurality of communication systems that is periodically updated. The base interface database is updated when a processing multiplexer interface module of one of the plurality of communication systems detects a change in the base interface status information of the one of the plurality of communication systems.

Abstract: A communication procedure suitable for a cordless telephone system involves time division duplex radio communication between a handset 11 and a base station using alternating bursts of transmission over a single radio channel. Once a radio link has been set up, initial transmissions carry a synchronization logical channel S and a signalling logical channel D multiplexed together, but the link may switch to bursts carrying a communications logical channel B for the speech data and the signalling logical channel D. Burst synchronization is achieved by the asynchronous detection of words in a synchronization channel S. These words have bit patterns reducing the probability of incorrect asynchronous detection of them. If one part ceases to receive handset signals from the other, it transmits a special signal, informing the other part. This enables both parts to detect the failure of a link at substantially the same time, so that their actions to re-establish the link are synchronized.

Abstract: A switch is provided for selectively routing digital information packets received from at least first and second external sources to at least first and second external destinations. At least one of the first sources generates an information packet including a datum, or a request therefore, and a corresponding descriptor. First and second routing interconnects have inputs for receiving packets from respective sources and outputs for transmitting packets to respective destinations. The interconnects are also coupled for transferring packets between one another. Directories within the interconnects store descriptors corresponding to data associated with the first destination, as well as requests routed from the other interconnect. A controller routes packets based on the correspondence, or lack thereof, between the descriptor in that packet and an entry signal allocated to corresponding directory.

Abstract: During an existing communication between a first communication unit and at least a second communication unit, any communication unit in the existing communication may add another communication unit to the communication. This may be accomplished by initiating a request to add another communication unit. The request is routed to the affiliated system data database circuits, wherein each system data database circuit reserves an entry in each signal destination field affiliated with a communication unit that is participating in the communication when an entry is available. With the entries reserved, each of the system data database circuits adds, in the entries, individualized information of the new communication unit such that the new communication unit can now participate in the communication.

Abstract: The network access node of a digital communication system for the bidirectional transmission of message signals between, for example, a switching center and subscribers as an electrically switchable connection between the lines to the switching centers with a first interface and the lines to the subscribers with a second interface. The first interface is preferably an interface for a time-division multiplex signal with a transmission rate of 2 Mbit/s; the second interface is preferably an interface for signals in multiple access with time-division multiplex (TDM/TDMA). The buffer memory of the TDM/TDMA system is made up of partial memories arranged as a matrix. The partial memories are used simultaneously as a buffer memory for the circuit of the paths.

Abstract: In a communication system network that comprises a plurality of communication systems and a processing multiplexer, each of the plurality of communication systems is equipped with fallback operation circuitry. The fallback operation circuitry enables a communication system to operate as a standalone system when the interface buses that connect it to the processing multiplexer fail. In addition, the fallback operation circuitry enables the communication system to be reconnected to the processing multiplexer when the interface buses resume proper operation.

Abstract: In a message-transmitting station, a signal to be transferred is divided into a plurality of time slots, an error correcting/detecting code is added to each time slot, and a re-transmission sequence order number in unit of messages, a re-transmission number and an address designating ID of a terminal device are added to a specified time slot. Then, data of the time slots are transmitted from the message-transmitting station to a message-receiving station. In the message-receiving station, it is determined whether or not any order number is missing, by demodulating and decoding the data unit containing the re-transmission sequence order number and the address, and a re-transmission request signal is transferred in accordance with the result of the comparison between the sequence number included in the demodulated, decoded data unit and the sequence number received last as an indication of the condition in which the data in each data unit has reached the message-receiving station.

Abstract: In a full-duplex modem, correlation of an echo estimate signal with an echo-canceled signal is used to determine the presence or absence of a remote signal.

Abstract: In a multimedia communication terminal, a CPU generates a mode identifier and subsequently a switching signal in response to a command input as well as in response to receipt of an incoming mode identifier. Frame synchronization circuitry multiplexes an outgoing digital video signal from a video codec with the mode identifier into an outgoing composite video signal, and demultiplexes an incoming composite video signal from a distant terminal into a mode identifier and a digital video signal. In response to the switching signal, the terminal is switched from video to data communication mode by coupling a LAPB controller to an ISDN interface so that the CPU can exchange computer data and/or a mode identifier with the distant terminal without frame sync. Due to the elimination of frame sync, the terminal can access a database through the ISDN network.

Abstract: A method and apparatus for conducting a conference call among a plurality of subscriber stations. Each subscriber station contains a transmitter, a receiver, and an auxiliary receiver. An output of the auxiliary receiver can be selectively connected to an adding member that is located between a microphone and an input of the transmitter. The subscriber stations establishing the conference call connection form a transmission chain. Each subscriber station involved in the conference call, with the exception of the first subscriber station on the transmission chain, receive a user signal of a preceding subscriber station. The user signal of the preceding subscriber station is added to its own user signal to produce a compound signal that is transmitted to the next subscriber station on the transmission chain. A compound signal created in the last subscriber station of the transmission chain is supplied to the receiver of all the subscriber stations on the transmission chain.

Abstract: A method and system in which the control channels of an associated base station directly correspond to certain time slots of a radio channel frame, which also includes time slots being utilized for traffic channels. The time slots being utilized as control channels are marked with uniquely defined control channel indicators which include unique Sync Words and unique control channel identification words. The mobile station recognizes the uniquely defined control channel indicators and identifies those particular time slots as control channels so as to distinguish from the time slots which are not being used as control channels.

Abstract: Methods and apparatus are provided for interconnecting first and second information buses each having a plurality of data lines. A pair of unidirectional information paths each consisting of twisted-pair cables are provided, along with a 25 MHz strobe. Information is transmitted using pseudo-ECL signal levels. A pair of clock differential receiver circuits is provided such that data is transferred over the interconnect bus using both the rising and falling edges of the transmitted clock signal and transferred from one bus to another at a rate of 50 MHz.

Abstract: A digital crossbar switch designed to facilitate easy and flexible interconnection of up to 8 data ports. The device includes 8 bidirectional ports, each 8 bit wide. Interconnection of the ports is controlled by 32 stored control memory locations associated with each port. The controlling memory locations can be changed dynamically without interfering with data flow. Additional program flexibility can be achieved by providing each port with a 16 word first-in first-out data buffer. The capability to bit reverse the data on any of the ports is also provided to simplify the interconnection of busses from different architectures. The device is fully expandable to wider busses, has extensive test capability and a master reset is provided for system initialization.