Abstract: A memory location is assigned to each virtual circuit, this location containing a context (CT) that defines the evaluation conditions for measuring the throughput of the virtual circuit and then, upon reception of each cell, providing for the context relating to the virtual circuit to which the cell belongs to be read. A clock signal is adapted to supply a current time associated with this virtual circuit. An indication of the measuring interval start time is written into the context (CT) for a virtual circuit upon arrival of a first cell for this virtual circuit. Upon the arrival of a subsequent cell for this virtual circuit, the context is read and from the current time (hc) the time interval start time is subtracted. The time difference is compared to a specified measurement interval duration and the number of cells already received is incremented.

Abstract: A digital signal multiplexing apparatus has n (n is an arbitrary integer) multiplexing circuits (11-1n) for converting input signals from a plurality of lines into m (m is an arbitrary integer) parallel signals which are added with added bits and have a first transmission speed. A parallel-serial conversion circuit (40) converts the m parallel signals from the n multiplexing circuits into a serial multiplexed signal by a parallel-serial conversion. A bus (30) connects the n multiplexing circuits and the parallel-serial conversion circuit. The n multiplexing circuits respectively have a circuit for successively transmitting the m parallel signals to the bus using a pluse signal having a second transmission speed which is n times the first transmission speed. A digital signal demultiplexing circuit has a serial-parallel conversion circuit (75) for converting a serial input signal into m (m is an arbitrary integer) parallel signals having a predetermined transmission speed.

Abstract: A multiplexer for the transmission of signals on different carrier frequencies includes a Butler matrix with a set of delay elements secured to output terminals of the matrix. Each of the delay elements differs from the other delay elements in that the delays imparted to signals by each of the elements differ by an integral number of delay units. The selection of frequency values is made in accordance with the increment in delay unit so as to develop incremental values of phase shift which compensate for phase shift introduced by the phase shift taper of a Butler matrix. This permits summation of signals from plural input ports of the matrix without the generation of intermodulation products among the various signal channels.

Abstract: In a digital communications network, data packets are prevented from making a transit through a domain if such data packets neither originate within nor are addressed to a node within that domain. Only data packets flagged as originating within the domain are allowed to be forwarded out of the domain.

Abstract: A memory location is assigned to each virtual circuit, this location containing a context (CT) that defines the evaluation conditions for measuring the throughput of the virtual circuit and then, upon reception of each cell, providing for the context relating to the virtual circuit to which the cell belongs to be read. A clock signal is adapted to supply a current time associated with this virtual circuit, and throughput measurement circuits supply, at the arrival of a cell, a virtual circuit throughput measurement for this virtual circuit.

Abstract: A frequency-hopping packet communication system without a master clock or master control unit is based on use of a receiver's frequency hopping timing and identification to control communication. A frequency-hopping band plan, involving the number of channels and the pseudo-random pattern of frequency change and nominal timing of changes, is universally known to each node in the network. A transmitter acquires synchronization with a target node by use of information previously received from or about a target indicating timing of present idle frequency hop of the target receiver. Each receiving node establishes in each station or node a table of receiver frequency hopping sequence offsets (hop timing offsets) of each other node within its communication range, and each node announces its presence on each frequency in a packet with a hop timing offset indicator. The hop timing offset indicator is a key used to read a table to allow nodes to set themselves in synchronization with one another.

Abstract: The incoming cells of a input asynchronous time-division multiplex channel (mtr) are counted by a counter (FFB) assigned to each virtual circuit which is incremented on each incoming cell of the virtual circuit and decremented periodically. Clock signals define consecutively numbered cell times (ntc). Queue and chaining table (FAVE, FCVN) define a cell time queue (FAF, FAL, FAV) specific to each of the cell times, a virtual circuit being assignable to a cell time by writing its identifier into the corresponding cell time queue. A controller (MC) uses the content of the cell time queues (FAF, FAL, FAV) and, for each cell time, identifies a virtual circuit to be processed and decrements the counter (FFB) belonging to this virtual circuit. The controller further includes arrangements whereby any virtual circuit whose counter is not idle is assigned to one of the cell times to be decremented by virtue of the arrival of this cell time.

Abstract: The device comprises an input unit for generating coded data to be transmitted, an FSK coder-modulator for modulating, by frequency shift, the coded data to be transmitted, in a frequency range located between about 15 and 18 KHz, a mixer circuit for superimposing, with an attenuation of 20 to 40 dB, the signals modulated by frequency shift on a low-frequency signal of a traditional program to be applied to a frequency modulation radio transmitter, a decoder comprising filter circuits and an FSK demodulator for separating the coded data from the signals delivered by a standard frequency modulation receiver, and a display or recording unit for displaying or recording the demodulated, filtered, transmitted coded data.

Abstract: An arrangement for conducting a conference call over a distributed digital network in which, at each station connected to the conference call, only voice packets from the other stations connected to the conference call are received. To avoid the need for synchronization between stations connected to the conference call, a local time base is established to define a sequence of periodic intervals during which a single voice packet will be accepted from each station connected to the conference call. The interval is advantageously set to be approximately equal the sampling period for data in a received data packet which will be reasonably uniform for all stations on the network. This provides that, typically, a maximum of one data packet will be received from any selected station during a single time base interval.

Abstract: An access controller for peer-to-peer communication networks which monitors the data packets transmitted between stations, determines when an access that needs to be controlled is being made, and then either destroys the packet or transmits one or more packets which appear as legitimate message packets to the stations but which, in fact, terminates or alters the communication path between the two stations. Since the invention is free of any particular protocol restrictions, it can be implemented with any type of protocol and at any layer of that protocol. And since the access control mechanism is neither part of the physical communication path nor part of the communication primitives, the stations cannot detect, in any direct sense, that their access is being controlled, and they do not need to be programmed to follow any special control protocols, or to use encryption.

Abstract: A method of arbitration for transmit mode access to the synchronous transmission medium of a distributed switching network whose architecture is based on a transmission medium time-shared between different stations, in which carries information in repetitive time positions, and in which a nominal time position being assigned on the basis of predetermined access criteria to respective stations communicating within the network, and spillover of stations outside the nominal time positions thus assigned is allowed. The arbitration method allocates an increasing access priority for an increasing seniority due to such spillover.

Abstract: A Synchronous Multiport Digital Communications Network (SMDCN) including a HEAD end Unit (HEADU) and SUBscriber Units (SUBU) providing a large number of simultaneous isolated two-way dial-up digital communications channels between a common head end facility and a large number of subscriber facilities over a broadband transmission medium such as coaxial cable or optical fiber arranged in a bus or tree topology, such as a local area network (LAN) or a cable television (CATV) network. The basic digital channel provided is a 64,000 bit per second data stream, the current standard of the digital telephone industry's T1 technology, and therefore readily accommodates voice telephone services. However, the network expressly accommodates higher bit rates up to 1.544 MB/s by combining basic channels.

Abstract: A method and apparatus for disabling an echo canceller in a digital telephone network. An originating DSU transmits a sequence of synchronization codes which are shifted by the various delays in the network. The answering DSU receives the shifted codes and determines how much adjustment is required by the originating modem in order to have byte boundaries aligned with those of the network. The answering DSU then transmits this information back to the originating DSU so that the originating DSU can adjust its transmit time to align with the byte boundaries of the network. The originating DSU then transmits byte aligned 2100 Hz tone samples in order to disable the network's echo canceller.

Abstract: A time division duplex transceiver incorporating a dual conversion superheterodyne receiver, and in which the first receiver local oscillator doubles as the frequency source for the transmitter. The oscillator is a voltage controlled oscillator VCO forming part of a mixer-type phase locked loop. Frequency deviation in the loop is achieved by mixing the VCO output with a selected harmonic of the output of the second receiver local oscillator. The reference oscillator is a crystal controlled oscillator whose output is switched as between transmit mode and receive mode at a switch before being passed to the loop phase detector. The transceiver is able to rapidly and repeatedly alternate between transmit and receive modes and is thus well suited to time division multiplex operation.

Abstract: A cell synchronizing apparatus and method for synchronizing the transmission and reception of a data train between switching systems. The data train is sectioned into a plurality of packeted data cells and synchronization cells of equal fixed length. A synchronization pattern is included in each synchronization cell. A time position of the synchronization pattern is detected and sequentially stored in a memory. Synchronization is determined from the relative positional relationship among time positions of equal value stored in the memory.

Abstract: A method and associated node structure (11) for the efficient and reliable transmission of delay sensitive traffic in a packet network (10) is disclosed. The method provides bounded end-to-end delay for all delay sensitive traffic and can guarantee loss-free transmission to that part of the delay sensitive traffic which has such a stringent requirement. To achieve statistical multiplexing gain, some loss is permitted for the rest of the delay sensitive traffic, with discrimination among different loss priority classes based on the corresponding degree of loss sensitivity. Bounded end-to-end delay is obtained by performing statistical multiplexing at the switching nodes (11) on a duration limited basis through use of a unique queuing discipline at the network nodes (11). This queuing discipline is instrumental in guaranteeing loss free transmission for the class of traffic with such a requirement.

Abstract: In a packet network which includes a plurality of packet switching stations and in which a packet including in its header portion a VPI (Virtual Path Indentifier) for identifying one of logical paths multipliexed on a transmission line and a VCI (Virtual Connection Identifier) for identifying one of logical connections multiplexed on one logical path is communicated between the switching stations, each switching station preliminarily designates a VCI to be given to a packet directed to that station when a logical connection is to be set up between that station and another station. When receiving an information packet from the other station, the each station makes access to header label conversion tables on the basis of a VCI included in the received packet to read internal routing information necessary for a packet switching operation and a VCI to be given to a packet to be delivered.

Abstract: A memory (MCT) is used in which a location is assigned to each virtual circuit, this location containing a context (CT) that defines the evaluation conditions of the throughput of the virtual circuit and, upon reception of each cell, providing for the context relating to the virtual circuit to which the cell belongs to be read, for the purpose of evaluating the throughput of the virtual circuit. A clock signal (BC) is used to supply a current time associated with this virtual circuit.

Abstract: The standard FDDI priority algorithm is implemented by programming Token Holding Time (THT) threshold values for asynchronous service either in an increasing or decreasing order as a function of token holding time. If the thresholds are programmed in a decreasing order, all higher priority data is sent to the network before any lower priority data is sent. If the thresholds are programmed in an increasing order, highest priority data is sent first, until the unexpired token holding time falls below the threshold value for that priority; the next lower priority level data then is transmitted, and so on. Accordingly, at least some data of all priority assignments pending for transmission are sent to the medium during each token capture.

Abstract: A synchronous, interleaved, time-division M:1 multiplexor. Following an input stage of parallel synchronous latches for latching M incoming parallel data bits (where M is an integer power of two equal to or greater than four) is an intermediate stage of parallel synchronous latches. The intermediate latches are clocked with selected phases of an M-phase clock having M equally-spaced phases of a clock signal having a frequency of B/M (where B is the outgoing bit rate) to latch each bit at a time at least 2/B (i.e., two outgoing bit periods) after such bit is received from its respective input latch. A first stage of 2:1 multiplexors, following the intermediate latches and used to begin multiplexing the latched bits, are clocked with selected phases of the M-phase clock to begin multiplexing each bit at a time at least 1/B (i.e., one outgoing bit period) after such bit is received from its respective intermediate latch.