Patents Examined by H Tsai
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Patent number: 9613811Abstract: A first protective layer, a mask layer, a second protective layer and a photoresist layer are sequentially formed on a substrate. A photoresist pattern is formed by partially removing the photoresist layer. An ion implantation mask is formed by sequentially etching the second protective layer, the mask layer and the first protective layer using the photoresist pattern. The ion implantation mask exposes the substrate. Impurities are implanted in an upper portion of the substrate exposed by the ion implantation mask.Type: GrantFiled: October 28, 2014Date of Patent: April 4, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Jik Baek, Sang-Jine Park, Bo-Un Yoon, Young-Sang Youn, Ji-Min Jeong, Ji-Hoon Cha
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Patent number: 9568826Abstract: A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is adherable, the device layer including a shot area and a scribe line area; a step of removing a portion, of the intermediate layer, formed in the scribe line area; a step of exposing an image of a mark on the scribe line area and forming, based on the image of the mark, a mark including recessed portion; and a step of applying the polymer layer containing the block copolymer on the device layer of the wafer. When a circuit pattern is forced by using the self-assembly of the block copolymer, it is possible to form the mark simultaneously with the formation of the circuit pattern.Type: GrantFiled: January 6, 2015Date of Patent: February 14, 2017Assignee: NIKON CORPORATIONInventor: Tomoharu Fujiwara
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Patent number: 9559253Abstract: A method of manufacturing a nitride semiconductor element includes preparing a wafer having a nitride semiconductor layer which includes p-type dopants, forming an altered portion by condensing laser beam on the wafer, and after the forming an altered portion, forming a p-type nitride semiconductor layer by subjecting the wafer to annealing.Type: GrantFiled: October 29, 2014Date of Patent: January 31, 2017Assignee: NICHIA CORPORATIONInventors: Junya Narita, Yohei Wakai, Kazuto Okamoto, Mizuki Nishioka
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Patent number: 9553177Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.Type: GrantFiled: June 18, 2015Date of Patent: January 24, 2017Assignee: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn
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Patent number: 9536731Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).Type: GrantFiled: October 24, 2014Date of Patent: January 3, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ZEON CORPORATIONInventors: Robert L. Bruce, Sebastian U. Engelmann, Eric A. Joseph, Mahmoud Khojasteh, Masahiro Nakamura, Satyavolu S. Papa Rao, Bang N. To, George G. Totir, Yu Zhu
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Patent number: 9536958Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.Type: GrantFiled: June 11, 2014Date of Patent: January 3, 2017Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Frank Pfirsch, Hans-Joerg Timme
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Patent number: 9502316Abstract: A method for producing a plurality of optoelectronic components may include measuring at least one measurement parameter for a first optoelectronic component and a second optoelectronic component, and processing the first optoelectronic component and the second optoelectronic component taking account of the measured measurement parameter value of the first optoelectronic component and the measured measurement parameter value of the second optoelectronic component, such that the optoelectronic properties of the first optoelectronic component and the optoelectronic properties of the second optoelectronic component are changed in a different way toward at least one common predefined optoelectronic target property. The processing of at least one value of a measurement parameter of the optoelectronic properties of the first optoelectronic component or of the optoelectronic properties of the second optoelectronic component toward the optoelectronic target property is formed by means of a compensation element.Type: GrantFiled: April 24, 2013Date of Patent: November 22, 2016Assignee: OSRAM OLED GMBHInventors: Simon Schicktanz, Daniel Steffen Setz
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Patent number: 9496362Abstract: A technique relates to forming a semiconductor device. Sacrificial gates are formed on a channel region of a substrate. Epitaxial layers are grown on source-drain areas between the sacrificial gates. A contact liner and contact material are deposited. The liner and the contact material are removed from above the sacrificial gates. Contact areas are blocked with one or more masking materials and etched. The masking material is removed. The contact material is partially recessed and a nitride liner deposited. An oxide layer is deposited and the sacrificial gate is removed. A metal gate is formed on the channel region and recessed. Insulator material and metal gate material are recessed and a cap is formed over the gate.Type: GrantFiled: January 4, 2016Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Emre Alptekin, Ravikumar Ramachandran, Viraj Y. Sardesai
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Patent number: 9482902Abstract: A liquid crystal display device is fabricated by forming a first alignment layer on a first base substrate. A second alignment layer is formed on a second base substrate. A liquid crystal is disposed on one of the first alignment layer and the second alignment layer. The first base substrate and the second base substrate are combined. At least one of the first alignment layer and the second alignment layer is formed by forming an alignment solution on a corresponding base substrate. An alignment layer is formed by curing the alignment solution. The alignment layer is aligned by radiating a light onto the base substrate, first cleaning the base substrate, and baking the alignment layer.Type: GrantFiled: December 10, 2013Date of Patent: November 1, 2016Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Jin-Soo Jung, Junwoo Lee, Baekkyun Jeon, Bongsung Seo
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Patent number: 9478420Abstract: A method for depositing a Group III nitride semiconductor film on a substrate is provided that comprises: providing a sapphire substrate; placing the substrate in a vacuum chamber; conditioning a surface of the substrate by etching and providing a conditioned surface; holding the substrate away from a substrate facing surface of a heater by a predetermined distance; heating the substrate to a temperature by using the heater whilst the substrate is held away from the substrate facing surface of the heater, and depositing a Group III nitride semiconductor film onto the conditioned surface of the substrate by a physical vapour deposition method whilst the substrate is held away from the substrate facing surface of the heater and forming an epitaxial Group III nitride semiconductor film with N-face polarity on the conditioned surface of the substrate.Type: GrantFiled: December 15, 2014Date of Patent: October 25, 2016Assignee: EVATEC AGInventors: Lorenzo Castaldi, Martin Kratzer, Heinz Felzer, Robert Mamazza, Jr.
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Patent number: 9449976Abstract: A novel semiconductor device structure includes a first-conductivity-type semiconductor substrate, an isolated region, a first-conductivity-type MOS region, and a second-conductivity-type MOS region. A first-conductivity-type MOS transistor locates in the first-conductivity-type MOS region with a second-conductivity-type well surrounding, and a first-conductivity-type deep well surrounding the second-conductivity-type well with a second-conductivity-type deep well surrounding. In the second-conductivity-type MOS region, a second-conductivity-type MOS transistor is formed with a first-conductivity-type well surrounding. The first-conductivity-type deep well and the second-conductivity-type deep well are sufficiently reducing the noise and current leakage from other devices or from the semiconductor substrate.Type: GrantFiled: December 12, 2013Date of Patent: September 20, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Ching Wu, Hsiang-Hui Tsai, Po-Jen Wang, Hung-Che Liao
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Patent number: 9443950Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The second electrode layer is connected with at least a part of a surface of the first electrode layer which is opposite to a surface of the first electrode layer that is in contact with the n-type semiconductor layer.Type: GrantFiled: December 12, 2013Date of Patent: September 13, 2016Assignee: TOYODA GOSEI CO., LTD.Inventors: Toru Oka, Nariaki Tanaka
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Patent number: 9443718Abstract: Provided is a method including forming a film including a predetermined element, oxygen and at least one element selected from a group consisting of nitrogen, carbon and boron on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a source gas to the substrate wherein the source gas contains the predetermined element, chlorine and oxygen with a chemical bond of the predetermined element and oxygen, and supplying a reactive gas to the substrate wherein the reactive gas contains the at least one element selected from the group consisting of nitrogen, carbon and boron.Type: GrantFiled: December 11, 2013Date of Patent: September 13, 2016Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Katsuyoshi Harada, Yoshiro Hirose, Atsushi Sano
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Patent number: 9437566Abstract: In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.Type: GrantFiled: May 12, 2014Date of Patent: September 6, 2016Assignee: Invensas CorporationInventors: Rajesh Katkar, Cyprian Emeka Uzoh
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Patent number: 9437479Abstract: Embodiments of methods for forming interconnect patterns on a substrate are provided herein. In some embodiments, a method for forming an interconnect pattern atop a substrate includes depositing a porous dielectric layer atop a cap layer and a plurality of spacers disposed atop the cap layer, wherein the cap layer is disposed atop a bulk dielectric layer and the bulk dielectric layer is disposed atop a substrate; removing a portion of the porous dielectric layer; removing the plurality of spacers to form features in the porous dielectric layer; and etching the cap layer to extend the features through the cap layer.Type: GrantFiled: October 24, 2014Date of Patent: September 6, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Suketu A. Parikh, Mehul Naik
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Patent number: 9425372Abstract: The LED device (27) has a LED bare chip (25) mounted directly on a metal contact (28), and supplies power to the bare chip and conducts heat from the bare chip via the metal contact.Type: GrantFiled: January 18, 2011Date of Patent: August 23, 2016Assignee: Japan Aviation Electronics Industry, LimitedInventor: Hideyuki Kanno
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Patent number: 9425038Abstract: A method for forming a silicon oxycarbonitride film includes supplying a gas containing a silicon precursor having an oxygen-containing group onto a process surface of a workpiece, supplying a gas containing a carbon precursor onto the process surface, and supplying a nitriding gas onto the process surface subjected to the supplying a gas containing a silicon precursor and the supplying a gas containing a carbon precursor. The silicon oxycarbonitride film is formed on the process surface by the supplying the gas containing the silicon precursor, the supplying gas containing the carbon precursor and the supplying a nitriding gas without performing an oxidation process.Type: GrantFiled: October 28, 2014Date of Patent: August 23, 2016Assignee: TOKYO ELECTRON LIMITEDInventor: Akira Shimizu
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Patent number: 9419092Abstract: A silicon carbide device has a termination region that includes a mesa region that links the termination region to an active area of the device and that includes one or more trenches.Type: GrantFiled: March 1, 2006Date of Patent: August 16, 2016Assignee: Vishay-SiliconixInventors: Rossano Carta, Laura Bellemo
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Patent number: 9412714Abstract: A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements at the first surface within the second region; a support structure having a third surface and a fourth surface remote from the third surface and overlying the first surface within the second region in which the third surface faces the first surface, second and third electrically conductive elements exposed respectively at the third and fourth surfaces and electrically connected to the conductive elements at the first surface in the first region; and wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases.Type: GrantFiled: May 30, 2014Date of Patent: August 9, 2016Assignee: Invensas CorporationInventors: Reynaldo Co, Wael Zohni, Rizza Lee Saga Cizek, Rajesh Katkar
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Patent number: 9406626Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.Type: GrantFiled: May 16, 2014Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsiao-Chun Lee, Chi-Feng Huang, Victor Chiang Liang