Abstract: A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.

Abstract: Methods and apparatus for routing signal paths in an integrated circuit. One or more signal routing paths for transferring signals of the integrated circuit may be determined. A dummy fill pattern for the integrated circuit may be determined based on the one or more metal density specifications and at least one design rule for reducing cross coupling capacitance between the dummy fill pattern and the routing paths. The signal routing paths and/or the dummy fill pattern may be incrementally optimized to meet one or more timing requirements of the integrated circuit.

Abstract: A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.

Abstract: Provided is a method for fabricating a phase change memory device. The method includes forming a plurality of bottom electrodes on a substrate, forming a first mold layer on the substrate to extend in a first direction where the bottom electrodes are exposed, forming a second mold layer on the substrate, the second mold layer extending in a second direction orthogonal to the first direction to expose parts of the bottom electrodes, forming a phase change material layer on the first and second mold layers to be connected to parts of the bottom electrodes dividing the phase change material layer as a plurality of phase change layers respectively connected to the parts of the bottom electrodes and forming a plurality of top electrodes on the phase change layers.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention including a plurality of first active areas which are provided in the memory cell array side-by-side in a first direction and which have a dimension smaller than a fabrication limit dimension obtained by lithography, a second active area provided between the first active areas adjacent in the first direction, a memory cell unit which is provided in each of the plurality of first active areas and which has memory cells and select transistors, and a linear contact which is connected to one end of the memory cell unit and which extends in the first direction, wherein an area in which the linear contact is provided is one semiconductor area to which the plurality of first active areas are connected by the plurality of second active areas, and the bottom surface of the linear contact is planar.

Abstract: Example embodiments are directed to a method of growing GaN single crystals on a silicon substrate, a method of manufacturing a GaN-based light emitting device using the silicon substrate, and a GaN-based light emitting device. The method of growing the GaN single crystals may include forming a buffer layer including a TiN group material or other like material on a silicon substrate, forming a nano-pattern including silicon oxide on the buffer layer, and growing GaN single crystals on the buffer layer and the nano-pattern.

Abstract: A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV is can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias.

Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line and a data line on the substrate and crossing each other to define a pixel region, a thin film transistor connected to the gate line and the data line, a first passivation layer on the thin film transistor and having a first unevenness structure at its top surface, an auxiliary unevenness layer on the first passivation layer and having a first roughness structure at its top surface, and a reflector on the auxiliary unevenness layer, the reflector having a second unevenness structure due to the first unevenness structure of the first passivation layer and a second roughness structure due to the first roughness structure of the auxiliary unevenness layer, the second roughness structure having smaller patterns than the second unevenness structure.

Abstract: First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.

Abstract: To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed.

Abstract: Methods of fabricating a light-emitting device are provided. A light-emitting device can be formed from bonding a lens including a plug and a cap to an LED package including a socket configured to receive the plug. The lens can be fabricated using an injection mold formed from a well secured to the LED package and injecting a material into the injection mold to cure into a shape of the lens. The lens can also be fabricated using a blank about the shape of the lens and machining the blank to produce the plug and the cap of the lens. The lens can be bonded to the LED package using a convex bead of adhesive deposited on the surface of the LED package and spreading the adhesive between the lens and the LED package.

Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.

Abstract: A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

Abstract: A chemical bath deposition method based on a new CBD reactor is presented to prepare different thin films on continuous flexible substrates in roll-to-roll processes. In particular, they are useful to deposit CdS or ZnS buffer layers in manufacture of thin film solar cells. This method deposits thin films onto vertically travelling continuous flexible workpieces delivered by a roll-to-roll system. The thin films are deposited with continuously spraying the reaction solutions from their freshly mixed styles to gradually aged forms until the designed thickness is obtained. The substrates and the solutions are heated to a reaction temperature. During the deposition processes, the front surfaces of the flexible substrates are totally covered with the sprayed solutions but the substrate backsides are remained dry. The reaction ambience inside the reactor can be isolated from the outside atmosphere. The apparatus is designed to generate a minimum amount of waste solutions for chemical treatments.

Abstract: Method and apparatus for direct writing of passive structures having a tolerance of 5% or less in one or more physical, electrical, chemical, or optical properties. The present apparatus is capable of extended deposition times. The apparatus may be configured for unassisted operation and uses sensors and feedback loops to detect physical characteristics of the system to identify and maintain optimum process parameters.

Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

Abstract: A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.

Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.

Abstract: Methods and apparatus for routing signal paths in an integrated circuit. One or more signal routing paths for transferring signals of the integrated circuit may be determined. A dummy fill pattern for the integrated circuit may be determined based on the one or more metal density specifications and at least one design rule for reducing cross coupling capacitance between the dummy fill pattern and the routing paths. The signal routing paths and/or the dummy fill pattern may be incrementally optimized to meet one or more timing requirements of the integrated circuit.

Abstract: A tapered roller bearing (31a) has a plurality of retainer segments (11a, 11d) each having a pocket to house a tapered roller (34a), and arranged so as to be continuously lined with each other in a circumferential direction between an outer ring (32a) and an inner ring (33a). The retainer segment (11a, 11d) is formed of a resin containing a filler material to lower a thermal linear expansion coefficient. In addition, a clearance (39a) is provided between the first retainer segment (11a) and the last retainer segment (11d) after the plurality of retainer segments (11a, 11d) have been arranged in the circumferential direction without providing any clearance. Here a circumferential range (R) of the clearance (39a) is larger than 0.075% of a circumference of a circle passing through a center of the retainer segment (11a, 11d) and smaller than 0.12% thereof at room temperature.