Abstract: A memory device may include a memory cell array, and a write driver and sense amplifier connected to the memory cell array through bit lines. The memory cell array includes a first cell area including a plurality of first memory cells arranged on a plane corresponding to a first direction and a second direction, a second cell area including a plurality of second memory cells arranged on the plane disposed on one side of the first cell area in the first direction, a word line extending in the first direction and is connected to the plurality of first memory cells and the plurality of second memory cells, first bit lines extending in the second direction and are respectively connected to the plurality of first memory cells, and second bit lines extending in the second direction and are respectively connected to the plurality of second memory cells.

Abstract: An embedded next generation access control system imposes fine-grained access control on data in a resource database and includes a resource database, NGAC database, administrator, and mediator. The resource database includes controlled resource data and a mediator. The NGAC database includes an adjudicator and access control policy data. The administrator communicates access control policy input to the NGAC database upon which access control policy data is made in the NGAC database. The controlled resource data is access controlled by access control policy data via calls of an adjudicator API, which implements Next Generation Access Control standard by NIST, by the resource database to obtain access decisions. The adjudicator determines which controlled resource data are accessed by a user and provides an access control list for each user and user attribute. The adjudicator also provides a prohibited access control list for a user and user attributes in the access control policy data if there are any.

Abstract: A semiconductor device includes a base chip configured to output a strobe signal and a control signal and to output a first update signal and a second update signal in response to receiving first and second core strobe signals, a first core chip configured to generate the first core strobe signal by delaying the strobe signal by a first delay amount while a pulse of the control signal is input, to output the first core strobe signal to the base chip, and to calibrate the first delay amount while the first update signal is enabled, and a second core chip configured to generate the second core strobe signal by delaying the strobe signal by a second delay amount when a pulse of the control signal is input, to output the second core strobe signal to the base chip, and to calibrate the second delay amount while the second update signal is enabled.

Abstract: For each voltage offset bin of a plurality of voltage offset bins, a corresponding period of scan operations of memory blocks associated with the voltage offset bin is determined. For each voltage offset bin of the plurality of voltage offset bins, a corresponding scheduling time offset of scan operations is determined. For a chosen voltage offset bin, based on a period of scan operations associated with the chosen voltage offset bin and a scheduling time offset associated with the chosen voltage offset bin, a scan operation is scheduled. The scan operation with respect to one or more blocks associated with the chosen voltage offset bin is performed.

Abstract: Technology for re-calibrating a temperature coefficient (Tco) for reading NAND memory cells. The Tco may be re-calibrated based on an amount of data retention impact to NAND memory cells since the NAND memory cells were programmed. The data retention impact may be measured by determining a shift to a candidate Vt distribution. The candidate Vt distribution may be selected as one that exhibits a significant data retention impact. The Tco may include, but is not limited to a bit line voltage Tco or a Vread Tco. The bit line voltage Tco may be used to establish the bit line voltage during read. The Vread Tco may be used to establish a voltage to unselected word lines during read.

Abstract: A memory apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes defining channels. The memory cells form a block including a first sub-block and a second sub-block disposed vertically above the first sub-block. A control means is configured to pre-charge the channels of the memory holes in a pre-charge operation. The control means applies each of a series of programming pulses of a program voltage in a program phase followed by verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines in a verify phase to program and verify the memory cells connected thereto during program loops. The pre-charge operation for the second sub-block occurs during the verify phase of a previously occurring one of the plurality of program loops.

Abstract: Embodiments described herein relate to methods and apparatuses for providing communication between a server and a client device via a proxy node. A method, in a proxy node, wherein the proxy node includes an intermediate node between a server and a client device includes receiving encrypted traffic transmitted between the client device and the server; receiving a key from the client device; performing a service in relation to the encrypted traffic to generate information; encrypting the information using the key to generate encrypted information; and transmitting the encrypted information to the server.

Abstract: A memory system includes: an address scrambler suitable for scrambling an address based on a scrambling rule to generate a scrambled address; a memory core including a plurality of memory cells and suitable for storing data in memory cells designated by the scrambled address; and a scramble control circuit suitable for changing the scrambling rule in response to satisfaction of an attack condition.

Abstract: Described herein is a method and apparatus to reduce electric displacement and polarization target for a memory bit-cell. In at least one embodiment, the apparatus comprises one or more circuitries to adjust voltage on a plate-line to be above or below a nominal voltage of the plate-line based on a write operation or read operation on a bit-cell. In at least one embodiment, the bit-cell comprises a transistor and a capacitor including non-linear polar material, wherein the capacitor has a first terminal coupled to the plate-line and a second terminal coupled to the transistor.

Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

Abstract: An operating method of a storage device includes a storage controller and a non-volatile memory device. The method includes providing, by the storage controller, the non-volatile memory device with a first command indicating a temperature read operation, providing, by a temperature sensor of the non-volatile memory device, a first measurement temperature value to the storage controller based on the first command, determining, by the storage controller, whether the first measurement temperature value is lower than a first threshold value, providing, by the storage controller, the non-volatile memory device with a second command indicating a dummy read operation in response to determining that the first measurement temperature value is smaller than the first threshold value, and performing, by the non-volatile memory device, the dummy read operation for heating based on the second command.

Abstract: The testing system comprises a processor and a local memory on a motherboard and an extension memory device under test (DUT). The local memory corresponds to a first address range within system memory and the extension memory DUT associated with a second address range within the system memory. The processor is operable to direct write latency testing of the extension memory DUT, including recording write latency measurement values. The recording can be done in a frequency table and the frequency table can be visualized (e.g., rendered, etc.) on a display. The testing comprises non-temporal write instructions that bypass processor caches. The extension memory DUT is compatible with a compute express link (CXL) protocol.

Abstract: The present disclosure relates to a method, a device, and a computer program for constructing a quantum cryptographic communication network.

Abstract: A sensing circuit and a control method of the sensing circuit are provided. The sensing circuit includes a data line, a complementary data line, a read bit line, a complementary read bit line, a read pass gate circuit and logic circuit. The logic circuit enables the read pass gate circuit when a voltage level on the read bit line and a voltage level on the complementary read bit line are pre-charged to a first voltage level, and disable the read pass gate circuit when one of the voltage level on the read bit line and the voltage level on the complementary read bit line is pull to a second voltage level different from the first voltage level. The read pass gate circuit is enabled to connect the data line to the read bit line and connect the complementary data line to the complementary read bit line.

Abstract: Systems and methods for providing a compliance solution for data storage (e.g., in compliance with a more restrictive solution chosen from among a plurality of storage solutions) are disclosed herein. The methods include receiving a request to store data, accessing a first set of jurisdictional rules applicable to storage of the data, accessing a second set of jurisdictional rules applicable to storage of the data that is divergent from the first set of jurisdiction rules with respect to storage of the data, determining that a first jurisdictional restriction among the first set of jurisdictional rules applicable to storage of the data is more restrictive than a first jurisdictional restriction among the second set of jurisdictional rules applicable to storage of the data, and storing the data in compliance with the first jurisdictional restriction among the first set of jurisdictional rules applicable to storage of the data.

Abstract: An example memory device includes: memory cells constituting memory cell rows coupled to word lines and memory strings coupled to bit lines; and a peripheral circuit configured to: perform a read operation on the memory cells connected to a first word line to obtain at least two read values; during the read operation performed on the memory cells connected to the first word line, divide the memory cells connected to a second word line into at least two groups based on threshold voltages of the memory cells connected to the second word line; and determine read results of the memory cells connected to the first word line from the at least two read values based on grouping information of the memory cells connected to the second word line. The first word line and the second word line are word lines adjacent to each other.

Abstract: A computer-implemented method (CIM), according to one approach, includes determining a first domain of operation associated with a first client, and creating a software security object that satisfies a current standard and/or ruleset associated with the first domain. The method further includes distributing the software security object to the first client, and in response to a determination that the current standard and/or ruleset has been updated, causing the software security object to be updated to conform to the updated standard and/or ruleset. A computer program product (CPP), according to another approach, includes a set of one or more computer-readable storage media, and program instructions, collectively stored in the set of one or more storage media, for causing a processor set to perform any combination of features of the foregoing methodology.

Abstract: The present disclosure relates to an information processing device, a mobile device, and a communication system capable of updating a session key. A first secret is derived from a key schedule by using first communication including transmission or reception of a command for controlling second communication faster than the first communication or a response to the command, a first session key related to the first secret is derived, the first session key is used for encryption or message authentication of the first communication, a second session key is received, transmitted, or derived by using the first communication, the second session key is used for encryption or message authentication of the second communication, a third session key is received, transmitted, or derived by using the first communication, and the third session key is used instead of the second session key.

Abstract: A memory circuit includes a first memory cell array configured to store data, and a second memory cell array. The second memory cell array is configured as a first logic circuit or a second logic circuit in response to a first set of control signals. The first logic circuit is configured to perform a first logic function on a first set of data signals based on a second set of control signals. The second logic circuit is configured to perform a second logic function on the first set of data signals based on the second set of control signals. The second logic function is different from the first logic function. The first set of data signals is part of the data stored in the first memory cell array. The first memory cell array and the second memory cell array are embedded in a same memory cell array.

Abstract: A computer-implemented method and system for managing access control policies for diverse database tables. The method involves consolidating access control by associating each table with a common set of access control policies, enforcing these policies to control access, and providing automated management without administrator input. The automated management includes auditing the policies, detecting discrepancies, and remedying them by modifying the policies. The system comprises at least one physical processor and memory containing instructions that, when executed, perform the method described.