Abstract: The present disclosure relates to an information processing device, a mobile device, and a communication system capable of updating a session key. A first secret is derived from a key schedule by using first communication including transmission or reception of a command for controlling second communication faster than the first communication or a response to the command, a first session key related to the first secret is derived, the first session key is used for encryption or message authentication of the first communication, a second session key is received, transmitted, or derived by using the first communication, the second session key is used for encryption or message authentication of the second communication, a third session key is received, transmitted, or derived by using the first communication, and the third session key is used instead of the second session key.

Abstract: A memory circuit includes a first memory cell array configured to store data, and a second memory cell array. The second memory cell array is configured as a first logic circuit or a second logic circuit in response to a first set of control signals. The first logic circuit is configured to perform a first logic function on a first set of data signals based on a second set of control signals. The second logic circuit is configured to perform a second logic function on the first set of data signals based on the second set of control signals. The second logic function is different from the first logic function. The first set of data signals is part of the data stored in the first memory cell array. The first memory cell array and the second memory cell array are embedded in a same memory cell array.

Abstract: A computer-implemented method and system for managing access control policies for diverse database tables. The method involves consolidating access control by associating each table with a common set of access control policies, enforcing these policies to control access, and providing automated management without administrator input. The automated management includes auditing the policies, detecting discrepancies, and remedying them by modifying the policies. The system comprises at least one physical processor and memory containing instructions that, when executed, perform the method described.

Abstract: A memory device and a programming method thereof are provided. The memory device has multiple word lines and a dummy word line set. A word line is selected from the word lines and is applied with a program voltage, and unselected word lines and the dummy word line set are applied with a pass voltage. After programming the selected word line, a program verification is performed on the selected word line. When the selected word line passes the program verification, a high bound and/or low bound check for the threshold voltage distribution of at least one of the dummy word lines is performed. When at least one of the dummy word lines fails in the high bound and/or low bound check, the status of the selected word line is shown as fail or a flag is set thereto.

Abstract: This application relates to a processing method for configuring a check pin of a memory performed by a computer device. The method includes: receiving a first data signal and a sampling pulse signal returned by a check pin in a target memory; time-shifting each first data signal through a delay circuit to align a target level value in each first data signal after the time shift with the sampling pulse signal to obtain a first delay parameter; and when receiving a second data signal returned by the check pin in the target memory, time-shifting a target data signal in each second data signal through the delay circuit to align target level values in all second data signals after the time shift to obtain a second delay parameter, determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

Abstract: An apparatus, system, and methods to use a low-observable encryption device that includes an encryption unit; a communication unit; and a computing unit, wherein a microprocessor comprises two encryption units. The low-observable encryption device may also include an interchangable device. In some embodiments, the interchangable device comprises a computing unit, a software defined radio, an electrical to optical converter, or a combination thereof. In some embodiments, power is delivered by a USB port. In some embodiments, an input interconnect comprises an Ethernet interface, a USB interface, a Wi-Fi interface, a radio interface, a SATCOM interface, or a Bluetooth interface. In some embodiments, an output interconnect comprises an Ethernet interface, a USB interface, a Wi-Fi interface, a radio interface, a SATCOM interface, or a Bluetooth interface.

Abstract: One or more unused locations in a software image are identified. An example of a software image may be a container image or virtual machine image. An unused location may be a location where padding is used in the software image. A first watermark is placed in the one or more unused locations to produce a watermarked software image. A request is received to load the watermarked software image. In response to receiving the request to load the watermarked software image, a second watermark is generated using the one or more unused locations in the watermarked software image and the second watermark is then compared to the first watermark. In response to the first watermark matching the second watermark, the software image is loaded. In response to the first watermark not matching the second watermark, the software image is not loaded.

Abstract: A multi-bit MRAM cell includes at least a first MTJ device storing a first logic bit and a second MTJ device storing a second logic bit. The multi-bit MRAM cell is readable through application of a reference current across the multi-bit MRAM cell and comparison of a resultant output voltage with a plurality of reference voltages.

Abstract: The present disclosure describes techniques for processing query predicates involving fine-grained privacy-preserving columns. A query predicate is received. It is determined whether there is a first match between identification information and operator information in a first row of a predicate catalog table and information associated with the query predicate. It is determined whether a value of a quantity limit in the first row is greater than zero in response to determining that there is the first match between the identification information and the operator information in the first row and the information associated with the query predicate. The query predicate is executed in response to determining that the value of the quantity limit in the first row is greater than zero. The value of the quantity limit in the first row is automatically reduced by one and the predicate catalog table is automatically updated.

Abstract: A memory device includes memory cells, first wirings extending along a first direction and connected to the cells, second wirings extending along a second direction and connected to the cells, the second direction intersecting the first direction, third wirings extending along a third direction and each connected to one or more second wirings, the third direction intersecting the first and second directions, sense circuits each connected to one or more third wirings, a switching circuit connected to the circuits and selectively outputting signals from the sense circuits, and a control circuit storing first addresses indicating second and third wirings connected to defective cells, and when a memory cell is selected, determining second addresses indicating second and third wirings connected to the selected cell, and based on the first and second addresses, controlling the switching circuit not to output signals from one or more sense circuits connected to the defective cells.

Abstract: Control logic in a memory device selects two or more blocks of a plurality of blocks to concurrently scan during a scan operation. The control logic can further cause a first voltage to be applied to a dummy word line of each block of the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of a set of sense amplifiers coupled with the plurality of blocks. The control logic can cause a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifier.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed according to a one bit per memory cell (SLC) programming scheme that includes an erased data state and a programmed data state. The memory cells in both the erased data state and in the programmed data state have threshold voltages Vt that are less than 0 V.

Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

Abstract: A memory device comprises an input interface configured to receive an erase request indicating a memory portion to be erased and control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.

Abstract: Methods, systems, and apparatus for management of program operations in a memory system are described. An example system includes a memory device and a memory controller. The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array. The peripheral circuit obtains a first temperature, and in response to determining that the first temperature is at or above a predetermined threshold, apply a first program voltage pulse with a first pulse width to a specified word line coupling memory cells of the memory cell array. The peripheral circuit obtains obtain a second temperature, and in response to determining that the second temperature is below the predetermined threshold, apply a second program voltage pulse with a second pulse width to the specified word line, where the second pulse width is larger than the first pulse width.

Abstract: A method, device, and medium for permission management is disclosed. The method includes obtaining, based on it being detected that an application is being installed, one or more permissions that the application needs to apply for during running, setting, based on the one or more permissions comprising a special permission and based on an installation package of the application not comprising a special permission certificate, the special permission to an unavailable state, and continuing to install the application, where the special permission certificate records a special permission that the application is allowed to apply for during running.

Abstract: Methods, systems, and devices for inductive energy harvesting and signal development for a memory device are described. One or more inductors may be included in or coupled with a memory device and used to provide current for various operations of the memory device based on energy harvested by the inductors. An inductor may harvest energy based on current being routed through the inductor or based on being inductively coupled with a second inductor through which current is routed. After harvesting energy, an inductor may provide current, and the current provided by the inductor may be used to drive access lines or otherwise as part of executing one or more operations at the memory device. Such techniques may improve energy efficiency or improve the drive strength of signals for the memory device, among other benefits.

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a target level based on a compensation value of a program command. The controller is further configured to sense a threshold voltage of the selected memory cell. The controller is further configured to in response to the compensation value having a first value and the threshold voltage being greater than a first program verify level, inhibit programming of the selected memory cell. The controller is further configured to in response to the compensation value having a second value different from the first value and the threshold voltage being greater than a second program verify level less than the first program verify level, inhibit programming of the selected memory cell.

Abstract: The present technology relates to a semiconductor device. According to the present technology, a memory device having a reduced size may include a plurality of memory cells connected to a selected word line, a plurality of page buffers configured to store at least one second logical page data except for first logical page data in a plurality of first program loops performed on the plurality of memory cells, and store the first logical page data after the plurality of first program loops are performed, and a control logic configured to control the plurality of first program loops based on the at least one second logical page data, determine first memory cells programmed to one program state based on the first logical page data, and control a plurality of second program loops performed on second memory cells.

Abstract: The disclosed system and method are directed to a novel implementation of encryption service provision which obviates a need for network communication between a card manufacturing/personalization entity and a validation entity during the card personalization phase. The proposed solution decouples the operation flow associated with personalization of an OTP card (as carried out by a manufacturing HSM) and the validation of an OTP card cryptogram (as carried out by a distinct validation HSM). This is accomplished by the generation and distribution of a third master key which enables the personalization and the validation HSMs to independently derive the shared secret value used in generation and validation of a transaction cryptogram associated with an OTP card operation.