Patents Examined by Han Yang
  • Patent number: 10290344
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array an array of memory cells via a sense line. The sensing circuitry is configured to sense, as a voltage associated with a second operand of a logical function, a voltage on the sense line corresponding to a first logical data value resulting in part from reading a first memory cell of the array of memory cells associated with a first operand of the logical function.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10290339
    Abstract: An operating method of a magnetic memory device may include: a first step of retrieving write data to be written to a plurality of magnetic memory cells sharing a bit line according to a write request, the write data including more of a first type of data than a second type of data; a second step of writing the first type of data simultaneously to all cells of the plurality of magnetic memory cells; and a third step of writing the second type of data to a portion of the plurality of magnetic memory cells, the second type of data being different from the first type of data.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: May 14, 2019
    Assignees: SK HYNIX INC., INDUSTRY-ACADEMIC COOPERATION FOUNDATION YONSEI UNIVERSITY
    Inventors: Kangwook Jo, Jongil Hong, Hongil Yoon
  • Patent number: 10290355
    Abstract: In a method of programming a semiconductor memory device, during a standby period, a standby voltage is applied to word lines coupled to a plurality of memory cells included in a selected memory cell string, and, during a first program period, a first pre-bias voltage is applied to a word line coupled to at least one of programmed memory cells of the selected memory cell string. The first pre-bias voltage is greater than the standby voltage.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventors: Eun Mee Kwon, Ji Seon Kim, Sang Tae Ahn
  • Patent number: 10284543
    Abstract: Disclosed are systems and methods for secure online authentication. An exemplary method comprises: determining, via a processor of a computing device, a connection being established between a browser application installed on a computer system and a protected website; obtaining information relating to the protected website in response to obtaining a request for authentication from the protected website; establishing a protected data transmission channel with the protected website to receive at least one certificate of the protected website; performing authentication and transmitting authentication data to the protected website; and in response to an indication of a successful authentication from the protected website, transmitting identification information to the browser application for enabling access to the protected website.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 7, 2019
    Assignee: AO KASPERSKY LAB
    Inventors: Dmitry L. Petrovichev, Artem O. Baranov, Evgeny V. Goncharov
  • Patent number: 10242729
    Abstract: Disclosed herein is a device includes a command generation circuit: that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first, and second command signals is activated, and an output gate circuit that receives a first signal output from the internal circuit, the output gate circuit being configured to pass the first signal when the second command signal is deactivated and to block the first signal when the second command signal is activated.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: March 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Keisuke Fujishiro
  • Patent number: 10203885
    Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 12, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 10181356
    Abstract: A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 15, 2019
    Assignee: PROTON WORLD INTERNATIONAL N.V.
    Inventors: Ronny Van Keer, Youssef Ahssini
  • Patent number: 10147465
    Abstract: Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. The power up circuitry may be configured to provide the internal power supply limited to a peak current, or may be configured to provide the internal power supply not limited to a peak current. The memory device may be, for example, a synchronous dynamic random access memory (SDRAM) device or Flash memory.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Ted Pekny, Jeff Yu
  • Patent number: 10141047
    Abstract: A static random access memory (SRAM) comprises a plurality of memory cells each having a pair of cross-coupled inverters, a first of the inverters being supplied by first and second power supply rails and a second of the inverters being supplied by third and fourth supply rails, an input of the second inverter being coupled to a first bit line via a first transistor; and a power supply circuit adapted to apply a first voltage difference across the first and second power supply rails and a second voltage difference across the third and fourth power supply rails, the second voltage difference being greater than the first voltage difference.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: November 27, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES
    Inventors: Kiyoo Itoh, Amara Amara, Khaja Ahmad Shaik
  • Patent number: 10121536
    Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: November 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Weihan Wang, Toshifumi Hashimoto, Noboru Shibata
  • Patent number: 10114555
    Abstract: A semiconductor device includes a memory cell array including a first memory region and a second memory region; a plurality of register sets for storing a plurality of parameter sets; and a control logic circuit configured to, activate a first register set among the plurality of register sets in response to a selection signal, and perform an access operation on the first memory region using a parameter set stored in an activated register set from among the plurality of register sets.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: October 30, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sil Wan Chang, Byung Gook Kim, Jae Young Kwon, Jong Youl Lee
  • Patent number: 10101933
    Abstract: According to one embodiment, a controller determines a write operation, when a write request to a memory, a write address and data are received, by comparing an amount of use of a write buffer and a threshold for determining a change of a write operation to the memory. The memory is capable of overwriting first data to second data at an identical physical address of the memory. By the determined write operation, the received data is written to the received write address of the memory.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 16, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuyuki Eguchi
  • Patent number: 10096362
    Abstract: A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: October 9, 2018
    Assignee: CROSSBAR, INC.
    Inventors: Hagop Nazarian, Sung Hyun Jo
  • Patent number: 10090037
    Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 2, 2018
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10083735
    Abstract: Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the processor die, a first thermal sensor of the processor die disposed adjacent to a first hot spot from a first type of workload and a second thermal sensor of the processor die disposed adjacent to a second hot spot from a second type of workload, and a hardware control circuit of the processor die to cause a refresh of a capacitor of the dynamic memory die when either of an output of the first thermal sensor exceeds a first threshold value and an output of the second thermal sensor exceeds a second threshold value.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 25, 2018
    Assignee: INTEL CORPORATION
    Inventors: Xiuting C. Man, Stanley S. Kulick
  • Patent number: 10078711
    Abstract: A method and system are provided for data driven shrinkage compensation. The method includes subdividing, by a polygon subdivider, polygons in a three-dimensional file into facets. The method further includes calculating, by an axis dimension calculator, dimensions of an object from an x-directional strand disposed between two facets of a first predetermined facet pair, a y-directional strand disposed between two facets of second predetermined facet pair, and a z-directional strand disposed between two facets of a third predetermined facet pair. The object is formed from at least some of the polygons. The method also includes predicting, by a dimension change predictor, dimensional changes in the strands based on a shape shrinkage model. The method additionally includes correcting, by a dimension change compensator, x-coordinate data, y-coordinate data, and z-coordinate data of at least one facet of the predetermined facet pairs to compensate for the dimensional changes in the strands.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventor: Masaharu Sakamoto
  • Patent number: 10078496
    Abstract: An apparatus is presented for generating a true random number generator (TRNG). The apparatus includes a magnetic tunnel junction (MTJ) device including a first layer, a second layer, and third layer, as well as a bias circuit to bias the MTJ device along with a pulse height discriminator and a time-to-amplitude convertor to generate random bit-streams. The second layer is a barrier layer with an energy barrier height in the order of 20 kT, where k is the Boltzmann constant and T is the absolute temperature. Random flipping of an orientation of magnetization of the third layer is induced by thermal fluctuations in the MTJ device.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Suyog Gupta, Chandrasekharan Kothandaraman, Jonathan Z. Sun
  • Patent number: 10074662
    Abstract: A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney, Marco Domenico Tiburzi
  • Patent number: 10067701
    Abstract: An authentication circuit coupled to a plurality of memory bits includes a monitoring engine configured to provide a first data pattern to all the bits thereby causing each bit to be in a first data state, detect whether a transition from the first data state to a second data state occurs for each bit in response to a first reducing voltage applied to the plurality of bits, provide a second data pattern to all the bits thereby causing each bit to be in the second data state, and detect whether a transition from the second data state to the first data state occurs for each bit in response to a second reducing voltage applied to the plurality of bits, wherein the first data state is different from the second data state, and a PUF controller configured to generate a PUF signature based on the transitions of each bit.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10056783
    Abstract: An energy harvesting circuit for use with a logic circuit includes an induction coil positioned near conductive elements of the logic circuit and configured to extract energy from the magnetic fields produced by transient currents associated with state changes within the logic circuit.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 21, 2018
    Assignee: Johnson Research & Development Co., Inc.
    Inventor: Lonnie G. Johnson