Abstract: A variety of applications can include apparatus having a memory device comprising plate select lines coupled to capacitors of memory cells of the memory device, plate line drivers coupled to the plate select lines, and a bias device coupled to each plate line driver. Use of a single bias device can allow for generation of robust current across multiple plate line drivers. The plate line drivers can be arranged with different formats that can operate with a single bias device. Plate select lines and the plate line driver can be structured in a scheme to balance the number of plate select lines and device counts for the plate line drivers.

Abstract: This disclosure describes techniques and mechanisms for providing an automatic and lightweight solution to detect and resolve session stuck failure(s) due to erroneous anti-replay packet drops in SDWAN networks. The techniques may operate in a data plane of the network devices, such as part of an anti-replay feature. The techniques may enable a sending and receiving edge device to communicate via secure tunnels. The receiving edge device may detect an out-of-window error and may generate and send, within the data plane, a message that includes a set control bit to trigger the sending edge device to perform a synchronization and recovery process.

Abstract: The present disclosure provides a three-dimensional memory array and a preparation method thereof, wherein the three-dimensional memory array includes memory cells arranged in an array; wherein in each memory cell: one end of the memory cell is connected to a word line WL, and the other end thereof is connected to a bit line BL; a corresponding gating transistor is arranged at the bottom of each word line WL, and the bottom of the word line WL is connected to the drain of the gating transistor; the gate of the gating transistor is connected to a gate line GL, and the source of the gating transistor is connected to a source line SL; the bit line BL, the word line WL, the source line SL and the gate line GL control the state of the memory cell.

Abstract: A controller iteratively activates a control signal for one-half a clock cycle while sweeping its phase relationship to the rising edge of the clock. Phase relationships that result in the rising edge of the clock occurring while the control signal is active result in the memory device outputting command/address data on the data bus. Phase relationships that do not result in the rising edge of the clock occurring while the control signal is active do not result in the memory device outputting the command/address data on the data bus. By changing the data on the CA bus between activations of the control signal, the controller can ascertain what phase relationships result in the control signal being successfully sampled. From this information, the controller can select a reliable setting for the phase relationship between the control signal and the clock signal.

Abstract: Systems and methods for secure digital communication with reduced resource utilization are provided. Systems and methods may include utilizing an intermediate node. Systems and methods may include establishing secure communication links between one or more client nodes and the intermediate node and between the intermediate node and one or more server nodes.

Abstract: A method for operating a memory device includes following steps. A memory device including a plurality of first electrodes, a plurality of second electrodes and a plurality of memory layers is provided, and a plurality of memory cells are formed at intersections between the first electrodes, the second electrodes and the memory layers. A selected memory cell is selected in the memory cells. ?? V is applied to a selected second electrode in the second electrodes, and the selected second electrode is in electrical contact with the selected memory cell. ? V is applied to a selected first electrode in the first electrodes, and the selected first electrode is in electrical contact with the selected memory cell. 0 V is applied to unselected second electrodes in the second electrodes. 0 V is applied to unselected first electrodes in the first electrodes.

Abstract: The present disclosure related to a client device including a communication interface configured to communicate with an agency server and a counterpart device, a memory, and a processor. The processor may transmit a topic creation request to the agency server, when a topic creation notification is received from the agency server, generate a first subscription DID corresponding to the topic, a pair of first subscription private key and first subscription public key corresponding to the first subscription DID, transmit the first subscription DID to the counterpart device, receive a second subscription DID generated by the counterpart device from the agency server, generate a first encryption key based on the first subscription private key and the second subscription DID, and transmit message data encrypted with the first encryption key to the agency server.

Abstract: This disclosure describes techniques for allowing an organization to manage user identities. In some examples, the management of user identities may be serverless. In some examples, serverless identity management may be enabled through a distributed application on user devices of the organization. The application may generate and/or store information related to the user identities on the user devices. Serverless identity management may further include storing at least some of the information at a location that is easily accessible to the user devices, such as a cloud computing location, while maintaining security for private data. Serverless identity management may therefore provide an organization with greater operational flexibility.

Abstract: An example is a method. A query challenging authenticity is received at an intellectual property (IP) block in an integrated circuit (IC) die. The query may be a query of a query-response pair. A response to the query is generated, at the IP block, using a logic built-in self-test (LBIST) circuit. The response is transmitted from the IP block. The response may be received and compared to an expected response of the query-response pair. Authenticity may be validated when the response matches the expected response.

Abstract: Disclosed herein are system, method, and computer program product embodiments for an Artificial Intelligence (AI)-enabled threat detection system. The embodiments describe evaluating an alert from an alert stream using a threat analysis system. The threat analysis system may include a proxy server for receiving and formatting system event data, a threat analysis pipeline for determining and normalizing risk scores for a set of endpoint data and behavioral metrics respectively, and an action engine for executing an action towards the alert. The action engine may disable the alert, whitelist the alert, and/or transmit a threat notification to an administrator server based on traffic light thresholding.

Abstract: An example system can include a memory device and a processing device. The memory device can include a group of memory cells. The processing device can be coupled to the memory device. The processing device can be configured to determine a distance of a memory die from a center of a memory component. The processing device can be configured to perform a read disturb operation on the memory die based on the determined distance use a first voltage window for a set of memory cells of the group of memory cells during a first time period.

Abstract: A memory device includes a reference voltage generator configured to generate a reference voltage, and a data input/output (I/O) buffer configured to receive a data signal having a first phase, generate a phase control signal having a second phase opposite to the first phase, and generate an output signal based on the data signal, the phase control signal, and the reference voltage.

Abstract: The present invention relates to a method for a primary station distributing an encryption key to a plurality of secondary stations.

Abstract: An electronic device includes a storage device, including a secure area assigned to a trusted application and a normal area, and a processor configured to generate a user identifier, assigned to the trusted application, based on the trusted application and device information and to manage data requested for the secure area from the trusted application based on the user identifier. The device information includes at least one of information associated with the storage device and information associated with the processor.

Abstract: A recursive Analog Content Addressable Memory (ACAM) device includes a first comparison stage and a second comparison stage. The first comparison stage includes a first match line, a first base segment comparator connected between the first match line and a reference node, a first incremented segment comparator, and a first pass transistor. The first pass transistor and the first incremented segment comparator are connected in series between the first match line and the reference node. The second comparison stage includes a first inverter connected to the first pass transistor, a second match line connected to the first inverter, and a second base segment comparator connected between the second match line and the reference node. The device enables efficient comparison of multi-bit values.

Abstract: A non-volatile memory device, a storage device including the non-volatile memory device, and an operating method of the storage device are provided. The non-volatile memory device comprises a data pin configured to output a data signal, and a command address pin being separate from the data pi the command address pin configured to receive a read command corresponding to the data signal and output a noise state data during a data output operation in which the data signal is output through the data pin in response to the read command.

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

Abstract: A semiconductor memory device includes: a first via-wiring extending in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the first via-wiring; memory portions arranged in the first direction and electrically connected to the first semiconductor layers; first gate electrodes arranged in the first direction and opposed to the plurality of first semiconductor layers; first wirings arranged in the first direction and electrically connected to the plurality of first gate electrodes; second semiconductor layers arranged in the first direction and electrically connected to the first wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; a second via-wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; and second wirings arranged in the first direction and electrically connected to the second semiconductor layers.

Abstract: At least one portion of a memory array may be arranged to provide high density non-volatile random access memory (HIGH DENSITY NON-VOLATILE RAM) while at least one other portion of the memory array may be arranged to provide dynamic random access memory (DRAM)-like memory. In some examples, the memory array may be arranged by programming one or more configuration devices. In some examples, the configuration device may include one or more switches to couple one or more memory cells to a sense amplifier. In some examples, the configuration device may include fuses and/or antifuses to couple one or more memory cells to a sense amplifier. In some examples, the portions of the memory array may be reconfigurable from one arrangement to another arrangement.

Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.