Patents Examined by Han Yang
  • Patent number: 10101933
    Abstract: According to one embodiment, a controller determines a write operation, when a write request to a memory, a write address and data are received, by comparing an amount of use of a write buffer and a threshold for determining a change of a write operation to the memory. The memory is capable of overwriting first data to second data at an identical physical address of the memory. By the determined write operation, the received data is written to the received write address of the memory.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 16, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuyuki Eguchi
  • Patent number: 10096362
    Abstract: A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: October 9, 2018
    Assignee: CROSSBAR, INC.
    Inventors: Hagop Nazarian, Sung Hyun Jo
  • Patent number: 10090037
    Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 2, 2018
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10083735
    Abstract: Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the processor die, a first thermal sensor of the processor die disposed adjacent to a first hot spot from a first type of workload and a second thermal sensor of the processor die disposed adjacent to a second hot spot from a second type of workload, and a hardware control circuit of the processor die to cause a refresh of a capacitor of the dynamic memory die when either of an output of the first thermal sensor exceeds a first threshold value and an output of the second thermal sensor exceeds a second threshold value.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 25, 2018
    Assignee: INTEL CORPORATION
    Inventors: Xiuting C. Man, Stanley S. Kulick
  • Patent number: 10078711
    Abstract: A method and system are provided for data driven shrinkage compensation. The method includes subdividing, by a polygon subdivider, polygons in a three-dimensional file into facets. The method further includes calculating, by an axis dimension calculator, dimensions of an object from an x-directional strand disposed between two facets of a first predetermined facet pair, a y-directional strand disposed between two facets of second predetermined facet pair, and a z-directional strand disposed between two facets of a third predetermined facet pair. The object is formed from at least some of the polygons. The method also includes predicting, by a dimension change predictor, dimensional changes in the strands based on a shape shrinkage model. The method additionally includes correcting, by a dimension change compensator, x-coordinate data, y-coordinate data, and z-coordinate data of at least one facet of the predetermined facet pairs to compensate for the dimensional changes in the strands.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventor: Masaharu Sakamoto
  • Patent number: 10078496
    Abstract: An apparatus is presented for generating a true random number generator (TRNG). The apparatus includes a magnetic tunnel junction (MTJ) device including a first layer, a second layer, and third layer, as well as a bias circuit to bias the MTJ device along with a pulse height discriminator and a time-to-amplitude convertor to generate random bit-streams. The second layer is a barrier layer with an energy barrier height in the order of 20 kT, where k is the Boltzmann constant and T is the absolute temperature. Random flipping of an orientation of magnetization of the third layer is induced by thermal fluctuations in the MTJ device.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Suyog Gupta, Chandrasekharan Kothandaraman, Jonathan Z. Sun
  • Patent number: 10074662
    Abstract: A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney, Marco Domenico Tiburzi
  • Patent number: 10067701
    Abstract: An authentication circuit coupled to a plurality of memory bits includes a monitoring engine configured to provide a first data pattern to all the bits thereby causing each bit to be in a first data state, detect whether a transition from the first data state to a second data state occurs for each bit in response to a first reducing voltage applied to the plurality of bits, provide a second data pattern to all the bits thereby causing each bit to be in the second data state, and detect whether a transition from the second data state to the first data state occurs for each bit in response to a second reducing voltage applied to the plurality of bits, wherein the first data state is different from the second data state, and a PUF controller configured to generate a PUF signature based on the transitions of each bit.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10056783
    Abstract: An energy harvesting circuit for use with a logic circuit includes an induction coil positioned near conductive elements of the logic circuit and configured to extract energy from the magnetic fields produced by transient currents associated with state changes within the logic circuit.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 21, 2018
    Assignee: Johnson Research & Development Co., Inc.
    Inventor: Lonnie G. Johnson
  • Patent number: 10048863
    Abstract: Systems and methods are disclosed for open block refresh management. In certain embodiments, an apparatus may comprise a circuit configured to monitor an amount of time a block of a solid-state memory remains in an open state where the block has not been fully filled with data, and in response to reaching an open block time limit, compare an amount of the block already written with data against a threshold amount. When less than a threshold amount of the block has been written with data, the circuit may refresh data from a last N pages from the block by writing the data to a new location, N being a number of pages less than all pages in the block. When more than the threshold amount of the block has been written with data, the circuit may fill a remaining unwritten amount of the block with dummy data.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 14, 2018
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Antoine Khoueir, Ara Patapoutian
  • Patent number: 10037796
    Abstract: A write-assist cell includes a first pull-up transistor electrically coupled to a voltage array and a first node, a first pass-gate transistor electrically coupled to the first node, and a bit-line electrically coupled to the first pass-gate transistor and a pull-down voltage. The first pass-gate is configured to selectively couple the bit-line to the first node. The pull-down voltage is configured to adjust a voltage of the voltage array from a first voltage to a second voltage when the bit-line is coupled to the first node.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sahil Preet Singh, Yen-Huei Chen
  • Patent number: 10038099
    Abstract: A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 31, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshihiko Saito
  • Patent number: 10032495
    Abstract: A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: July 24, 2018
    Assignee: SK Hynix Inc.
    Inventor: Hee Sang Kim
  • Patent number: 10026477
    Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: July 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jianhua Yang, Ning Ge, John Paul Strachan, Gary Gibson, Warren Jackson
  • Patent number: 10020043
    Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: July 10, 2018
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10008269
    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 26, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 10007311
    Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: June 26, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Deepak Raghu, Pao-Ling Koh, Philip Reusswig, Chris Nga Yee Yip, Jun Wan, Yan Li
  • Patent number: 10001937
    Abstract: A memory device may include: a memory cell array comprising a plurality of search regions, each of the search regions comprising a plurality of group regions, each of the group regions comprising a flag cell, each flag cell comprising information indicating whether the corresponding group region is programmed; a voltage generator suitable for generating a read bias voltage for the memory cell array according to a voltage control signal; and a memory controller suitable for selecting a search region and controlling the voltage generator to adjust the read bias voltage based on information of flag cell of the selected search region when a read command is received, and controlling a read operation for the selected search region based on the adjusted read bias voltage.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 19, 2018
    Assignee: SK Hynix Inc.
    Inventors: Won-Jin Jung, Ga-Ram Han, Keun-Woo Lee
  • Patent number: 9990153
    Abstract: A memory system includes a memory device performing write operations on lines included in a memory block among a plurality of memory blocks included in the memory device; a counting unit counting a write count for each of the plurality of memory blocks, and outputting the write counts; a first wear-leveling unit performing a wear leveling operation by shifting the lines of each of the plurality of memory blocks; and a second wear-leveling unit detecting hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swapping the hot memory block with the cold memory block, wherein the second wear-leveling unit selects at least one memory block among the plurality of memory blocks based on the write counts, and checks whether the write operation is performed on each of the lines included in the selected memory block.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 5, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jung-Hyun Kwon, Dong-Gun Kim, Sang-Gu Jo
  • Patent number: 9966144
    Abstract: In a method of programming a semiconductor memory device, during a standby period, a standby voltage is applied to word lines coupled to a plurality of memory cells included in a selected memory cell string, and, during a first program period, a first pre-bias voltage is applied to a word line coupled to at least one of programmed memory cells of the selected memory cell string. The first pre-bias voltage is greater than the standby voltage.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 8, 2018
    Assignee: SK hynix Inc.
    Inventors: Eun Mee Kwon, Ji Seon Kim, Sang Tae Ahn