Abstract: A memory device includes a reference voltage generator configured to generate a reference voltage, and a data input/output (I/O) buffer configured to receive a data signal having a first phase, generate a phase control signal having a second phase opposite to the first phase, and generate an output signal based on the data signal, the phase control signal, and the reference voltage.

Abstract: The present invention relates to a method for a primary station distributing an encryption key to a plurality of secondary stations.

Abstract: An electronic device includes a storage device, including a secure area assigned to a trusted application and a normal area, and a processor configured to generate a user identifier, assigned to the trusted application, based on the trusted application and device information and to manage data requested for the secure area from the trusted application based on the user identifier. The device information includes at least one of information associated with the storage device and information associated with the processor.

Abstract: A recursive Analog Content Addressable Memory (ACAM) device includes a first comparison stage and a second comparison stage. The first comparison stage includes a first match line, a first base segment comparator connected between the first match line and a reference node, a first incremented segment comparator, and a first pass transistor. The first pass transistor and the first incremented segment comparator are connected in series between the first match line and the reference node. The second comparison stage includes a first inverter connected to the first pass transistor, a second match line connected to the first inverter, and a second base segment comparator connected between the second match line and the reference node. The device enables efficient comparison of multi-bit values.

Abstract: A non-volatile memory device, a storage device including the non-volatile memory device, and an operating method of the storage device are provided. The non-volatile memory device comprises a data pin configured to output a data signal, and a command address pin being separate from the data pi the command address pin configured to receive a read command corresponding to the data signal and output a noise state data during a data output operation in which the data signal is output through the data pin in response to the read command.

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

Abstract: A semiconductor memory device includes: a first via-wiring extending in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the first via-wiring; memory portions arranged in the first direction and electrically connected to the first semiconductor layers; first gate electrodes arranged in the first direction and opposed to the plurality of first semiconductor layers; first wirings arranged in the first direction and electrically connected to the plurality of first gate electrodes; second semiconductor layers arranged in the first direction and electrically connected to the first wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; a second via-wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; and second wirings arranged in the first direction and electrically connected to the second semiconductor layers.

Abstract: At least one portion of a memory array may be arranged to provide high density non-volatile random access memory (HIGH DENSITY NON-VOLATILE RAM) while at least one other portion of the memory array may be arranged to provide dynamic random access memory (DRAM)-like memory. In some examples, the memory array may be arranged by programming one or more configuration devices. In some examples, the configuration device may include one or more switches to couple one or more memory cells to a sense amplifier. In some examples, the configuration device may include fuses and/or antifuses to couple one or more memory cells to a sense amplifier. In some examples, the portions of the memory array may be reconfigurable from one arrangement to another arrangement.

Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.

Abstract: An embedded next generation access control system imposes fine-grained access control on data in a resource database and includes a resource database, NGAC database, administrator, and mediator. The resource database includes controlled resource data and a mediator. The NGAC database includes an adjudicator and access control policy data. The administrator communicates access control policy input to the NGAC database upon which access control policy data is made in the NGAC database. The controlled resource data is access controlled by access control policy data via calls of an adjudicator API, which implements Next Generation Access Control standard by NIST, by the resource database to obtain access decisions. The adjudicator determines which controlled resource data are accessed by a user and provides an access control list for each user and user attribute. The adjudicator also provides a prohibited access control list for a user and user attributes in the access control policy data if there are any.

Abstract: A memory device may include a memory cell array, and a write driver and sense amplifier connected to the memory cell array through bit lines. The memory cell array includes a first cell area including a plurality of first memory cells arranged on a plane corresponding to a first direction and a second direction, a second cell area including a plurality of second memory cells arranged on the plane disposed on one side of the first cell area in the first direction, a word line extending in the first direction and is connected to the plurality of first memory cells and the plurality of second memory cells, first bit lines extending in the second direction and are respectively connected to the plurality of first memory cells, and second bit lines extending in the second direction and are respectively connected to the plurality of second memory cells.

Abstract: A semiconductor device includes a base chip configured to output a strobe signal and a control signal and to output a first update signal and a second update signal in response to receiving first and second core strobe signals, a first core chip configured to generate the first core strobe signal by delaying the strobe signal by a first delay amount while a pulse of the control signal is input, to output the first core strobe signal to the base chip, and to calibrate the first delay amount while the first update signal is enabled, and a second core chip configured to generate the second core strobe signal by delaying the strobe signal by a second delay amount when a pulse of the control signal is input, to output the second core strobe signal to the base chip, and to calibrate the second delay amount while the second update signal is enabled.

Abstract: For each voltage offset bin of a plurality of voltage offset bins, a corresponding period of scan operations of memory blocks associated with the voltage offset bin is determined. For each voltage offset bin of the plurality of voltage offset bins, a corresponding scheduling time offset of scan operations is determined. For a chosen voltage offset bin, based on a period of scan operations associated with the chosen voltage offset bin and a scheduling time offset associated with the chosen voltage offset bin, a scan operation is scheduled. The scan operation with respect to one or more blocks associated with the chosen voltage offset bin is performed.

Abstract: Technology for re-calibrating a temperature coefficient (Tco) for reading NAND memory cells. The Tco may be re-calibrated based on an amount of data retention impact to NAND memory cells since the NAND memory cells were programmed. The data retention impact may be measured by determining a shift to a candidate Vt distribution. The candidate Vt distribution may be selected as one that exhibits a significant data retention impact. The Tco may include, but is not limited to a bit line voltage Tco or a Vread Tco. The bit line voltage Tco may be used to establish the bit line voltage during read. The Vread Tco may be used to establish a voltage to unselected word lines during read.

Abstract: A memory apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes defining channels. The memory cells form a block including a first sub-block and a second sub-block disposed vertically above the first sub-block. A control means is configured to pre-charge the channels of the memory holes in a pre-charge operation. The control means applies each of a series of programming pulses of a program voltage in a program phase followed by verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines in a verify phase to program and verify the memory cells connected thereto during program loops. The pre-charge operation for the second sub-block occurs during the verify phase of a previously occurring one of the plurality of program loops.

Abstract: Embodiments described herein relate to methods and apparatuses for providing communication between a server and a client device via a proxy node. A method, in a proxy node, wherein the proxy node includes an intermediate node between a server and a client device includes receiving encrypted traffic transmitted between the client device and the server; receiving a key from the client device; performing a service in relation to the encrypted traffic to generate information; encrypting the information using the key to generate encrypted information; and transmitting the encrypted information to the server.

Abstract: A memory system includes: an address scrambler suitable for scrambling an address based on a scrambling rule to generate a scrambled address; a memory core including a plurality of memory cells and suitable for storing data in memory cells designated by the scrambled address; and a scramble control circuit suitable for changing the scrambling rule in response to satisfaction of an attack condition.

Abstract: Described herein is a method and apparatus to reduce electric displacement and polarization target for a memory bit-cell. In at least one embodiment, the apparatus comprises one or more circuitries to adjust voltage on a plate-line to be above or below a nominal voltage of the plate-line based on a write operation or read operation on a bit-cell. In at least one embodiment, the bit-cell comprises a transistor and a capacitor including non-linear polar material, wherein the capacitor has a first terminal coupled to the plate-line and a second terminal coupled to the transistor.

Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

Abstract: An operating method of a storage device includes a storage controller and a non-volatile memory device. The method includes providing, by the storage controller, the non-volatile memory device with a first command indicating a temperature read operation, providing, by a temperature sensor of the non-volatile memory device, a first measurement temperature value to the storage controller based on the first command, determining, by the storage controller, whether the first measurement temperature value is lower than a first threshold value, providing, by the storage controller, the non-volatile memory device with a second command indicating a dummy read operation in response to determining that the first measurement temperature value is smaller than the first threshold value, and performing, by the non-volatile memory device, the dummy read operation for heating based on the second command.