Abstract: Disclosed a device-based cross point array and a method of operation therefor. The method relates to a method for updating a cross point array implemented as a device where a potentiation region and a depression region are separated, and the method is performed by a control logic. The method includes: in a first cycle, controlling lines where positive values are applied among first lines, in ON state, and applying a first voltage pulse at each of second lines intersecting with the first lines based on an applied value; and in a second cycle, controlling lines where negative values are applied among the first lines, in ON state, and applying a second voltage pulse at each of the second lines based on an applied value.

Abstract: An electronic device may include memory cells, access lines coupled to the memory cells, and access line drivers each coupled to an access line to drive that access line. Each access line driver may be configured to receive a biasing voltage and produce an access line voltage on the respective access line. A biasing voltage generator may be configured to generate the biasing voltage to be received by the access line drivers. A biasing voltage controller may be configured to maintain a level of the biasing voltage for a specified slew rate of the access line voltage when the access line voltage is within a first range and to increase the level of the biasing voltage to maintain the specified slew rate of the access line voltage when the access line voltage is within a second range.

Abstract: The present disclosure provides for pre-charging a memory device. The memory device comprises memory cells connected to data word lines and in a plurality of channels. The word lines comprise first data word lines and second data word lines separated by dummy word lines. Examples include performing a program-verify operation to verify programming of one or more memory cells connected to a selected data word line of the first data word lines by applying an overdrive voltage to the second data word lines and the dummy word lines. Examples include, during the program-verify operation, pre-charging a channel of memory cells connected to unselected data word line of the first data word lines by applying a pre-charge voltage to a source line, and ramping down the overdrive voltage applied to the dummy word lines prior to ramping down the overdrive voltage.

Abstract: A memory device includes a memory cell array including memory cells; a row control circuit coupled to the memory cells through word lines and configured to apply, to a selected word line during read operations, respective read voltages having different levels; a page buffer circuit coupled to the memory cells through bit lines and configured to adjust, according to a sensing control signal during each of the read operations, an amount of current flowing through the bit lines to sense the adjusted amount; and a read control circuit configured to adjust, during a second read operation subsequent to a first read operation among the read operations, a voltage level of the sensing control signal when a voltage level of a second read voltage corresponding to the second read operation is different from a level of a first read voltage corresponding to the first read operation.

Abstract: A memory stack for a VCMA-MRAM device includes a magnetic tunnel junction (MTJ) layer structure, an auxiliary magnetic layer structure including a second hard magnetic layer and an auxiliary magnetic layer, and an interposer layer structure interposing a free layer of the MTJ layer structure and the auxiliary magnetic layer of the auxiliary magnetic layer structure. The interposer layer structure includes a second barrier layer configured to induce a VCMA in the auxiliary magnetic layer and a non-magnetic spacer layer interposing the second barrier layer and the free layer. In response to a first bias voltage exceeding a first threshold voltage across the memory stack, the VCMA induced in the auxiliary magnetic layer causes the auxiliary magnetic layer to be destabilized from a pinned magnetization state with a magnetization oriented along the first direction, and brought to a destabilized magnetization state.

Abstract: Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to apply an erase pulse having a target voltage level and having an erase pulse flattop; for each suspend of a plurality of suspends initiated during the application of the erase pulse flattop, increase a value of the target voltage level; and resume applying the erase pulse having the target voltage level until initiation of any subsequent suspend of the plurality of suspends. Such controllers might further be configured to cause the memory to maintain the value of the target voltage level for each suspend of one or more additional suspends initiated during the application of the erase pulse flattop, and resume applying the erase pulse having the target voltage level until initiation of any subsequent suspend of the one or more additional suspends.

Abstract: In some embodiments, the present disclosure relates to a memory device, including a plurality of content addressable memory (CAM) units arranged in rows and columns and configured to store a plurality of data states, respectively. A CAM unit of the plurality of CAM units includes a first ferroelectric memory element, a plurality of word lines extending along the rows and configured to provide a search query to the plurality of CAM units for bitwise comparison between the search query and the data states of the plurality of CAM units, and a plurality of match lines extending along the columns and configured to output a plurality of match signals, respectively from respective columns of CAM units. A match signal of a column is asserted when the data states of the respective CAM units of the column match corresponding bits of the search query.

Abstract: Apparatus and methods for providing a conductive path between bit lines using bit line switches are disclosed. An example apparatus includes a memory mat comprising a first plurality of bit lines and a second plurality of bit lines. A plurality of bit line switches can be activated to provide a conductive path between respective ones of the first plurality of bit lines and a second plurality of bit lines. For example, the bit line switches can be activated during a threshold voltage compensation phase or operation and deactivated during a memory cell activation phase or operation.

Abstract: Exemplary methods, apparatuses, and systems include logic-based defective memory component screening. A defectivity manager reads a defective byte map of memory having separately accessible chunks of memory. Each chunk of memory has a number of bytes addressable in a physical and logical domain. Each chunk of the memory is allocated a number of bytes to repair defective bytes. The defectivity manager maps a number of defective bytes in a chunk of a memory in the physical domain to a number of sub-segments of the memory in the logical domain. The defectivity manager writes, to a portion of the memory, an address of a defective byte in the chunk of the memory for repair in response to determining that an available number of bytes allocated to repair defective bytes satisfies a number of defective bytes in a sub-segment of the number of sub-segments of the memory in the logical domain.

Abstract: A semiconductor memory device of embodiments includes a semiconductor layer, a gate electrode layer, memory cells each including a gate insulating layer containing Si, O, and N, and a control circuit. The control circuit performs a write operation and an erase operation on the memory cells. The control circuit determine whether or not the number of times of execution of the erase operation on the memory cells has reached a predetermined number of times. When the number has reached the predetermined number of times, the control circuit perform first processing and second processing on the memory cells. The first processing applies a voltage with the same polarity as that in the write operation to the gate electrode layer with a pulse width larger than that in the write operation. The second processing applies a voltage with a polarity opposite to that in the write operation to the gate electrode layer.

Abstract: An authentication system or a relay device includes: at least one service application configured to utilize vehicle information; a service manager configured to acquire the vehicle information stored in an electronic control unit; at least one service bus configured to manage transmission and reception of data between the at least one service application and the service manager; and an authorization confirmation unit configured to confirm whether to authorize a vehicle information acquisition request of the confidential information. The authorization confirmation unit is installed in the at least one service bus or in the service manager.

Abstract: Disclosed herein is an apparatus and method for generating a quantum circuit for an ARIA substitution layer. The apparatus may configure a multiplicative inverse operation quantum circuit by arranging a preconfigured multiplicative inverse operation quantum circuit, configure four types of S-box operation quantum circuits including S1 and S2 operation quantum circuits, which perform two substitution operations used in ARIA by arranging a quantum circuit for performing affine transform and a quantum circuit for addition of a constant value in the multiplicative inverse operation quantum circuit, and S1?1 and S2?1 operation quantum circuits, which perform inverse substitution operations, and construct the ARIA algorithm as a quantum circuit by rearranging the four types of S-box operation quantum circuits for two substitution layers.

Abstract: An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. Control circuitry can be configured to: receive a command corresponding to a sensing operation to be performed on a selected access line of a first group of access lines corresponding to a first erase block; and determine an adjusted sense voltage to be applied to the selected access line in association with performing the sensing operation. The adjusted sense voltage is based on: a quantity of the first group of access lines that are programmed; or a quantity of the second group of access lines that are programmed; or both.

Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.

Abstract: A secure, field-based data sharing protocol leveraging the DNS infrastructure with DNSSEC, post-quantum cryptography, and real-time usability flows. The protocol enables domain owners to selectively expose structured confidential data (e.g., IBANs, credit cards, wallets, phone numbers) to authorized entities like banks, PSPs, or telcos using a set of predictable, encrypted DNS TXT records. It introduces a format for revocable, auditable, and verifiable publishing of confidential information, distributed without centralized APIs.

Abstract: A memory is provided in this application, including multiple group regions, a command decoding circuit, and a control circuit. Each group region includes multiple bank groups, and each bank group corresponds to one bank group address. An active instruction is received by the command decoding circuit, and the active instruction is decoded to obtain an active command signal. The bank group address, a row address, and the active command signal are received by the control circuit, and the row address is sent to one of the group regions based on the active command signal and the bank group address.

Abstract: The present application discloses an operation method of a memory, and a memory, a memory system, and an electronic system. The method includes: acquiring a data output command; in response to the data output command, utilizing charge pump cells to boost voltages on all word lines corresponding to each of memory planes to pass voltages, wherein the number of the charge pump cells corresponding to the memory plane of which the data output sequence is the first is greater than or equal to the average number, and the total number of the charge pump cells is less than the total number of charge pump cells that have been configured in the memory; and one of the memory planes that has been pre-charged, reading data of the one of the memory planes, and outputting the data of the one of the memory planes according to the data output sequence.

Abstract: A blockchain-based data processing method including: acquiring a resource consumption task including an initiating object address and a target resource identifier; calling, according to the resource consumption task, a resource consumption function, and determining, based on the resource consumption function, a holding object address holding a target virtual resource in the blockchain, the target virtual resource referring to a virtual resource represented by the target resource identifier; consuming, according to the initiating object address and the holding object address, the target virtual resource to obtain a transaction execution result of the resource consumption task; and broadcasting a resource consumption event corresponding to the transaction execution result to a service device corresponding to the initiating object address, so as to make the service device perform, on a target item, service processing associated with the resource consumption event, the target virtual resource being configured for

Abstract: A variety of applications can include apparatus having a memory device comprising plate select lines coupled to capacitors of memory cells of the memory device, plate line drivers coupled to the plate select lines, and a bias device coupled to each plate line driver. Use of a single bias device can allow for generation of robust current across multiple plate line drivers. The plate line drivers can be arranged with different formats that can operate with a single bias device. Plate select lines and the plate line driver can be structured in a scheme to balance the number of plate select lines and device counts for the plate line drivers.

Abstract: This disclosure describes techniques and mechanisms for providing an automatic and lightweight solution to detect and resolve session stuck failure(s) due to erroneous anti-replay packet drops in SDWAN networks. The techniques may operate in a data plane of the network devices, such as part of an anti-replay feature. The techniques may enable a sending and receiving edge device to communicate via secure tunnels. The receiving edge device may detect an out-of-window error and may generate and send, within the data plane, a message that includes a set control bit to trigger the sending edge device to perform a synchronization and recovery process.