Patents Examined by Han Yang
  • Patent number: 10048863
    Abstract: Systems and methods are disclosed for open block refresh management. In certain embodiments, an apparatus may comprise a circuit configured to monitor an amount of time a block of a solid-state memory remains in an open state where the block has not been fully filled with data, and in response to reaching an open block time limit, compare an amount of the block already written with data against a threshold amount. When less than a threshold amount of the block has been written with data, the circuit may refresh data from a last N pages from the block by writing the data to a new location, N being a number of pages less than all pages in the block. When more than the threshold amount of the block has been written with data, the circuit may fill a remaining unwritten amount of the block with dummy data.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 14, 2018
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Antoine Khoueir, Ara Patapoutian
  • Patent number: 10038099
    Abstract: A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 31, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshihiko Saito
  • Patent number: 10037796
    Abstract: A write-assist cell includes a first pull-up transistor electrically coupled to a voltage array and a first node, a first pass-gate transistor electrically coupled to the first node, and a bit-line electrically coupled to the first pass-gate transistor and a pull-down voltage. The first pass-gate is configured to selectively couple the bit-line to the first node. The pull-down voltage is configured to adjust a voltage of the voltage array from a first voltage to a second voltage when the bit-line is coupled to the first node.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sahil Preet Singh, Yen-Huei Chen
  • Patent number: 10032495
    Abstract: A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: July 24, 2018
    Assignee: SK Hynix Inc.
    Inventor: Hee Sang Kim
  • Patent number: 10026477
    Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: July 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jianhua Yang, Ning Ge, John Paul Strachan, Gary Gibson, Warren Jackson
  • Patent number: 10020043
    Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: July 10, 2018
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10007311
    Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: June 26, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Deepak Raghu, Pao-Ling Koh, Philip Reusswig, Chris Nga Yee Yip, Jun Wan, Yan Li
  • Patent number: 10008269
    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 26, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 10001937
    Abstract: A memory device may include: a memory cell array comprising a plurality of search regions, each of the search regions comprising a plurality of group regions, each of the group regions comprising a flag cell, each flag cell comprising information indicating whether the corresponding group region is programmed; a voltage generator suitable for generating a read bias voltage for the memory cell array according to a voltage control signal; and a memory controller suitable for selecting a search region and controlling the voltage generator to adjust the read bias voltage based on information of flag cell of the selected search region when a read command is received, and controlling a read operation for the selected search region based on the adjusted read bias voltage.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 19, 2018
    Assignee: SK Hynix Inc.
    Inventors: Won-Jin Jung, Ga-Ram Han, Keun-Woo Lee
  • Patent number: 9990153
    Abstract: A memory system includes a memory device performing write operations on lines included in a memory block among a plurality of memory blocks included in the memory device; a counting unit counting a write count for each of the plurality of memory blocks, and outputting the write counts; a first wear-leveling unit performing a wear leveling operation by shifting the lines of each of the plurality of memory blocks; and a second wear-leveling unit detecting hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swapping the hot memory block with the cold memory block, wherein the second wear-leveling unit selects at least one memory block among the plurality of memory blocks based on the write counts, and checks whether the write operation is performed on each of the lines included in the selected memory block.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 5, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jung-Hyun Kwon, Dong-Gun Kim, Sang-Gu Jo
  • Patent number: 9966144
    Abstract: In a method of programming a semiconductor memory device, during a standby period, a standby voltage is applied to word lines coupled to a plurality of memory cells included in a selected memory cell string, and, during a first program period, a first pre-bias voltage is applied to a word line coupled to at least one of programmed memory cells of the selected memory cell string. The first pre-bias voltage is greater than the standby voltage.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 8, 2018
    Assignee: SK hynix Inc.
    Inventors: Eun Mee Kwon, Ji Seon Kim, Sang Tae Ahn
  • Patent number: 9947419
    Abstract: A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal. A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 17, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Rakesh Kumar Sinha, Priyankar Mathuria, Sharad Kumar Gupta
  • Patent number: 9934840
    Abstract: A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: April 3, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert C. Baumann, John A. Rodriguez
  • Patent number: 9928912
    Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: March 27, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Boon Bing Ng, Hang Ru Goy
  • Patent number: 9922729
    Abstract: Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: March 20, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Alan J. Wilson, Jeffrey Wright
  • Patent number: 9921761
    Abstract: The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises allocating at least one block of memory selected from a subset of blocks to be written in accordance with an equalizing technique to equalize a variation between blocks of memory based on at least one factor. The method further comprises resupplying the subset of blocks.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: March 20, 2018
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • Patent number: 9911495
    Abstract: A technique including using an array of memory cells for data storage. A given cell of the memory cells includes a capacitive storage element and a resistive storage element that is coupled in series with the capacitive storage element. The technique includes accessing the given memory cell to write a value to the given memory cell or read a value stored in the memory cell. The accessing includes applying a time varying voltage to the memory cell.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: March 6, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Brent E. Buchanan
  • Patent number: 9899090
    Abstract: During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is controlled by the level of the control voltage applied to the control gate and the item of data is de facto written with the numerical value during the putting into conduction of the cell. The programming is then stopped.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 20, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Fran├žois Tailliet
  • Patent number: 9899103
    Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra
  • Patent number: 9892781
    Abstract: A dual port static random access memory cell includes a write port portion and a read port portion. The write port further includes a WPU1 and a WPU2; a WPD1 and a WPD2; and a WPG1 and a WPG2. The WPU1, WPU2, WPD1 and WPD2 are configured to form two cross-coupled inverters for data storage, wherein the WPG1 and WPG2 are connected to the two cross-coupled inverters for writing. The read port portion further includes a read pull down device (RPD) and a read pass gate device (RPG) connected to the two cross-coupled inverters for reading. Each of the WPU1 and WPU2 includes a single FinFET. Each of the WPD1, WPD2, WPG1, WPG2, RPD and RPG includes multiple FinFETs. The WPD1, WPD2, WPG1 and WPG2 include a same number of FinFETs. The RPD includes a number of FinFETs greater than a number of FinFETs in the RPG.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw