Abstract: A data storage system and method for securely storing data includes (a) a host CPU; (b) a non-volatile storage (NVS) memory for storing data; (c) a processor, the processor being coupled to the host CPU and the NVS memory and monitoring availability of space in the NVS memory and in a non-volatile buffer (NV-Buffer); and (d) the NV-Buffer, the NV-Buffer being coupled to the host CPU, the NVS memory, and the processor, upon receiving a request to write data into the NVS memory, the host CPU storing data to be transferred to the NVS memory into the NV-Buffer, and upon receiving a confirmation message that data of a write operation to the NV-Buffer is committed, the NV-Buffer transferring the data to the NVS memory. The NVS memory includes a fast dump space for storing data transferred from the NV-Buffer when a main power is down and for restoring back data from the NVS memory to the NV-Buffer when the power is up.

Abstract: A power management system pad clock and self-test circuit includes a clock processing circuit having a input configured to receive an oscillator clock signal having a first frequency. The clock processing circuit is configured to generate a first pad clock signal having a frequency approximately equal to one-half the first frequency and a second pad clock signal having a frequency that is equal to a programmable fraction of the first frequency. The circuit also includes a main pad clock output node. Multiplexer circuitry is coupled to the clock processing circuitry and the main pad clock output node and configured to receive a plurality of peripheral signals. The multiplexer circuitry is configured to operate in a standard mode of operation wherein one of the first pad clock signal and the second pad clock signal is routed to the main pad clock output node and a first test mode of operation wherein one of the plurality of peripheral signals is selectably routed to the main pad clock output node.

Abstract: A PCI/ISA computer system architecture is disclosed in which the ISA legacy circuitry (such as the interrupt request controller, DMA controller, and timer counter unit) is integrated within the system controller coupling the processor and PCI buses. Accordingly, the ISA bridge coupling the PCI and ISA buses is simplified relative to prior art PCI-ISA bridges. A high speed communications channel between the system controller and the ISA bridge is established by first placing an address on the PCI bus which is recognizable only by the system controller and the ISA bridge. Data transfer then occurs within standard PCI protocols, but need only require a subset of the A/D lines. Backwards compatibility is maintained, while system performance is improved and system cost is reduced.

Abstract: A computer system is described in which a table created in memory includes drive description data for one or more IDE devices included in the system. A command intercept circuit is described which intercepts device-identification commands and reroutes the device-identification operation to memory. The command intercept circuit includes an address decode circuit which asserts a first control signal upon decoding an address corresponding with the one or more IDE devices. A command decode circuit responds to the asserted first control signal to decode data and asserts a second control signal when the decoded data corresponds with a device-identification command. An address generator responds to the asserted second control signal to generate a memory address where the drive description data table is stored.

Abstract: In a computer system equipped with a hibernation type resume function including standby control functions, a power supply controller detects whether AC power or battery power is used as power for the system. When AC power is supplied, power is kept supplied to a memory even when a power switch is set off. When the power switch is set on later, an AC standby control function to set the system back to the operational state is executed based on the memory contents.

Abstract: A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is associated with a priority weight that indicates a probability that the associated requester will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requesters. In response to the current priorities of the requesters, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.

Abstract: A system for scheduling periodic events having varying rates. The system uses a linked list type data structure and an array to schedule the plurality of events having varying rates. In a preferred embodiment of the invention, data items are scheduled for transfer during a plurality of data transfer intervals. The linked list type data structure is traversed for each data transfer interval to collect the data items requiring transfer.

Abstract: The present invention is implemented in a peripheral component coupled to a peripheral component interconnect (PCI) bus. The peripheral component includes an internal device operating in an internal clock domain while the PCI bus operates in a PCI clock domain. The system of the present invention efficiently interfaces the internal device with the PCI bus. The present invention generates and couples a request for PCI bus ownership, originating from the internal device, to the PCI bus. The present invention then determines whether the PCI bus is idle or busy. Where the PCI bus is idle, a proceed signal is generated for the internal device. Where the PCI bus is busy, a do not proceed signal for the internal device is generated. Both the proceed and the do not proceed signals are synchronous to the internal clock domain. The PCI bus is acquired and a data transaction from the internal device is executed when the internal device receives the proceed signal.

Abstract: Apparatus and methods are provided for balancing a plurality of received processing requests among a plurality of servers of a processing system network. At least a subset of the processing requests are received from one or more of a plurality of network nodes of the processing system network. Storage means are provided for storing one or more measurable characteristics for at least each of a first server and a second server, both of which are operative to run a common application. A control circuit is also provided and is operative to receive a processing request to run the common application from a particular network node. The control circuit is further operative, in response to the processing request, to allocate either the first and/or the second server to run the common application as a function of the one or more measurable characteristics.

Abstract: In an information processing apparatus having a central processing unit, input/output units controlled by the central processing unit such as a liquid crystal display, a hard disk drive, a PCMCIA controller and a floppy disk drive, and a battery for supplying power to the central processing unit and the input/output units, a desired operating time of the information processing apparatus is set in a desired operating time setting circuit. Next, a residual capacity detecting circuit detects a residual capacity of the battery. On the basis of the desired operating time set by the desired operating time setting circuit and an operable time of the information processing apparatus calculated from the residual capacity of the battery detected by the residual capacity detecting circuit, the central processing unit commands an operating condition changing circuit to change operating conditions such that the desired operating time becomes longer than the operable time.

Abstract: In the server control section, the number of virtual channel wherein data is being transmitted is counted per service class. The data output rate from each service class corresponds to the number of counted virtual channels in each service class.

Abstract: Disclosed is a process and apparatus for controlling a power shutdown of an electrical device. The operations for controlling a power shutdown include determining a value MAX indicating a maximum number of safe power-on transitions that could have been experienced by the electrical device prior to a specified date. In addition, a threshold value P indicating a number of permissible power-on transitions prior to the specified date is determined from the value MAX. A value N indicating a number of power-on transitions that have occurred prior to the specified date is then determined. The power shutdown is inhibited if the value N is greater than the threshold value P, and otherwise allowed.

Abstract: A serial data interface device is coupled to electronic devices or other data transmitters or receivers, such as disk, optical, tape or CD-ROM drives, computers, printers, etc. The interface includes first and second ports capable of receiving and transmitting information to respective electronic devices, and first and second storage devices, such as frame buffers, for storing information. Each of the storage devices is coupled to both the first and second ports and are coupled to another electronic device. Included in each storage device is a main memory that is coupled to at least one of the electronic devices and at least one of the ports. A control memory that is coupled to the main memory is also included, along with a main memory arbiter that is coupled to the control memory and the main memory. Further included is a buffer allocation control that is coupled to the at least one electronic device and at least one of the ports.

Abstract: A method and apparatus are provided for reducing processor interrupt processing time in a data processing system. The data processing system includes a system processor, a system memory and an adapter coupled to the system processor and the system memory. The adapter checks for an interrupt condition. Responsive to identifying an interrupt condition, the adapter transfers predetermined interrupt status information to the system memory. Then the adapter raises an interrupt to the system processor. The adapter uses a direct memory access (DMA) descriptor or a source address and a destination address to move the predetermined interrupt status information to the system memory.

Abstract: A system and method for managing access by a user to a reusable resource. An integer pool is provided, along with program and hardware structures for obtaining an integer from the integer pool, for returning an integer to the integer pool. Responsive to the integer pool being empty, the user is waited. The integer pool includes a NEXT control structure from which a next integer is obtained for use and into which an integer is loaded upon being made available for reuse. The integer pool includes, for holding integers received from or to be provided to said NEXT control structure, (a) a LIFO stack or (b) a linked list by proxy. Reusable resources include data buffers, hardware status bits, logical connections and/or data channels.

Abstract: A computer system is presented having various peripheral devices coupled to a PCI local bus (i.e., an expansion bus), a subset of the peripheral devices having quaternary interfaces configured to communicate via quaternary signals conveyed upon the PCI local bus. The various peripheral devices may include a video/graphics card, a sound card, a hard disk drive, a CD-ROM drive, and a network interface card. When data is transferred from a master device to a target device, and the master and target devices both have quaternary interfaces, the master device converts the data to quaternary signals before transmitting the data the target device via the PCI local bus. The target device receives the quaternary signals from the PCI local bus and converts the quaternary signals to the binary data. Two binary digits (i.e.

Abstract: A method and system for providing arbitration within a ringlet-type interconnect of a computer system are described. By providing different arbitration values as part of out-of-band information and introducing asymmetry at a scrubber node, fair allocation of interconnect bandwidth is achieved. The number of arbitration values can be extended from a basic set to provide additional functionality to handle specialized traffic situations.

Abstract: A method of dispatching documents, wherein the basic idea is to first convert the documents from a customer-specific data format to a standardization data format, and only then to decide by means of a decision logic using the document in the standardized data format, whether the document is further transmitted to the recipient as an electronic document, or whether it is converted from the standardized to a postal data format in a converter station. The converter station then dispatches the document to a postal service printing center in the area where the recipient is located. There the document is printed out and directed for delivery by postal service personnel.

Abstract: A system and method for determining the physical presence, proper electrical coupling and predetermined identifying characteristics and attributes of various computer system elements and components, including both fixed and removable modules such as field replaceable units ("FRUs"), utilizing a minimum number of signal lines per component. In a preferred embodiment, a voltage divider is established between a first resistance in an environmental monitoring unit ("EMU") and a second resistance in an associated FRU wherein a voltage level taken intermediate the first and second resistances is indicative of a particular FRU attribute.

Abstract: A core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and either an AGP or PCI device(s). The core logic chip set also has an AGP/PCI arbiter having additional Request ("REQ") and Grant ("GNT") signal lines so that more than one PCI device may be utilized on the additional PCI bus. Selection of the type of bus bridge (AGP or PCI) in the core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or PCI device connected to the common bus.