Abstract: A system for transforming computer system interrupts from state based interrupts to event based interrupts. The system of the present invention includes an interrupt acknowledge detection circuit adapted to detect an interrupt acknowledge from a computer system. The interrupt acknowledge detect circuit is coupled to a vector match circuit. The vector match circuit is adapted to receive an interrupt vector from the computer system and determine whether the interrupt vector matches a predetermined interrupt vector within the vector match circuit. The vector match circuit is, in turn, coupled to an interrupt assertion circuit. The interrupt assertion circuit includes an internal interrupt request line and an external interrupt request line. The interrupt assertion circuit functions by asserting an interrupt signal via the external interrupt request line to the computer system in response to receiving a state based interrupt via the internal interrupt request line.

Abstract: A power sequence controller contains wakeup logic for responding to each wakeup event signal intercepted by the power sequence controller. The wakeup logic compares the intercepted wakeup event signal with a wakeup filter mask to determine if the wakeup event signal should be processed or ignored. If the wakeup event signal requires processing, the wakeup logic transitions the system's processor to a working state. The wakeup logic also determines if the intercepted wakeup event signal requires software processing. If so, a non-zero value associated with the wakeup event signal is stored in an interrupt source register, which causes the processor to execute an interrupt handler procedure and process the wakeup event signal when it transitions to a working state. The wakeup logic also evaluates the processor sleep state to determine if transitioning the processor from the sleep state to a working state requires execution of a processor wakeup procedure to return the processor to normal operation.

Abstract: A computer system is provided which supports an increase in the number of pluggable cards on the secondary I/O bus by using driver/receiver modules and direction control logic in place of more complex and more expensive bus to bus bridges. The number of pluggable cards on the I/O bus in a computer system is limited by the electrical loading of each card and the frequency of operations on the bus. Reducing the bus frequency provides more signal propagation time. The added signal propagation time supports the extension of the bus by driver/receiver modules and logic which controls the direction the driver/receiver modules drive the bus signals. Further, the driver/receiver modules support changing the hardware configuration of the system by adding or removing an I/O card without the need to cease data processing activity for the entire computer.

Abstract: A self-control type bus arbitration circuit and an arbitration method are disclosed, in which a bus arbiter is not needed, but entities commonly connected to a bus share 3 kinds of information, so that the entities can arbitrate the bus ownership use for themselves, and can occupy the bus in accordance with the priorities without mutual conflicts. Further, in order to solve the problem of the limit in the number of the sharing entities, the entities are made to use a clock information contained in the 3 kinds of information, i.e., the clock, the reference pulse and the in-use signal information, in such a manner that the clock is multiplied by an integer within the entities.

Abstract: In an interrupt control system to be applied, especially, to a laptop or notebook type personal computer that can use an expansion unit, an interrupt encoder converts the leading edges of a plurality of interrupt signals into serial data and transfers the serial data to an interrupt decoder. The interrupt decoder converts the serial data into original parallel interrupt signals, and outputs these signals to a programmable interrupt controller. A bridge circuit generates an idle cycle of a secondary bus by detecting the idle cycle of a primary bus, and generates latch pulses for interrupt serial data of the secondary bus.