Abstract: A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

Abstract: A data storage device with efficient page table block allocation. In one example, a memory includes a plurality of memory dies. A controller is configured to allocate a first region of the memory for storing data received from an external electronic device, and allocate a second region of the memory for storing metadata associated with the data. The first region includes a first memory die of the plurality of memory dies, and the second region includes a second memory die of the plurality of memory dies different from the first memory die. The controller is further configured to receive, from the external electronic device, a write command including first data to be written to the memory, control the memory to write the first data to the first region, generate first metadata associated with the first data, and control the memory to write the first metadata to the second region.

Abstract: A storage device may load, between a first time point at which information on candidate memory regions among a plurality of memory regions is started to be sent to an external device and a second time point at which a command requesting a map segment for a target memory region among the plurality of memory regions is received from the external device, all or a part of map segments corresponding to the candidate memory regions into a buffer.

Abstract: A data recording apparatus, including: a data obtaining section for obtaining multiple sets of measurement data obtained by measuring a measurement target; a determining section for determining for every measurement data of the multiple sets of measurement data whether a data volume is reducible; a data volume reducing section for reducing, in response to a result of the determining, a data volume for measurement data of which data volume has been determined as being reducible; a data compressing section for compressing multiple sets of measurement data including the measurement data of which data volume has been reduced; and a data recording section for recording the multiple sets of measurement data which have been compressed, is provided.

Abstract: An example apparatus can include a dual-rank dual-inline memory module (DIMM) device. The dual-rank DIMM device can include a plurality of dual-rank memory chip sets and each includes a first-ranked memory chip and a second-ranked memory chip. Each of the plurality of dual-rank memory chip sets can be positioned on a same side of the dual-rank DIMM device.

Abstract: A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. The DRAM is configured to respond to at least two types of commands. A first type of command (cache data access command) seeks to access a cache line of data, if present in the DRAM cache. A second type of command (cache probe command) seeks to determine whether a cache line of data is present, but is not requesting the data be returned in response. In response to these types of access commands, the DRAM device is configured to receive cache tag query values and to compare stored cache tag values with the cache tag query values. A hit/miss (HM) interface/bus may indicate the result of the cache tag compare and stored cache line status bits to a controller.

Abstract: A storage device comprising a volatile memory comprising a plurality of physical areas, a compression operation circuit configured to compress write data at a first rate to generate first compressed data, and a control operation circuit configured to divide the plurality of physical areas included in the volatile memory into first physical areas and second physical areas, store the first compressed data in the first physical areas, and store first logical information indicating an area storing the first compressed data, in a first selected area of the second physical areas.

Abstract: A self-managed DRAM module and method. A controller chip is configured to handle data access requests according to a process that includes: searching a first tier for an uncompressed cache data block; in response to a first tier hit, serving the uncompressed cache data block to service the data access request; in response to a first tier miss, searching a second tier for a compressed cache data block; in response to a second tier hit, decompressing the compressed cache data block to generate a decompressed cache data block, and inserting the decompressed cache data block into the first tier to service the data access request; and in response to a second tier miss, reading a compressed data block from DRAM, decompressing the compressed data block to generate a decompressed data block, and inserting the decompressed data block into the first tier to service the data access request.

Abstract: A system for dynamically controlling point-of-coherency or a point-of-serialization of shared data includes a plurality of processing engines grouped into a plurality of separate clusters and a shared communications path communicatively connecting each of the plurality of clusters to one another. Each respective cluster includes memory shared by the processing engines of the respective cluster, each unit of data in the memory being assigned to a single owner cluster responsible for maintaining an authoritative copy and a single manager cluster permanently responsible for assigning the owner cluster responsibility. Each respective cluster also includes a controller configured to receive data requests, track each of a manager status and an ownership status of the respective cluster, and control ownership status changes with respect to respective units of data based at least in part on the tracked ownership and manager statuses of the respective cluster.

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

Abstract: The present disclosure provides a controller. The controller is configured to: receive data to be compressed which includes multiple full data. Compressed data is output based on the data to be compressed. The compressed data includes at least first compressed data and second compressed data. The first compressed data and the second compressed data are obtained based on first data to be compressed and second data to be compressed in the data to be compressed respectively. The first compressed data includes a first base value and an incremental value of at least one of full data in the first data to be compressed relative to the first base value. The second compressed data includes a second base value and an incremental value of at least one of full data in the second data to be compressed relative to the second base value.

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.

Abstract: Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.

Abstract: A ring buffer storage method includes generating data of a first output according to Q input tokens of a large language model (LLM), and writing the data of the first output into last Q column vectors of an updated first cache tensor buffer matrix. A starting memory address of a first cache tensor buffer is shifted according to the number Q of input tokens of the LLM for updating the first cache tensor buffer. The first cache tensor buffer forms a first cache tensor buffer matrix. The updated first cache tensor buffer forms the updated first cache tensor buffer matrix. The first cache tensor buffer matrix includes a plurality of space segments. Each row of the first cache tensor buffer matrix includes C space segments. C is a cache size. The plurality of space segments have continuous memory addresses.

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to: perform a programming operation on the first group of memory cells of the first erase block; monitor a quantity of programming and/or erase operations performed on the second group of memory cells subsequent to the programming of the first group of memory cells; and perform an action on the first erase block responsive to the quantity of programming and/or erase operations performed on the second group of memory cells meeting a criteria.

Abstract: Techniques and mechanisms for selectively increasing or decreasing an amount of cache resources which are to be available for use in the provisioning of decoded micro-operations in a processor. In an embodiment, a processor core comprises both a first cache which is dedicated to caching micro-operations, and a second cache which is coupled to receive data, or non-decoded instructions. The core further comprises circuitry to monitor one or more cache performance characteristics of the core. Based on the one or more cache performance characteristics, the circuitry performs an evaluation to determine whether to increase—or alternatively, to decrease—the size of a pool of one or more caches which are to be available to receive micro-operations. In another embodiment, the second cache is added to the pool based on an indication of an overutilization of the first cache.

Abstract: A memory management unit controls, for each predetermined storage unit, a storage destination of data for which a writing request is made by a host. The memory management unit includes: a storage destination control unit configured to select the storage destination of the data for each storage unit from a main memory having the number of rewritable times less than 1015 and a cache memory able to execute copy back of writing the data for each storage unit to the main memory in accordance with a predetermined trigger; and a copy back detection unit that detects that the copy back is executed for each storage unit.

Abstract: One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to communication between a processor core and an accelerator. For example, a system can comprise a memory that can store computer executable components. The system can further comprise a processor that can execute the computer executable components stored in the memory, wherein the computer executable components can comprise a tracking component that can track a running state of an accelerator during execution of one or more functions by the accelerator. The computer executable components can further comprise an installation component that can install, via the accelerator, a message in a cache accessible to a processor core, wherein a cache line comprised within the cache can be updated based on installation of the message in the cache.

Abstract: When performing a consolidation process, entries (uRuns) in the update region (uRegion) of an update layer (uLayer) are typically erased immediately after the data in the uRuns is updated to a master layer (mLayer). The data may, at a later time, be copied back to the uRuns for read purposes. Rather than erasing the uRuns and then copying the data back to the uRuns for read purposes, the uRuns can simply not be erased after the consolidation. If space is needed, the uRuns can be erased without any need for consolidation. Furthermore, if another consolidation process occurs, the uRuns that were previously consolidated, but not erased, can simply be erased.

Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.