Abstract: A self-managed DRAM module and method. A controller chip is configured to handle data access requests according to a process that includes: searching a first tier for an uncompressed cache data block; in response to a first tier hit, serving the uncompressed cache data block to service the data access request; in response to a first tier miss, searching a second tier for a compressed cache data block; in response to a second tier hit, decompressing the compressed cache data block to generate a decompressed cache data block, and inserting the decompressed cache data block into the first tier to service the data access request; and in response to a second tier miss, reading a compressed data block from DRAM, decompressing the compressed data block to generate a decompressed data block, and inserting the decompressed data block into the first tier to service the data access request.

Abstract: A system for dynamically controlling point-of-coherency or a point-of-serialization of shared data includes a plurality of processing engines grouped into a plurality of separate clusters and a shared communications path communicatively connecting each of the plurality of clusters to one another. Each respective cluster includes memory shared by the processing engines of the respective cluster, each unit of data in the memory being assigned to a single owner cluster responsible for maintaining an authoritative copy and a single manager cluster permanently responsible for assigning the owner cluster responsibility. Each respective cluster also includes a controller configured to receive data requests, track each of a manager status and an ownership status of the respective cluster, and control ownership status changes with respect to respective units of data based at least in part on the tracked ownership and manager statuses of the respective cluster.

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

Abstract: The present disclosure provides a controller. The controller is configured to: receive data to be compressed which includes multiple full data. Compressed data is output based on the data to be compressed. The compressed data includes at least first compressed data and second compressed data. The first compressed data and the second compressed data are obtained based on first data to be compressed and second data to be compressed in the data to be compressed respectively. The first compressed data includes a first base value and an incremental value of at least one of full data in the first data to be compressed relative to the first base value. The second compressed data includes a second base value and an incremental value of at least one of full data in the second data to be compressed relative to the second base value.

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.

Abstract: Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.

Abstract: A ring buffer storage method includes generating data of a first output according to Q input tokens of a large language model (LLM), and writing the data of the first output into last Q column vectors of an updated first cache tensor buffer matrix. A starting memory address of a first cache tensor buffer is shifted according to the number Q of input tokens of the LLM for updating the first cache tensor buffer. The first cache tensor buffer forms a first cache tensor buffer matrix. The updated first cache tensor buffer forms the updated first cache tensor buffer matrix. The first cache tensor buffer matrix includes a plurality of space segments. Each row of the first cache tensor buffer matrix includes C space segments. C is a cache size. The plurality of space segments have continuous memory addresses.

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to: perform a programming operation on the first group of memory cells of the first erase block; monitor a quantity of programming and/or erase operations performed on the second group of memory cells subsequent to the programming of the first group of memory cells; and perform an action on the first erase block responsive to the quantity of programming and/or erase operations performed on the second group of memory cells meeting a criteria.

Abstract: Techniques and mechanisms for selectively increasing or decreasing an amount of cache resources which are to be available for use in the provisioning of decoded micro-operations in a processor. In an embodiment, a processor core comprises both a first cache which is dedicated to caching micro-operations, and a second cache which is coupled to receive data, or non-decoded instructions. The core further comprises circuitry to monitor one or more cache performance characteristics of the core. Based on the one or more cache performance characteristics, the circuitry performs an evaluation to determine whether to increase—or alternatively, to decrease—the size of a pool of one or more caches which are to be available to receive micro-operations. In another embodiment, the second cache is added to the pool based on an indication of an overutilization of the first cache.

Abstract: One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to communication between a processor core and an accelerator. For example, a system can comprise a memory that can store computer executable components. The system can further comprise a processor that can execute the computer executable components stored in the memory, wherein the computer executable components can comprise a tracking component that can track a running state of an accelerator during execution of one or more functions by the accelerator. The computer executable components can further comprise an installation component that can install, via the accelerator, a message in a cache accessible to a processor core, wherein a cache line comprised within the cache can be updated based on installation of the message in the cache.

Abstract: A memory management unit controls, for each predetermined storage unit, a storage destination of data for which a writing request is made by a host. The memory management unit includes: a storage destination control unit configured to select the storage destination of the data for each storage unit from a main memory having the number of rewritable times less than 1015 and a cache memory able to execute copy back of writing the data for each storage unit to the main memory in accordance with a predetermined trigger; and a copy back detection unit that detects that the copy back is executed for each storage unit.

Abstract: When performing a consolidation process, entries (uRuns) in the update region (uRegion) of an update layer (uLayer) are typically erased immediately after the data in the uRuns is updated to a master layer (mLayer). The data may, at a later time, be copied back to the uRuns for read purposes. Rather than erasing the uRuns and then copying the data back to the uRuns for read purposes, the uRuns can simply not be erased after the consolidation. If space is needed, the uRuns can be erased without any need for consolidation. Furthermore, if another consolidation process occurs, the uRuns that were previously consolidated, but not erased, can simply be erased.

Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

Abstract: A processor with a high-capacity last-level cache is shown, which includes a plurality of cores, a primary storage node, a plurality of cache slices corresponding to the cores, and a mesh-type interconnection structure. The cache slices are combined as a last-level cache. The mesh-type interconnection structure connects the primary storage node and the cache slices in a ring, and connects at least two cache slices non-adjacent to each other in the ring.

Abstract: A system and method for efficient execution of I/O operations in a storage environment including receiving, by a storage controller, an incoming I/O operation that can be serviced by a storage device while at least one pending operation is to be processed using the storage device, determining, based on an analysis by the storage controller of an operational state of a storage system that includes the storage device, whether processing the at least one pending operation is more efficient than issuing an alternative operation to the storage device, and issuing, by the storage controller, one or more instructions to the storage device.

Abstract: A data storage security system includes an end-user device and a transitory R/W storage unit conditionally connected to the outside world via a first air gap or to an offline storage system via a second air gap. The system includes a process control unit that controls all data cycles according to a predefined schedule and is equipped with tamper-responsive and tamper-resistant properties to protect against unauthorized access. A plurality of “n” cold data storage units that are never directly connected to the outside world and are protected from unauthorized access, and an immutable PLC switch that connects the cold data storage units to the data unit and the second air gap to the transitory R/W storage unit. The system provides unidirectional data transfer from the outside world to the offline storage system, and system status communication and monitoring through communication isolation element connections to prevent external tampering.

Abstract: Provided is an electronic device such as a storage apparatus coping with, with a simple configuration, a situation where data transfer cannot be performed because of an occurrence of an abnormality in the connection using a connector or the like, at the time of occurrence of a shock due to an earthquake or the like. The present invention is applied to an electronic device in which a drive that stores data and a control board having disposed thereon a controller that controls data transfer between the drive and another apparatus are connected via a connector.

Abstract: A computer-implemented method (CIM), according to one embodiment, includes identifying types of data that are suitable for caching, and mapping first application data elements of a predetermined application to the identified types of data to classify each of the first application data elements to one of the types of data. The CIM further includes computing priorities for the first application data elements, where the priorities are based on user use cases and access patterns of the first application data elements. A predetermined target is provided with recommendations regarding how to cache the first application data elements, where the recommendations are based on the computed priorities. A computer program product (CPP), according to another approach, includes a set of one or more computer-readable storage media, and program instructions, collectively stored in the set of one or more storage media, for causing a processor set to perform the foregoing method.

Abstract: A neural processing device is provided. The neural processing device comprises: a processing unit configured to perform calculations, an L0 memory configured to receive data from the processing unit and provide data to the processing unit, and an LSU (Load/Store Unit) configured to perform load and store operations of the data, wherein the LSU comprises: a neural core load unit configured to issue a load instruction of the data, a neural core store unit configured to issue a store instruction for transmitting and storing the data, and a sync ID logic configured to provide a sync ID to the neural core load unit and the neural core store unit to thereby cause a synchronization signal to be generated for each sync ID.

Abstract: A method or system for managing data placement in multi-tier storage devices. The system monitors usage of data items stored across storage devices, each associated with a performance tier. The system collects usage metrics for the data items, including access frequency, recency, file size, growth rate, sequentiality, or temporal access patterns. Multiple tiering methods are executed in parallel, with each method analyzing at least a subset of the usage metrics to generate tiering recommendations. These recommendations indicate whether each data item should be promoted to a higher-performance tier, demoted to a lower-performance tier, or retained in its current tier. The system aggregates the outputs of the tiering methods to compute a consensus decision for each data item. Based on the consensus, the system relocates data items to appropriate storage tiers.