Abstract: Systems and methods of the present disclosure enable intelligent dynamic caching of data by accessing an activity history of historical electronic activity data entries associated with a user account, and utilizing a trained entity relevancy machine learning model to predict a degree of relevance of each entity associated with the historical electronic activity data entries in the activity history based at least in part on model parameters and activity attributes of each electronic activity data entry. A set of relevant entities are determined based at least in part on the degree of relevance of each entity. Pre-cached entities are identified based on pre-cached entity data records cached on the user device, and un-cached relevant entities from the set of relevant entities are identified based on the pre-cached entities. The cache on the user device is updated to cache the un-cached entity data records associated with the un-cached relevant entities.

Abstract: Optimization of an aerial density capability (ADC) leveraging different qualities of media surfaces to which sub-portions of an encoded data portion are written. That is, data may be encoded to generate an encoded data portion according to a coding scheme. In turn, the encoded data portion may be divided into a plurality of sub-portions, each of which may be written to different media surfaces in a storage drive. The sub-portions may be read from the different media surfaces and combined to generate a recreated encoded data portion that is decoded using the coding scheme. As the encoded data portion is divided into sub-portions, the combined sub-portions may provide different error rates or signal-to-noise ratios that may allow for lower quality sub-portions to be assisted during the decoding process by higher quality sub-portions.

Abstract: A cache memory circuit capable of dealing with multiple conflicting requests to a given cache line is disclosed. In response to receiving an acquire request for the given cache line from a particular lower-level cache memory circuit, the cache memory circuit sends probe requests regarding the given cache line to other lower-level cache memory circuits. In situations where a different lower-level cache memory circuit is simultaneously trying to evict the given cache line at the particular lower-level cache memory circuit is trying to obtain a copy of the cache line, the cache memory circuit performs a series of operations to service both requests and ensure that the particular lower-level cache memory circuit receives a copy of the given cache line that includes any changes in the evicted copy of the given cache line.

Abstract: A neural core, a neural processing device including same and a method for lauding data of a neural processing device are provided. The neural core comprises a processing unit configured to perform operations, an L0 memory configured to store input data and an LSU configured to perform a load task and a store task of data between the processing unit and the L0 memory, wherein the LSU comprises a local memory load unit configured to transmit the input data in the L0 memory to the processing unit, and the local memory load unit comprises a target decision module configured to identify and retrieve the input data in the L0 memory, a transformation logic configured to transform the input data and thereby generate transformed data and an output FIFO configured to receive the transformed data and transmit the transformed data to the processing unit in the received order.

Abstract: An apparatus has processing circuitry, load tracking circuitry and load prediction circuitry to determine a prediction for a predicted load operation. It is determined whether the prediction is correct, and whether the tracking information indicates that, for a given younger load operation issued before it is known whether the prediction is correct, there is a risk of second target data associated with that given load operation having changed after having been loaded. Independent of whether the addresses of the predicted load operation and younger load operation correspond, at least the given load operation is re-processed when the prediction is correct and the tracking information indicates there is a risk of the second target data having changes after being loaded. This protects against ordering violations.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide superbkock management based on memory component reliabilities.

Abstract: A cache allocation method is provided. A core accesses a L3 cache when detecting a miss response from each of a L1 and a L2 cache accessed by the core through sending instruction fetching instructions configured to request L1 and L2 caches to return an instruction and data. The L1 cache is a private cache of the core, the L2 cache is a common cache corresponding to a core set including the core, the L3 cache is a common cache shared by core sets, and the miss response from the L2 cache carries network slice information. A planning unit in the L3 cache allocates the core sets to network slices, configures caches for the network slices according to the network slice information, and sends a hit response to the core. The hit response is configured to return data in a cache of a network slice corresponding to the core set.

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.

Abstract: The subject technology provides compact, searchable, random-access storage of genome data, particularly for large datasets, such as an entire human genome. The genome data may be stored in binary format, and compressed, in part, by leveraging characteristics of genome data itself, and in a way that maintains searchability of the stored compressed data.

Abstract: Aspects of the present disclosure calculate masked data shares dynamically inside the CPU boundary, and use a plurality of memory channels to write the masked data shares to an external memory location and/or to read the data shares from that external memory location. Each dynamically generated mask value is uniquely associated with a corresponding memory channel during writing data to the external memory. The modified masked data is unmasked or remasked during a subsequent read operation.

Abstract: A memory sub-system to, in response to a power up, executing a first loading process to load a sequence of a set of trim values into one or more registers of the memory sub-system. In response to a request to execute a memory access operation, interrupting the first loading process. A second loading process including loading a portion of the set of trim values corresponding to the request is executed. The memory access operation is executed using the portion of the set of trim values loaded into the one or more registers during the second loading process. Following execution of the memory access operation, the first loading process is resumed to load one or more unloaded trim values of the sequence of trim values.

Abstract: A method of operating a storage unit having non-volatile random-access memory (NVRAM) and solid-state memory is provided. The method includes transferring contents of the NVRAM to the solid-state memory, in response to detecting a power loss. The method includes during the transferring, having each of a plurality of channels in parallel, reading one or more of a plurality of logical unit numbers (LUNs) each corresponding to a portion of the NVRAM, performing an XOR of data of each of the one or more of the plurality of LUNs with data of a preceding LUN, and writing results of the XOR to the solid-state memory.

Abstract: A compression device includes an analyzer circuit, a control circuit, a compressor circuit, and a selector circuit. The analyzer circuit is configured to analyze first data that is input thereto and generate one or more parameter values regarding data compression and/or decompression. The control circuit is configured to generate at least one compression mode information indicating whether or not compression is to be performed, based on the one or more parameter values. The compressor circuit is configured to compress the first data into second data according to the compression mode information. The selector circuit is configured to output the first data if not compressed or the second data if the first data is compressed, together with the compression mode information.

Abstract: The embodiments of the present disclosure relate to a memory system for managing data corresponding to a plurality of zones and operating method thereof. According to embodiments of the present disclosure, the memory system may include i) a memory device including a plurality of memory blocks each including a plurality of pages, and ii) a memory controller configured to write data corresponding to a plurality of zones to a first area including two or more of the plurality of memory blocks, flush the data corresponding to a first zone among the plurality of zones to a second area including two or more of the plurality of memory blocks on determination that a flush condition set for the first zone is satisfied.

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.

Abstract: A storage device may include a storage medium, a storage device controller coupled to the storage medium, a host interface coupled to the storage device controller, and an attachable module interface configured to connect an attachable compute module to the storage device controller. The attachable module interface may include a data interface, a side-band interface, and/or a power interface. The attachable module interface may include a connector configured to connect the attachable compute module to the storage device controller. The storage device may include an enclosure having an opening configured to enable the attachable compute module to be connected to the attachable module interface through the opening. The storage device controller may be configured to utilize one or more resources of the attachable compute module. The storage device controller may be configured to communicate with the attachable compute module through one or more command extensions of a storage protocol.

Abstract: A system includes a memory and a processor. The memory is in communication with the processor and configured to initialize a secure interface configured to provide access to a virtual machine (VM) from a device, where the VM is associated with a level of security. A buffer is allocated and associated with the secure interface, where the level of security of the VM indicates whether the device has access to guest memory of the VM via the buffer. The buffer is then provided to the device. Inputs/outputs (I/Os) are sent between the device and the VM using the secure interface.

Abstract: An electronics assembly including a plurality of midplanes positioned between and coupled to a plurality of electronic components at one side of the plurality of midplanes and at least one electronic component at an opposite side of the plurality of midplanes in a manner so that the midplanes are vertically oriented in parallel relative to each other so as to define spaces therebetween. The midplanes each include electrical traces configured to send signals among and between the plurality of electronic components at the one side of the midplanes and the at least one electronic component at the opposite side of the midplanes.

Abstract: A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.