Abstract: A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.

Abstract: In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.

Abstract: Provided herein may be a data storage device for efficiently controlling performance and a method of operating the same. The data storage device may include a plurality of memory dies, a command storage configured to store commands, a credit information generator configured to generate and store maximum credit information indicating, for each command type, a maximum number of commands that are capable of being simultaneously performed by the plurality of memory dies, and a performance manager configured to provide the commands to the plurality of memory dies so that the plurality of memory dies process a number of commands greater than or equal to the maximum credit information.

Abstract: A data processing system and method, and a medium. In the present application, the data processing system includes a plurality of internal-memory devices and at least one host. After the host has received an accessing request, if the host has determined that the buffer element of the host does not store the target data that the accessing request is to access, the current host transmits the accessing request to the plurality of internal-memory devices, whereby the plurality of internal-memory devices respond to the accessing request, determine pre-buffered data by using the buffer-prefetching decision generator, and transmit the pre-buffered data to the buffer element of the current host to be stored.

Abstract: The present disclosure relates to automatic configuration and management of storage devices. In an implementation, a computer-implemented method is provided. The method includes receiving product information of storage devices and determining a new configuration of a signal conditioning device based on the product information. The signal conditioning device is coupled to the storage devices and is configured to improve quality of an input/output (I/O) signal of the storage devices. The method further includes determining whether the new configuration is different from a present configuration of the signal conditioning device; and in response to determining that the new configuration is different from the present configuration, transmitting a control signal to the signal conditioning device. The control signal indicates the new configuration.

Abstract: Methods, apparatuses, and systems for interleaving cache line data transfers and handling misses of speculatively fetched data are disclosed, including receiving, by a first cache, one or more data requests from a requesting device; transferring, by the first cache in response to the one or more data requests, data of a first cache line to a second cache; interrupting the transfer of data of the first cache line by transferring a first portion of data of a second cache line to the second cache; and transferring, by the first cache, remaining data of the first cache line to the second cache.

Abstract: Systems and methods are disclosed for concurrent support for multiple cache inclusivity schemes using low priority evict operations. For example, some methods may include, receiving a first eviction message having a lower priority than probe messages from a first inner cache; receiving a second eviction message having a higher priority than probe messages from a second inner cache; transmitting a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in a cache hierarchy; and, transmitting a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.

Abstract: A method for computational storage may include storing, at a storage device, a first portion of data, wherein the first portion of data may include a first fragment of a record, and a second portion of data may include a second fragment of the record, and appending the second fragment of the record to the first portion of data. The method may further include performing, at the storage device, an operation on the first and second fragments of the record. The method may further include determining that the first portion of data may include a first fragment of a record, and a second portion of data may include a second fragment of the record, wherein appending the second fragment of the record to the first portion of data may include appending, based on the determining, the second fragment of the record to the first portion of data.

Abstract: A system receives a user request to mount a child frontend application comprised in a primary frontend application. The system, in response to receiving the user request, checks whether the child frontend application is in a cache. The system, in response to determining that the child frontend application is not in the cache, mounts the child frontend application and initializes the child frontend application using a first lifecycle function that performs initial setup for the child frontend application. The system stores the child frontend application in the cache using a second lifecycle function for saving a current state of the child frontend application.

Abstract: A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

Abstract: A data storage device with efficient page table block allocation. In one example, a memory includes a plurality of memory dies. A controller is configured to allocate a first region of the memory for storing data received from an external electronic device, and allocate a second region of the memory for storing metadata associated with the data. The first region includes a first memory die of the plurality of memory dies, and the second region includes a second memory die of the plurality of memory dies different from the first memory die. The controller is further configured to receive, from the external electronic device, a write command including first data to be written to the memory, control the memory to write the first data to the first region, generate first metadata associated with the first data, and control the memory to write the first metadata to the second region.

Abstract: A storage device may load, between a first time point at which information on candidate memory regions among a plurality of memory regions is started to be sent to an external device and a second time point at which a command requesting a map segment for a target memory region among the plurality of memory regions is received from the external device, all or a part of map segments corresponding to the candidate memory regions into a buffer.

Abstract: A data recording apparatus, including: a data obtaining section for obtaining multiple sets of measurement data obtained by measuring a measurement target; a determining section for determining for every measurement data of the multiple sets of measurement data whether a data volume is reducible; a data volume reducing section for reducing, in response to a result of the determining, a data volume for measurement data of which data volume has been determined as being reducible; a data compressing section for compressing multiple sets of measurement data including the measurement data of which data volume has been reduced; and a data recording section for recording the multiple sets of measurement data which have been compressed, is provided.

Abstract: An example apparatus can include a dual-rank dual-inline memory module (DIMM) device. The dual-rank DIMM device can include a plurality of dual-rank memory chip sets and each includes a first-ranked memory chip and a second-ranked memory chip. Each of the plurality of dual-rank memory chip sets can be positioned on a same side of the dual-rank DIMM device.

Abstract: A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. The DRAM is configured to respond to at least two types of commands. A first type of command (cache data access command) seeks to access a cache line of data, if present in the DRAM cache. A second type of command (cache probe command) seeks to determine whether a cache line of data is present, but is not requesting the data be returned in response. In response to these types of access commands, the DRAM device is configured to receive cache tag query values and to compare stored cache tag values with the cache tag query values. A hit/miss (HM) interface/bus may indicate the result of the cache tag compare and stored cache line status bits to a controller.

Abstract: A storage device comprising a volatile memory comprising a plurality of physical areas, a compression operation circuit configured to compress write data at a first rate to generate first compressed data, and a control operation circuit configured to divide the plurality of physical areas included in the volatile memory into first physical areas and second physical areas, store the first compressed data in the first physical areas, and store first logical information indicating an area storing the first compressed data, in a first selected area of the second physical areas.

Abstract: A self-managed DRAM module and method. A controller chip is configured to handle data access requests according to a process that includes: searching a first tier for an uncompressed cache data block; in response to a first tier hit, serving the uncompressed cache data block to service the data access request; in response to a first tier miss, searching a second tier for a compressed cache data block; in response to a second tier hit, decompressing the compressed cache data block to generate a decompressed cache data block, and inserting the decompressed cache data block into the first tier to service the data access request; and in response to a second tier miss, reading a compressed data block from DRAM, decompressing the compressed data block to generate a decompressed data block, and inserting the decompressed data block into the first tier to service the data access request.

Abstract: A system for dynamically controlling point-of-coherency or a point-of-serialization of shared data includes a plurality of processing engines grouped into a plurality of separate clusters and a shared communications path communicatively connecting each of the plurality of clusters to one another. Each respective cluster includes memory shared by the processing engines of the respective cluster, each unit of data in the memory being assigned to a single owner cluster responsible for maintaining an authoritative copy and a single manager cluster permanently responsible for assigning the owner cluster responsibility. Each respective cluster also includes a controller configured to receive data requests, track each of a manager status and an ownership status of the respective cluster, and control ownership status changes with respect to respective units of data based at least in part on the tracked ownership and manager statuses of the respective cluster.

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

Abstract: The present disclosure provides a controller. The controller is configured to: receive data to be compressed which includes multiple full data. Compressed data is output based on the data to be compressed. The compressed data includes at least first compressed data and second compressed data. The first compressed data and the second compressed data are obtained based on first data to be compressed and second data to be compressed in the data to be compressed respectively. The first compressed data includes a first base value and an incremental value of at least one of full data in the first data to be compressed relative to the first base value. The second compressed data includes a second base value and an incremental value of at least one of full data in the second data to be compressed relative to the second base value.