Patents Examined by Hashem Farrokh
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Patent number: 11543972Abstract: The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.Type: GrantFiled: March 14, 2022Date of Patent: January 3, 2023Assignee: HITACHI, LTD.Inventors: Naoya Okada, Takashi Nagao, Kentaro Shimada, Ryosuke Tatsumi, Sadahiro Sugimoto
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Patent number: 11531622Abstract: Systems and methods are disclosed including a processing device operatively coupled to a first and a second memory device. The processing device can receive a set of data access requests, from a host system, in a first order and execute the set of data access requests in a second order. The processing device can further identify a late data access request of the set of data access requests and determine whether a data structure in a local memory associated with the processing device includes a previous outstanding data access request corresponding to an address associated with the late data access request. Responsive to determining that the data structure includes an indication of a previous outstanding data access request corresponding to the address associated with the late data access request, identifying a type of data dependency associated with the previous outstanding data access request and performing one or more operations associated with the type of data dependency.Type: GrantFiled: August 26, 2020Date of Patent: December 20, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Horia C. Simionescu, Chung Kuang Chin, Paul Stonelake, Narasimhulu Dharanikumar Kotte
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Patent number: 11513951Abstract: A method, computer program product, and computer system for identifying, by a computing device, a list of objects containing a plurality of physical layer blocks (PLBs). One or more next PLBs of the plurality of PLBs may be allocated from a selected free object of the list of objects. One or more additional free objects from the list of objects may be generated. Garbage collection may be performed between an inactive object of the plurality of objects and the selected free object.Type: GrantFiled: July 31, 2019Date of Patent: November 29, 2022Assignee: EMC IP Holding Company, LLCInventors: Amitai Alkalay, Uri Shabi
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Patent number: 11513954Abstract: During a concurrent Relocation Phase, a GC thread relocates live objects, as an application thread executes. References in a frame on a call stack are remapped if the application thread attempts to access the frame. References on the call stack remains stale if no application thread attempts access. The GC thread may proceed with a subsequent phase of a GC cycle, even if a frame has stale references and therefore has not assumed a remap state. During a concurrent Mark/Remap Phase, the call stack may include frames in different frame states. The GC thread selects appropriate operations for processing each frame based on the respective frame state. When the GC thread encounters a frame not in the remap state, references therein are first remapped, and then identified as roots. Hence, root reference remapping and identification are performed in a single concurrent phase of a GC cycle.Type: GrantFiled: March 25, 2021Date of Patent: November 29, 2022Assignee: Oracle International CorporationInventors: Erik Ă–sterlund, Per Liden, Stefan Mats Rikard Karlsson
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Patent number: 11494312Abstract: A storage device includes a flash memory array and a controller. The flash memory array stores a plurality of user data. After the controller finishes initialization, the controller accesses the user data stored in the flash memory array according to a plurality of host commands and an H2F mapping table, and records a plurality of address information about the user data in a powered-ON access table.Type: GrantFiled: March 20, 2020Date of Patent: November 8, 2022Assignee: Silicon Motion, Inc.Inventors: Jieh-Hsin Chien, Yi-Hua Pao
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Patent number: 11474750Abstract: A storage control apparatus comprising: a memory; and a processor coupled to the memory and configured to: receive a release request for a first storage area in a virtual storage area, release, among unit storage areas included in a physical storage area, one or more first unit storage areas allocated to the first storage area from the first storage area, execute overwrite processing of writing 0 to each of the first unit storage areas at a timing asynchronous with the release of the first unit storage areas, and when a write request is received to write data to the virtual storage area, execute write processing in which an unallocated unit storage area among the unit storage areas included in the physical storage area is allocated to a write destination area for the write data in the virtual storage area.Type: GrantFiled: December 4, 2020Date of Patent: October 18, 2022Assignee: FUJITSU LIMITEDInventors: Guangyu Zhou, Yukari Tsuchiyama
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Patent number: 11474944Abstract: This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.Type: GrantFiled: January 19, 2021Date of Patent: October 18, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Oluleye Olorode, Ramakrishnan Venkatasubramanian, Hung Ong
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Patent number: 11467972Abstract: In one embodiment, a microprocessor, comprising: a first data cache; and a second data cache configured to process both a miss in the first data cache resulting from a first load or store operation and an eviction from the first data cache to accommodate the first load or store operation, the second data cache configured to indicate to the first data cache that the eviction is complete before the eviction is actually complete based on a first state corresponding to the eviction.Type: GrantFiled: December 1, 2020Date of Patent: October 11, 2022Assignee: CENTAUR TECHNOLOGY, INC.Inventors: Douglas Raye Reed, Colin Eddy
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Patent number: 11467775Abstract: Example implementations relate to virtual persistent volumes for containerized applications. In an example, a plurality of different storage mounts are acquired from a mix of storage types. A containerized storage virtualization system creates and manages a virtual persistent volume that aggregates the acquired storage mounts. A mount point of the virtual persistent volume is provided to the containerized application. The virtual persistent volume includes a hierarchical structure that relates data objects of the containerized application by content-based signatures to a root object.Type: GrantFiled: October 15, 2019Date of Patent: October 11, 2022Assignee: Hewlett Packard Enterprise Development LPInventor: Bradley Cain
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Patent number: 11467745Abstract: A memory controller, for controlling a memory device including a plurality of memory blocks, includes a garbage collection controller configured to determine candidate blocks in which valid data is equal to or less than a predetermined ratio among the plurality of memory blocks, and configured to determine at least two or more memory blocks as victim blocks among the candidate blocks based on information on blocks that may be simultaneously erased among the plurality of memory blocks. The memory controller also includes an operation controller configured to control the memory device to copy valid data stored in the victim blocks to a different memory block.Type: GrantFiled: June 30, 2020Date of Patent: October 11, 2022Assignee: SK hynix Inc.Inventor: Jiman Hong
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Patent number: 11461020Abstract: The present disclosure relates to a memory device comprising a hybrid memory portion in turn comprising a main nonvolatile memory and an auxiliary nonvolatile memory, and a controller configured to store data information in the main nonvolatile memory. The controller of the present disclosure comprises a parity engine configured to accumulate temporary parity information in the auxiliary nonvolatile memory, the parity information being associated with the data information stored in the main nonvolatile memory; when the parity information accumulated in the auxiliary nonvolatile memory is complete, the parity engine is further configured to transfer the complete parity information from the auxiliary nonvolatile memory to the main nonvolatile memory. A related apparatus and a related method are also disclosed.Type: GrantFiled: October 9, 2019Date of Patent: October 4, 2022Assignee: Micron Technology, Inc.Inventor: Paolo Amato
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Patent number: 11461035Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.Type: GrantFiled: December 18, 2020Date of Patent: October 4, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Priya Venkataraman, Pitamber Shukla, Scott A. Stoller, Giuseppina Puzzilli, Niccolo' Righetti
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Patent number: 11455118Abstract: Implementations of the present disclosure provide a memory apparatus that includes a plurality of memory cells stored with memory data in N dies. Each of the N dies includes M planes. Each of the M planes includes a memory block. The apparatus also includes a controller configured to determine J layers in the memory block in each of the M planes and in each of the N dies, each of the J layers comprising a pair of adjacent gate conductive layers. The controller is also configured to determine M sets of stripes. Each of the M sets of stripes comprising a plurality of data portions stored in a respective one of the M planes. The controller is further configured to determine M sets of parity data portions. The controller is further configured to control a temporary storage unit to store the M sets of parity data portions.Type: GrantFiled: March 30, 2021Date of Patent: September 27, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Weizhen Kong, Jian Cao, Wei Tao, Ling Du, Yuan Tao
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Patent number: 11449269Abstract: Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.Type: GrantFiled: July 22, 2020Date of Patent: September 20, 2022Assignee: Micron Technology, Inc.Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
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Patent number: 11449434Abstract: Systems and methods for memory management for virtual machines. An example method may comprise running, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor which manages a Level 2 virtual machine having encrypted memory pages. The Level 1 hypervisor may generate a shadow page table where each shadow page table entry of the plurality of shadow page table entries maps a Level 2 guest virtual address of a Level 2 address space associated with the Level 2 virtual machine to a corresponding Level 1 guest physical address of a Level 1 address space associated with the Level 1 virtual machine. The Level 0 hypervisor may generate a Level 0 page table comprising a plurality of Level 0 page table entries that maps a Level 1 guest physical address to a corresponding Level 0 host physical address.Type: GrantFiled: April 13, 2020Date of Patent: September 20, 2022Assignee: Red Hat, Inc.Inventors: Michael Tsirkin, Andrea Arcangeli
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Patent number: 11437103Abstract: A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.Type: GrantFiled: December 4, 2020Date of Patent: September 6, 2022Assignee: Micron Technology, Inc.Inventors: Umberto Minucci, Tommaso Vali, Fernanda Irrera, Luca De Santis
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Patent number: 11429295Abstract: Provided are a storage device storing data on the basis of key-value and an operating method thereof, wherein the storage device separates and manages a plurality of keys and a plurality of values respectively corresponding to the plurality of keys, and includes a first controller processing a first key and a first value corresponding to the first key, a second controller processing a second key and a second value corresponding to the second key, and a nonvolatile memory storing the first key, the second key, the first value, and the second value, wherein the first key includes information about the second controller regarding a processing core for the second value processed next to the first value.Type: GrantFiled: September 30, 2020Date of Patent: August 30, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wan Heo, Satish Kumar, Hwang Lee, Byounggeun Kim, Chansoo Kim, Sangyoon Oh
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Patent number: 11416399Abstract: A server includes a field programmable gate array (FPGA) partitioned into a set of partial reconfiguration (PR) slots and a memory that supports a set of logical buffers. A deterministic application request module (DARM) receives application requests to allocate the set of reconfiguration slots to one or more tenants and the one or more tenants configure the allocated reconfiguration slot to perform tasks. The DARM stores data associated with the application request in a first logical buffer from the set of logical buffers. A reconfiguration slot scheduling (RSS) module identifies a first reconfiguration slot from the set of reconfiguration slots and associates the first reconfiguration slot with the first logical buffer. A reconfiguration slot initialization (RSI) module reconfigures the first reconfiguration slot to perform the tasks based on the data stored in the first logical buffer.Type: GrantFiled: June 25, 2020Date of Patent: August 16, 2022Assignee: Nokia Solutions and Networks OyInventors: Andrea Enrici, Bogdan Uscumlic
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Patent number: 11416387Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.Type: GrantFiled: June 12, 2020Date of Patent: August 16, 2022Assignee: Kioxia CorporationInventors: Hideki Yoshida, Shinichi Kanno
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Patent number: 11409443Abstract: A data storage device including, in one implementation, a non-volatile memory device and a controller coupled to the non-volatile memory device. The non-volatile memory device includes a memory block. The controller is configured to receive a cycle operation request and perform a wear-level mitigation operation in response to receiving the cycle operation request. To perform the wear-level mitigation operation, the controller is configured to determine a read state condition of the memory block, perform the requested cycle operation, and increment a cycle count of the memory block by a value based on the determined read state condition of the memory block. The first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.Type: GrantFiled: February 17, 2021Date of Patent: August 9, 2022Assignee: Western Digital Technologies, Inc.Inventors: Ravi Kumar, Deepanshu Dutta, Niles Yang, Mark Shlick