Patents Examined by Hau Nguyen
  • Patent number: 8736617
    Abstract: A method of displaying graphics data is described. The method involves accessing the graphics data in a memory subsystem associated with one graphics subsystem. The graphics data is transmitted to a second graphics subsystem, where it is displayed on a monitor coupled to the second graphics subsystem.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: May 27, 2014
    Assignee: Nvidia Corporation
    Inventors: Stephen Lew, Bruce R. Intihar, Abraham B. de Waal, David G. Reed, Tony Tamasi, David Wyatt, Franck R. Diard, Brad Simeral
  • Patent number: 8730253
    Abstract: One embodiment of the present invention sets forth a technique for decomposing and filling cubic Bèzier segments of paths without tessellating the paths. Path rendering may be accelerated when a GPU or other processor is configured to perform the decomposition operations. Cubic Bèzier paths are classified and decomposed into simple cubic Bèzier path segments based on the classification. A stencil buffer is then generated that indicates pixels that are inside of the decomposed cubic Bèzier segments. The paths are then filled according to the stencil buffer to produce a filled path.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: May 20, 2014
    Assignee: NVIDIA Corporation
    Inventor: Mark J. Kilgard
  • Patent number: 8730242
    Abstract: To perform time slice-based visual prediction, a weighted moving aggregate of data values in a data set is calculated over previous time slices to predict data values based on interactive user input. A visual accuracy indicator is generated for display to indicate a quality of prediction of data values at different times. A visualization presents data values from the data set and the predicted data values, where the data values from the data set and the predicted data values are represented as corresponding cells.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: May 20, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ming C. Hao, Umeshwar Dayal, Halldór Janetzko, Ratnesh Kumar Sharma
  • Patent number: 8723874
    Abstract: Methods and apparatus are provided for efficiently and intelligently communicating characteristic information in video graphics switcher environments. An intelligent video graphics switcher obtains display device characteristic information associated with multiple display devices and maintains updated characteristic information. When an event such as a connection/disconnection or switching event occurs between the video graphics switcher and a display device, the characteristic information is communicated to an appropriate host by triggering a connection/disconnection event with the host.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 13, 2014
    Assignee: RGB Spectrum
    Inventors: Don Day, David Haycock
  • Patent number: 8723873
    Abstract: Methods and apparatus are provided for efficiently and intelligently communicating characteristic information in video graphics switcher environments. An intelligent video graphics switcher obtains display device characteristic information associated with multiple display devices and maintains updated characteristic information. When an event such as a connection/disconnection or switching event occurs between the video graphics switcher and a display device, the characteristic information is communicated to an appropriate host by triggering a connection/disconnection event with the host.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: May 13, 2014
    Assignee: RGB Spectrum
    Inventors: Don Day, David Haycock
  • Patent number: 8723889
    Abstract: A display controller including a pixel processor which processes working pixel data for each pixel of a frame, and which includes an overlap detector, a collision detector, and a construction processor. The overlap detector detects an overlap when any new pixel value of a new update region is within a region of a current update of the frame. The collision detector issues a correction request when at least one pixel within the overlap region has a begin pixel value prior to the current update that is different from an end pixel value provided by the current update, and when a new pixel value provided by the new update for the pixel is different from the end pixel value. The construction processor updates the working pixel data before the current update is completed using a new pixel value for each non-overlapping pixel.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiaohui Wang, Sebastian Ahmed
  • Patent number: 8723877
    Abstract: A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (CPUs) and graphic processing units (GPUs). A system creates a subbuffer from a parent buffer for each of a plurality of heterogeneous compute units. If a subbuffer is not associated with the same compute unit as the parent buffer, the system copies data from the subbuffer to memory of that compute unit. The system further tracks updates to the data and transfers those updates back to the subbuffer.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: May 13, 2014
    Assignee: Apple Inc.
    Inventors: Aaftab A. Munshi, Ian R. Ollmann
  • Patent number: 8717390
    Abstract: An integrated system and method for content-aware video retargeting. An interactive framework combines key frame-based constraint editing with numerous automatic algorithms for video analysis. This combination gives content producers a high level of control of the retargeting process. One component of the framework is a non-uniform, pixel-accurate warp to the target resolution that considers automatic as well as interactively-defined features. Automatic features comprise video saliency, edge preservation at the pixel resolution, and scene cut detection to enforce bilateral temporal coherence. Additional high level constraints can be added by the producer to achieve a consistent scene composition across arbitrary output formats. Advantageously, embodiments of the invention provide a better visual result for retargeted video when compared to using conventional techniques.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: May 6, 2014
    Assignee: Disney Enterprises, Inc.
    Inventors: Markus Gross, Alexander Hornung, Manuel Lang, Philipp Kraehenbuehl
  • Patent number: 8711162
    Abstract: An arbitration circuit to arbitrate an issue between a read/write command and a scan command and a display driver integrated circuit including the arbitration circuit.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Wan-jung Kim, Chan-ho Lee, Tae-hyoung Kim
  • Patent number: 8704840
    Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: William Radke
  • Patent number: 8698805
    Abstract: Embodiments of the invention provide techniques for calculating volumetric obscurance. Volumetric obscurance is an alternative approach to screen-space ambient occlusion that can be efficiently evaluated on graphics processing units (GPUs). In one embodiment, to calculate the volumetric obscurance at a particular pixel location, an integral is calculated that sums distances between depth values in a depth buffer relative to a surface of a sphere centered at the pixel location. In alternative embodiments, a statistical model of the depth buffer can be used to calculate the volumetric obscurance.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: April 15, 2014
    Assignee: Disney Enterprises, Inc.
    Inventor: Peter-Pike Johannes Sloan
  • Patent number: 8698823
    Abstract: A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: April 15, 2014
    Assignee: NVIDIA Corporation
    Inventors: Michael Toksvig, Erik Lindholm
  • Patent number: 8698842
    Abstract: Systems and methods that provide graphics using a graphical engine are provided. One such system includes at least one graphical pipeline and a graphical engine. The at least one graphical pipeline is coupled to a bus and operable to generate a plurality of graphical layers. The graphical engine is coupled to the bus and operable to receive, over the bus, the plurality of graphical layers. The graphical engine is operable to composite the received plurality of graphical layers into a composite graphical layer, and to store the composite graphical layer in a local memory of the graphical engine.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 15, 2014
    Assignee: Broadcom Corporation
    Inventors: David A. Baer, Darren Neuman
  • Patent number: 8698741
    Abstract: The invention provides, in some aspects, medical apparatus with software-based cursor control and graphical user interface hotspot selection. This can be used, by way of non-limiting example, as part of a graphical user interface by which doctors, nurses, patient care technicians, other health care providers, and/or patients can enter data into enter data and/or to control the apparatus and/or associated medical equipment.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: April 15, 2014
    Assignee: Fresenius Medical Care Holdings, Inc.
    Inventors: Fei Wang, Martin Crnkovich
  • Patent number: 8692848
    Abstract: A method and system are provided in which one or more processors and/or circuits are operable to generate position information for a plurality of primitives utilizing a coordinate shader, one or more lists based on the generated position information, and rendering information for the plurality of primitives utilizing a vertex shader and the generated one or more lists. The generated one or more lists may comprise indices associated with one or more primitives from the plurality of primitives and with one or more tiles from a plurality of tiles in a screen plane. The position information and the one or more lists may be generated during a first rendering phase, and the rendering information may be generated during a second rendering phase different from the first rendering phase. The coordinate shader may perform a subset of the operations supported by the vertex shader.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: April 8, 2014
    Assignee: Broadcom Corporation
    Inventors: James Adams, Gary Keall, Eben Upton, Giles Edkins
  • Patent number: 8681164
    Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: March 25, 2014
    Assignee: STMicroelectronics, Inc.
    Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
  • Patent number: 8674984
    Abstract: A method for generating a mesh of a subterranean medium comprising at least one sedimentary layer crossed by at least one fault. The at least one layer is delimited vertically by two geological horizons discretized by two triangulated three-dimensional surfaces. For each horizon, a three-dimensional gridded surface is constructed by means of isometric unfolding accounting for the presence of the fault. Next, the mesh of the subterranean medium is generated by generating cells by creating links between the three-dimensional gridded surfaces. To do this, nodes of the first gridded surface that are situated on one side of the fault which differs from the side of a node of the second gridded surface having the same coordinates i, j are detected. Each non-detected node is joined with a node of the second gridded surface having the same coordinates i, j, and each detected node is joined with the fault by considering a direction of a neighboring node.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: March 18, 2014
    Assignee: IFP Energies Nouvelles
    Inventors: Longmin Ran, Abdallah Benali, Houman Borouchaki, Chakib Bennis
  • Patent number: 8675004
    Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: March 18, 2014
    Assignee: Apple Inc.
    Inventors: Joseph P. Bratt, Shing Choo, Peter F. Holland, Timothy J. Millet, Brijesh Tripathi
  • Patent number: 8674999
    Abstract: An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 18, 2014
    Assignee: Qimonda AG
    Inventor: Thomas Hein
  • Patent number: 8669991
    Abstract: One embodiment of the present invention sets forth a method macro expander (MME) coupled to a driver and the processing pipeline of a graphics processing unit. In operation, the MME receives, from the driver, a first packet of work indicating a macro stored in an instruction memory that is to be executed. The MME then executes the commands of the macro in the instruction memory to generate a second packet of work, and the second packet of work is then transmitted to the processing pipeline for further execution.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: March 11, 2014
    Assignee: Nvidia Corporation
    Inventors: Jerome Francis Duluk, Jr., Jesse David Hall, Patrick R. Brown, Gregory Scott Palmer, Eric S. Werness