Abstract: A plurality of core chips are arranged on a body of a semiconductor device, and a plurality of voltage down circuits are arranged on the outside of the core chips to lower a power supply voltage to a plurality of operating voltages of the core chips. In cases where the operating voltages differ from each other, each core chip is connected to the corresponding voltage down circuit. In cases where the operating voltages are the same as each other, one voltage down circuit corresponding to the same operating voltage is connected to a line surrounding the core chips, and the core chips are connected to the line. In cases where the operating voltage of one core chip is equal to the power supply voltage, the core chip is directly connected to a line of the power supply voltage.

Abstract: Provided are a layout verification apparatus and a layout verification method, each employing an L/S matrix to achieve higher accuracy of verification, as well as a program thereof. The layout verification method is realized by dividing each segment in accordance with the layout of its surrounding other polygon. For instance, in FIG. 3, since the left side of polygon (P1) (i.e., segment Segc) is, over its entire segment length, most adjacent to polygon (P5), this side is not divided. Since the upper side of the polygon (P1) is, only in part of its segment length, most adjacent to polygon (P7) within distance (R), this side is divided into segment (Segb1) that corresponds to the part adjacent to the polygon (P7), and segment (Segb2) that is the rest. Then, the L/S matrix is referred to segment by segment, to judge whether the polygon can be resolved.

Abstract: A method for facilitating the assignment of alternating voltage potentials to a set of shield wires in a routing layer of an integrated circuit involves generating a set of vertices representing at least a portion of the set of shield wires and of edges representing adjacency of at least the portion of the set of shield wires, minimizing a set of edges in the set of vertices to obtain a minimized set of vertices, and assigning a first indicator to one vertex of the minimized set of vertices.

Abstract: The present invention includes methods for optimizing integrated circuit design by identifying a buffer tree in the integrated circuit design, the buffer tree having a plurality of vertices, each representing one of a buffer and an inverter, and also having branches, between the vertices, each representing an electrical connection. A plurality of optimization devices are applied in a random sequence to the vertices of the buffer tree. Such devices can include, for example, cell type modification; insertion of one buffer; insertion of several buffers; interchange of two grandchildren; making a grandchild into a child; making a child a grandchild; interchanging a child and a grandchild; eliminating two inverters; removing one buffer; removing more than one buffer; and removing two inverters.

Abstract: With the assistance of a computer, in order to verify a layout of an integrated circuit, for one or more selected interconnection networks that are contained in the layout, the capacitance with respect to other interconnection networks contained in the layout is calculated as follows: A filter polygon is determined, which corresponds to the form of the selected interconnection network, the dimensions of the filter polygon are enlarged by a predeterminable extent relative to the dimensions of the selected interconnection networks. The portions of the other interconnection networks which overlap the filter polygon are determined, and the capacitance between the selected interconnection networks and the portions of the other interconnection networks which overlap the filter polygon is determined.

Abstract: A test system for a design of a network device under test, having multiple design modules, includes multiple field programmable gate arrays configured for performing operations of the respective design modules. The test system also includes shared resources, where each field programmable gate array includes resource control logic for accessing the shared resources according to a prescribed shared resource protocol. Hence, the resource control logic of each of the field programmable gate arrays cooperate to ensure there is no interference between the multiple field programmable gate arrays for the shared resources. Hence, a design can be partitioned into multiple field programmable gate arrays, enabling testing of large scale designs; moreover, the partitioning of the design into multiple FPGAs enables each design module to be separately controlled, enabling design revisions to different design modules as necessary, without any other modification to the remaining test system.

Abstract: A novel method and corresponding system are provided for safely reconfiguring a portion of a reprogrammable logic device. The method includes the steps of identifying the nets to be reprogrammed, identifying the device drivers that may induce signal contention during or after a new configuration on the identified nets, electrically isolating the identified drivers, and implementing the new configuration.

Abstract: A run time controller which controls the sequence of evaluations of combinatorial blocks in a functional verification system. A target design is partitioned into multiple clusters, with each cluster in turn containing multiple combinatorial blocks. Evaluation units may be designed to evaluate the combinatorial blocks in each cluster in parallel. The run time controller may contain a flow processor, a flow control memory, and a cluster control memory. The contents of cluster control memory may be configured to specify how different condition bits/registers are to be altered upon evaluation of each cluster. The flow control memory is configured with instructions to data from different sources to be sent the evaluation units. In addition, the instructions are designed to examine the status of different registers and cause the flow processor to alter the evaluation flows.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Abstract: In response to a design request, fault detection strategy optimizing means selects RT-VCs and a fault detection method from a VCDB. The design request includes: requirements for a system LSI (e.g., area, number of pins, test time and information about the weights of prioritized constraints); and VC information. The fault detection strategy optimizing means performs computations for optimization in view of various parameters, thereby specifying a best fault detection strategy and a method of constructing a single-chip fault detection controller. On the VCDB, multiple VCs associated with the same function and mutually different test techniques are stored. By weighting the parameters affecting a test cost in accordance with a user defined priority order, a test technique of the type minimizing the total test cost can be selected from the VCDB.

Abstract: A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The keepout file includes a map of areas of an integrated circuit design where fill patterns cannot be placed. The map of areas from the keepout file is then overlaid with a fill pattern to yield a fill-pattern file. Fill patterns from the fill-pattern file is removed from locations that coincide with locations as defined by the keepout data to yield a final-fill file with crucial fill pattern data. The crucial fill pattern data from the final-fill file is overlaid on the design layout data in the chip design layout file to yield a complete design layout file. Finally, the design rule integrity and logical to physical correspondence of the complete design layout file is verified.

Abstract: The number of good IC (Integrated Circuit) chips per wafer or time to print a wafer is optimized by examining a number of prospective chip-to-wafer offsets, and, for each offset, a number of prospective arrangements of reticle exposures (shot maps). Integrating such a shot map optimization sub-system with a reticle layout (frame generation) sub-system permits creation of an optimal shot map for an IC chip of known size. These two sub-systems can also be used iteratively to explore a range of possible chip sizes, presenting the results in a simple graphical form. The instant invention integrates shot map optimization, frame generation and chip size optimization/visualization into a single system, providing the chip designer with insight into the impact of chip size on manufacturability.

Abstract: A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming one or more interconnect layer specialized according to a desired storage capacity and cutting the wafer using a sawing pattern according to the desired storage capacity.

Abstract: A system, device, and method for dynamically testing integrated circuits is disclosed. The system includes a first integrated circuit including input pins, output pins, normal operating logic, and control logic. The control logic is connectable to the input pins and configured to initiate a test interval based on a state of the input pins and to record the state of the input pins during the test interval. A second integrated circuit of the system includes input pins, output pins, normal operating logic, and test control logic. The control logic connectable to the output pins and configured to generate a user programmable set of test output signals. At least some of the output pins of the second integrated circuit are connected to at least some of the input pins of the first integrated circuit. The test control logic of the first integrated may be configured to initiate the test interval when the state of the input pins matches a predefined state.

Abstract: A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run interconnect lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing on the remaining interconnect lines and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without critically increasing the line-to-line capacitance of these lines and adversely affecting the overall line RC time constant.

Abstract: An apparatus performs a process for partitioning a netlist. The process picks a unique color for each clock and traverses the clock tree coloring the latches in support of that clock tree with that color. The process then colors the fanout logic cones for each latch and notes any coloring collisions. In the case of a multicolored gate, the process retimes the network by moving the terminating latch backwards, towards the collision, to enable single coloring of the gate. The process then performs a depth-first search on the fanout logic of each primary input to the first latch encountered or a primary output. If a primary output is encountered, the path is colored with a color representing the free-run domain. Otherwise, the process colors the path with the color of the terminating latch. Next, the process duplicates the fanin cones for remaining multicolored gates so that a copy of the logic can be incorporated with each independent domain.

Abstract: The present invention comprises method for optimizing an integrated circuit design that includes computing of capacities and delays of an integrated circuit design, resynthesizing said integrated circuit design utilizing a plurality of local optimization procedures, and removing overlap the local optimization procedures can include a local resynthesis of logic trees procedure that utilizes multiple cost functions, a dynamic buffer and inverter tree optimization procedure, and a cell resizing procedure. Generally, faster local optimization procedures are applied first and slower, more thorough procedures are applied to areas where the faster procedures have not solved the optimization tasks.

Abstract: A circuit comprising a plurality of gates and a plurality of control circuits. The plurality of gates may each have an output connected to an input of a next gate of the plurality of gates. The plurality of control circuits may be connected to a second input of one or more gates of the plurality of gates. The plurality of control circuits may simulate switching.

Abstract: A component-based method and system for structured use of a plurality of software tools. In various embodiments, components are used to package objects that are constructed to test an electronic circuit design using different software tools. Flow files describe different execution sequences for selected ones of the plurality of software tools, and a first set of objects contains one or more methods for interfacing with a selected one or more of the flow files. A second set of objects contains one or more methods for collecting data from the software tools and entering the data in a database. The components include one or more methods that invoke one or more methods of the first and second sets of objects.

Abstract: A library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool suite may include a post operations tool, an audit tool, a custom interface, a setup file and a place and route model preparation utility which interact with the conventional tools and design data to automate and ensure integrity of the physical design process. The tool suit facilitates automatically generating libraries corresponding to an overall cell plan, generating attributes defining strength of connection between possible pin placements within a cell to facilitate routing inter-cell nets through a cell, and auditing cells for errors prior to inclusion in a manufacturing library.