Abstract: A method for generating a semiconductor test program is disclosed. The method is practiced by first creating a test plan according to a test key database, then take out the related parameters from the other databases in light of the test item in the test plan and creating a semiconductor test program. The semiconductor test program is attached to the wafer acceptance test (WAT) main program as a sub-program. The method for generating the auto-testing program can promote the efficiency for writing a test program and is easy to expand and maintain according to the progress of semiconductor processes.

Abstract: A method is provided for manufacturing a die. A supply voltage is provided to a power plane of a selected integrated circuit, formed in and on a semiconductor substrate, having a selected design, so that a respective test current flows through a plurality of test elements, of the selected integrated circuit, each being connected to a respective test point on the power plane, the test points being spaced from one another. A magnitude of each respective test current is detected. A respective test voltage is calculated at each respective test point utilizing the respective magnitude of the respective test current flowing through the respective test element connected to a respective test point. The respective test voltages are utilized to determine at which ones of the test points the respective test voltages are more than a predetermined maximum below a supply voltage.

Abstract: An apparatus or method for testing the setup time and hold time specifications of a chip. An apparatus according to the invention would include a first chip, a second chip, and multiple links coupling the first chip to the second chip. One of the links carries a clock signal between the chips. Other links carrying data have propagation delays different from the propagation delay of the link carrying the clock signal. The relation of the delays for the data links to the delay for the clock link determines a particular setup and/or hold time tested.

Abstract: An initial arrangement is effected based on a net list and a cell library. Combination functions are extracted from a cost function. An optimum estimated temperature is calculated based on the difference between values of the cost function before and after two adjacent elements that have been selected randomly from elements to be arranged are interchanged in position, while near-optimum estimated temperatures are calculated based on the differences between respective values of the combination functions before and after the positional interchange. Of the near-optimum estimated temperatures, those lower than the optimum estimated temperature are recorded in a temperature schedule list together with the optimum estimated temperature. Thereafter, the Monte-Carlo method based on a random positional interchange between the elements to be arranged using the cost function is executed in order of the decreasing temperatures recorded in the temperature schedule list, whereby the initial arrangement is improved.

Abstract: A method of generating a cell function and timing model library in a standard library format includes the steps of (a) receiving as input a model source file, a technology dependent file, and a cell list data file; (b) parsing a functional description for each cell in the cell list data file from the model source file; (c) expanding parameterized timing data for each cell in the cell list data file from the technology dependent file; and (d) generating as output a cell model library in a standard library format from the parameterized timing data.