Abstract: An electric stringed instrument, namely a fiddle stick (10) and a combination magnetic and contact pickup (20) are disclosed. Fiddle stick (10) has a set of five metallic strings (16) being attached under tension along the length of elongated body (11). Elongated body (11) includes a head (12), a neck (13), a finger board (14), base segment (15), a tail piece (18) and a chin rest (33). An adjustable position combination electromagnetic and contact pickup (20) is suspendedly attached to elongated body (11) and includes a first coil (21), and a magnet (32). A second humbucking coil (29), having an opposite electrical sense to that of first coil (21), is suspended within elongated body (11) to inhibit electrical noise.

Abstract: In a noise shaping requantization circuit, a requantized output digital signal and an input digital signal are processed in an operational circuit whose output signal is requantized to provide the requantized output signal. The processing circuit can be configured in a variety of ways but has fixed limitations established for circuit parameters which determine the relationship between the output signal therefrom and the two input signals. By comparison with prior art noise shaping requantization circuits, a substantially better S/N ratio (assuming equal values of output signal resolution), or a substantially lower degree of output signal resolution (assuming equal values of S/N ratio) can be achieved, with stable operation.

Abstract: An incremental position encoder and method are disclosed herein for a close loop position control system, for example, for positioning a printing device in an electronic postage meter. The incremental position encoder and method includes three channels, first and second of which provide signals for coarse position determination and first or second and third of which provide signals for fine position determination.

Abstract: A high-speed, high-resolution superconducting counting A/D converter providing greatly increased conversion speeds with a low device count. The superconducting counting A/D converter includes a double-junction SQUID quantizer and a bidirectional binary counter having n stages of grounded four-junction SQUID flip-flops, where n is the number of bits of accuracy of the counter. The quantizer continuously tracks an analog signal, generating up-count and down-count voltage pulses of the same polarity on two different output lines for increasing and decreasing values of the analog current, respectively. The bidirectional binary counter algebraically counts the voltage pulses, increasing the binary count when up-count pulses are received and decreasing the binary count when downcount pulses are received.

Abstract: A high-speed, high-resolution superconducting counting A/D converter providing greatly increased conversion speeds with a low device count. The superconducting counting A/D converter includes includes a double-junction SQUID quantizer and a bidirectional binary counter having n stages of floating four-junction SQUID flip-flops, where n is the number of bits of accuracy of the counter. The quantizer continuously tracks an analog signal, generating up-count and down-count voltage pulses of the same polarity on two different output lines for increasing and decreasing values of the analog current, respectively. The bidirectional binary counter algebraically counts the voltage pulses, increasing the binary count when up-count pulses are received and decreasing the binary count when down-count pulses are received. Several techniques for reading the contents of the bidirectional binary counter at the end of each sampling interval are also disclosed.

Abstract: Electrodes (6) provided on the inner periphery of a rotary plate (3) are different in number from those provided on the outer periphery. A slide knob (12) moves a contact part (5) along the plane of the rotary plate (3). Thus, the number of electric pulses generated every rotation of the rotary plate (3) when the contact part (5) is in the inner periphery is different from that when the contact part (5) is in the outer periphery.

Abstract: A digital-to-analog converter for use in a timing control loop. The converter includes a plurality of cells, each activated in response to a timing loop control signal. The converter also includes a resistive current mirror, with a first resistance R1, providing a reference curent which is mirrored in each cell by a current source FET. Each cell is constructed to switch the current from its current source FET through an output FET when a respective control bit provided to the cell is positive. Otherwise, the current is diverted through a sink FET. All of the cell output FETs are tied to a single resistance R2 which collects the currents of the active cells and provides the AC output of the converter. The converter's output is related only to the ratio R2/R1, thereby decoupling process, temperature, and voltage effects from the output of the converter.

Abstract: An analog-to-digital converting unit comprises an analog level varying circuit having a plurality of gains and varying a magnitude of an analog input signal for producing a plurality of analog output signals different in magnitude from one another with the respective gains, a plurality of analog-to-digital converting circuits respectively supplied with the analog output signals and producing a plurality of digital code signals, respectively, a controlling circuit supplied with two of the digital code signals and calculating a difference therebetween for producing a first control signal indicative of varying one of the digital code signals in value so as to be equal in value to the other digital code signal, a calculating circuit responsive to the first control signal and causing one of the digital code signals to be varied in value for producing a candidate of a digital output signal, and an output circuit coupled to one of the analog-to-digital converting circuits and to the calculating circuit and supplying

Abstract: This invention relates to a flash-successive approximation analog-to-digital converter combining the low speed, high resolution successive approximation method of conversion with the high speed, low resolution flash method of conversion, which provides the advantages of higher conversion speed with no increased conversion error.

Abstract: A method and apparatus for demodulating biphase-encoded signals is disclosed. A digital phase-locked loop produces a clock signal which is in phase with the clock signal of the biphase-encoded input signal. The clock signal from the phase-locked loop is then used to derive the data signal from the biphase-encoded input signal in a manner which enhances tolerance to edge skewing.

Abstract: A digital to analog signal converter apparatus for converting digital signals to analog signal outputs. The converter apparatus includes a microprocessor, a low pass filter portion for converting a digital output signal from the microprocessor to an analog output signal, and an analog to digital converter portion for sampling and converting the analog output signal to provide a digital input to the microprocessor, permitting control of the analog output signal.

Abstract: A peak-valley detector of an analog signal which provides a digital output of the analog signal. A digital counter is used having an output coupled to a digital-to-analog convertor. The output of the digital-to-analog convertor is compared to an input analog signal. The output of the comparator is used to control the input of a clock signal to the counter. A selective invertor controls whether the comparator's output allows counting for signals above or below the digital-to-analog convertor's output level.

Abstract: To provide for a higher speed operation, lower cost and less complexity in terms of manufacturing, the present invention analog-to-digital converter has feedforwards, from the more significant comparators, to the less significant comparators. As the respective outputs of the comparators change state, the voltage representing that state, for that comparator, is fed to succeeding less significant comparators. With the exception of the most significant comparator whose reference bias voltage remains static, the respective bias voltages of the rest of the successive less significant comparators are shifted, either higher or lower, as the output states of their predecessor comparator(s) change. Consequently, the respective outputs of the comparators correspond, in a binary progressive manner, to a digital word that is representative of the voltage of an input analog signal.

Abstract: To compensate for an offset of an A/D converter, a predetermined reference signal is supplied to the A/D converter. Based on the output signal of the A/D converter, the amount of the offset for this converter is acquired. A multiplexer outputs a compensation signal which serves to cancel out the acquired offset amount, the output of this multiplexer is subjected to analog addition to the analog input signal, and the offset of this A/D converter is compensated for at the input stage.

Abstract: A digital-to-analog converter which includes a digital-to-analog conversion circuit of the current output type, a current-to-voltage conversion circuit receptive of an analog current produced form the digital-to-analog conversion circuit in correspondence to an input digital signal value, for converting the analog current to a voltage and producing it at the output thereof in an output stage of the converter, a first drive circuit for driving the digital-to-analog conversion circuit with constant current, and a second drive circuit which is controlled by the first drive circuit to drive the current-to-voltage conversion circuit with constant current, thereby it being made possible to arrange a plurality of digital-to-analog converters in a simple structure.

Abstract: An analog baseband signal modulates a reference-frequency carrier signal to provide a double-sideband, suppressed-carrier DSB-SC signal. The DSB-SC signal is converted in a voltage-to-frequency converter to a series of pulses, which are demodulated to produce a digitally formatted version of the baseband signal. A notch filter for rejecting an undesired analog signal includes a voltage-to-frequency converter and a selective feedback path which demodulates the undesired signal from a frequency-encoded domain back to the analog domain for a cancellation in a summer preceding the voltage-to-frequency converter.

Abstract: A circuit for converting analog velocity and acceleration signals into digital signals for further digital processing is disclosed. An integration stage using the register accumulation process replaces the charging capacitor used on analog systems and is much more accurate.

Abstract: A SQUID comparator having two junctions configured so that its operating characteristics are substantially the same as a single junction SQUID. In particular, the ratio of the critical current of these two junctions is selected to avoid introduction of hysteresis. An n-bit single pass comparator is present that can produce 4-bit A/D conversion up to 10 GHz. A method is implemented to remove effects of dynamic hysteresis by use complementary comparators.

Abstract: A parallel type A/D converter includes circuitry for generating plural reference voltages, comparators for comparing the plural reference voltages with an input voltage, logic circuits for logically processing the outputs of comparators, and an encoder circuit for encoding the outputs from the logic circuits. A pair of logic outputs are obtained by a first logic circuit chain for receiving as inputs the outputs of a comparator of number i and of a comparator i+2. Conversion errors are reduced by properly processing this pair of logic outputs in a second logic circuit, or by composing an encoder circuit for receiving the pair of logic outputs as inputs.

Abstract: A circuit for automatically matching the gain and offset of a time-shifted digitizing channel in a data acquisition circuit which includes a reference digitizing channel, having a fixed voltage reference, and at least one time-shifted digitizing channel having components that are adjustable for gain and offset. Feedback is provided by examining the dynamic range and average value of a known input signal which is digitized, sent through the time-shifted digitizing channel and stored in memory. A microprocessor reads the stored data and, by separately varying the gain and offset parameters, computes optimal values for each parameter. Digital-to-analog converters (DAC's) allow the microprocessor to communicate with one fixed-gain variable-offset amplifier in the front end and with one fixed-gain variable-offset amplifier and one analog-to-digital converter (ADC) in each time-shifted digitizing channel.