Abstract: An encoder circuit is disclosed wherein a plurality of input signals are parallel-supplied directly to the gates of transistor pairs. Each transistor pair comprises at least two series-connected transistors which are provided between an associated one of output lines and a source of a predetermined potential level (a supply potential or groud potential). The encoding function of the circuit is performed by turning on and off the transistors.

Abstract: A highly accurate, inexpensive digital to analog converter requiring minimal accuracy in component values. A digital word is received serially, the least significant bit first. A voltage is stored on a capacitor at each bit, the value of the voltage being halfway between a reference voltage and the previously stored voltage, the reference voltage value depending on whether the bit is a logic "1" or "0". In each case, the halfway point of the voltage difference is determined by coupling to the midpoint of a pair of resistive components having essentially the same value. The value of the stored voltage represents the analog value of the digital word. The process is preferably repeated for the same word and the two resulting final voltages is averaged to eliminate any effect of a slight difference in component values in a pair.

Abstract: An A/D converter comprises a D/A conversion circuit, a sample-holding circuit which samples and holds the output signal of the D/A conversion circuit, a substraction circuit which performs subtraction for the output signal of the D/A conversion circuit and the output signal of the sample-holding circuit, a subtracting-amplifying circuit which performs subtraction for the output signal of the substraction circuit and the input analog signal and amplifies the result of subtraction, a switch circuit which blocks the input analog signal to the subtracting-amplifying circuit, and an A/D conversion circuit which performs A/D conversion selectively for the input analog signal or the output signal of the subtracting-amplifying circuit.

Abstract: A system is described for correcting errors in a waveform comprising a plurality of binary pulses, each having a different rise time and fall time with respect to the positive going and negative going transitions of each pulse. The system generates a plurality of correction pulses, each synchronously with a corresponding positive going or negative going transition of the binary pulses; and adds each of the correction pulses to the waveform so that the signal area lost by the rise characteristic of the resulting binary pulses will equal the signal area gained by the fall characteristics of the resulting binary pulses.

Abstract: A magnetic rotary encoder which is reduced in overall size and production cost and wherein little torsional force around an axis of a rotary shaft is applied to a bearing for the rotary shaft from a force from an object member for detection and the detection sensitivity does not fluctuate even if the rotary shaft is yielded. The rotary shaft includes a fixed shaft fixedly supported at least at one portion thereof and having an inner race of the bearing secured to an outer periphery thereof, a cylindrical member having an outer race of the bearing secured to an inner periphery thereof, and a magnetic member provided on an outer periphery of the cylindrical member and having magnetic poles formed thereon. A magnetic sensor for detecting a magnetic flux from the magnetic member is supported on the fixed shaft by means of a mounting plate, and a detecting member is mounted in sliding contact with the cylindrical member and rotates, when it is rotated, the magnetic member around the axis of the rotary shaft.

Abstract: A reference voltage is divided by a plurality of resistors (6), the respective voltages and an analogue input voltage being compared with each other by comparators (7). An output of each of the comparators is applied to a data transfer circuit (13) of a hand shake type and latched. The data transfer circuit shifts discontinuous portions of logic which appeared in latched data. Therefore, simultaneous selection of a plurality of addresses in an encoder (10) is avoided.

Abstract: A high speed comparator unit for a flash A/D converter in which a bank of comparator units compare simultaneously an analog input voltage with equally spaced reference voltages, and an encoder ROM produces digital signals based on the comparator unit's outputs. The comparator unit includes a two-stage cascode configuration and a level shifter configuration which effectively reduces the miller-effect of the comparator unit.

Abstract: A successive approximation type A/D converter of the present invention has a capacitor having a predetermined capacitance value and arranged between an input terminal of a voltage comparator and a fixed potential terminal having a predetermined potential. According to the successive approximation type A/D converter of the present invention, the capacitor arranged between the input terminal of the voltage comparator and the fixed potential terminal having the predetermined potential prevents a potential at the input node of the voltage comparator from being greatly changed to exceed a power source voltage range due the influences of a local D/A converter when the sample mode is switched to the approximation mode. Therefore, the leakage of charges stored in the input side of the voltage comparator can be prevented. Accordingly, even if the amplitude of an analog input voltage is equal to the amplitude of the power source voltage, high-precision A/D conversion can still be performed.

Abstract: In a successive approximation analog to digital converter, an analog signal to be converted to a digital signal is held in a local digital to analog converter. The analog signal thus held is sampled dependent on the bit order of the digital signal, and the sampled analog signal is subjected to a successive bit comparison in a first comparator. A successive approximation register controls the local digital to analog converter to perform the sampling of the held analog signal, and holds the results of the successive bit comparison to provide the digital signal. Second and third comparators compare the analog signal and two reference signals, so that the successive bit comparison is performed from the MSB to the LSB where a voltage of the analog signal is between voltages of the two reference signals, while the successive bit comparison is performed from the second significant bit to the LSB where the analog signal voltage is outside a range between the voltages.

Abstract: A cycle-portion encoder, an electronic circuit to dynamically measure the period of a variable electrical input signal and generate an output signal at a preselected time in the next cycle, is provided. The cycle-portion encoder locates a point in time in a recurrent signal's period of interest, based on the real-time measurement of the immediately preceding cycle period and a selected portion of the period of interest. A control output is delivered at the desired phase angle (with respect to the input signal) with a resolution limited only by the counting and gating electronics, and an error primarily related to the repeatability of the input signal from cycle to adjacent cycle.

Abstract: A path memory control method in a Viterbi decoder outputs, when a plurality of decoding steps are required to trace back to a final stage of a surviving path, the same number of decoded data as that of the decoding steps required for trace-back, thereby determining the decoded data. During trace-back, state transition information throughout a plurality of times can be combined with each other, and the final stage of the surviving path can be traced back by jumping back a plurality of stages, at a time, by reducing the number of memory access, thereby realizing high-speed decoding.

Abstract: An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits which has a plurality of resistors connected in a series circuit to a voltage source for establishing respective reference voltages, an upper bit encoder having a first input receiving the analog input voltage and second inputs connected to the series circuit at respective intervals defining groups of the resistor therebetween for generating the m upper bits and a switch control signal, each of the groups including a plurality of the resistors, a first lower bit encoder having a first input receiving the analog input voltage signal and second inputs for generating the n lower bits, a second lower bit encoder having a first input receiving the analog input voltage signal and second inputs for generating the n lower bits, a switch circuit associated with each of the groups of the resistors and responsive to the switch control signal for selectively connecting each of t

Abstract: Method and apparatus for processing compressed, stored analog signals, such as audio signals, from a storage medium, including first converting the signals to digital signals and thereafter expanding the signals.To realize a large volume range in the conversion of compressed recorded signals to expand digital signals, the compressed analog signals picked up from a storage medium are initially analog/digital converted and only then digitally expanded.

Abstract: Employed is a thermometer-code-to-one-of-n converter having a number of similar portions each of which includes gates each configured to detect a zero-zero-one pattern and to develop a one-of-n signal, gates each configured to detect a one-zero-zero pattern (an invalid pattern) and to develop an error signal, gates configured to combine the error signals, and gates configured to gate the error signals with the one-of-n pattern signals to block (inhibit) one-of-n signals.

Abstract: An analog-to-digital converter of the successive-approximation type has a successive-approximation logic circuit for successively generating selection signals defined by significant bits in a digital value, a string of high resistance elements to provide voltage dividers for successively dividing a reference voltage into divided voltages, a switch matrix circuit for generating the divided voltages when activated in response to the selection signals, a comparator for successively comparing an analog level with the divided voltages and for generating comparison signals respectively indicative of the significant bits and an output circuit for generating an output digital signal defined by the significant bits when applied with all the comparison signals, the output circuit being associated with the logic circuit for causing it to generate the selection signals in response to the comparison signals.

Abstract: A current split circuit that includes a multiplying digital to analog converter (DAC) and a controller. The controller establishes a first and second terminal of the DAC at the same potential so that a digital input to the DAC determines the ratio by which a current at a third terminal of the DAC is split between the first and second terminals of the DAC.

Abstract: A digital to analog converter comprises a plurality of resistors coupled in series, having first and second nodes at the repsective ends of the plurality of resistors coupled in series and a plurality of nodes, one each between each of the plurality of resistors. A multiplexing circuit is coupled to the first and second nodes and the plurality of nodes, for selecting the voltage on one of the first and second nodes and the plurality of nodes in response to a digital input signal and providing the result as an analog output signal. An input circuit is coupled to the first and second nodes for adjusting the voltage level at both the first and second nodes in response to the digital input signal, wherein the voltage difference between the first and second nodes remains substantially the same and the current through each of the resistors remains substantially the same.

Abstract: A subranging analog-to-digital (A/D) converter is provided with a calibration mode for linearity correction. In the calibration mode, an up/down calibration counter provides a digital input to a calibration logic circuit and to an estimator digital-to-analog (D/A) converter. The analog output of the estimator D/A converter is provided as an inverted input to a residue operational amplifier, and is combined with a dither noise signal for input to a sample-and-hold circuit. The output of the sample-and-hold circuit is provided to a noninverting input of the residue operational amplifier. The operational amplifier provides an analog residue signal to a residue A/D converter that generates a digital residue signal for input to the calibration logic circuit. The calibration logic circuit calculates and stores a linearity correction table based on the average step size computed from the inputs to the calibration logic circuit for each step of the up/down counter.

Abstract: An approach to A/D converter architecture is based on a "pipelined and submerged" architecture which includes a pipeline of elemental stages (10.sub.i). Each stage of the pipeline comprises a low-resolution flash A/D subconverter (12), a D/A converter (14), and a unity-gain buffer (16). To minimize converter nonlinearity due to component mismatches, a self calibration technique based on an "interpolation" scheme is used. This technique employs an on-chip delta-sigma A/D converter (32) to provide the reference for calibration and a 100-bit memory (50) to store nonlinearity information. Long term drift is corrected by a calibrator (34) in parallel with data conversion.

Abstract: A pipelined analog-to-digital converter architecture comprises three pipeline stages wherein the first stage includes a low-resolution flash A/D subconverter (10), two sample-and-hold amplifiers (12 and 14), two D/A converters (16 and 18), and two unity-gain buffers (20 and 22). Parallel-autozero analog processing is accomplished by alternately passing the analog signal through one or the other of two parallel processing channels. The sampled analog signal is delivered to the flash A/D subconverter and the D/A converters simultaneously. The residue from the D/A converters is delivered to the second stage, passing through a flash A/D subconverter (24), an additional D/A converter (26), and alternately through two comparators (28 and 30) each having a gain of eight. The second stage produces and delivers its residual voltage to the final pipeline stage comprising a flash A/D subconverter (32).