Abstract: A computer software-related device and method uses regression testing techniques for testing computer hardware and/or software application(s). Input data and commands from a user are stored, and are sent to a hardware/software system under test. Signatures (representative of visual display data) which are received (with a selected prevalence) as a result of the sent input data and commands are also stored. On command of a user, the stored signatures, input data and commands are subsequently sent to the hardware/software system under test, and new signatures are generated. These new signatures are compared with the stored signatures, and the results of this comparison are used as an indication that the hardware/software system under test is performing as expected.

Abstract: An apparatus for decoding a received BCH code signal for correcting a combined complex error is disclosed which includes a syndrome generating circuit for generating two n-bit syndromes corresponding to the received signal, a syndrome converting circuit for converting the two n-bit syndromes to a 2n-bit syndrome, a random error correcting circuit, a burst error correcting circuit, two combining circuits and output selecting circuit. The random error correcting circuit receives input as the two n-bit syndromes and outputs a random error correction signal to one of the combining circuits and the burst error correcting circuit receives as input the 2n-bit syndrome and outputs a burst error correction signal to the other of the combining circuits. The combining circuits combine the correction signals with the received BCH code signal.

Abstract: An error correction circuit is provided which uses NMOS and PMOS synapses to form network type responses to a coded multi-bit input. Use of MOS technology logic in error correction circuits allows such devices to be easily interfaced with other like technology circuits without the need to use distinct interface logic as with conventional error correction circuitry.

Abstract: The system comprises a pair of error checking processors connected in a master/slave configuration such that the slave receives inputs and outputs of the master, mimics operation of the master based on the inputs to produce mimicked outputs, compares the mimicked outputs with the master outputs and indicates an error condition if the mimicked outputs do not equal the master outputs. A checking circuit forces a difference between the mimicked output and the master output and determines if the master slave configuration accurately determines the presence of the forced error.

Abstract: There is provided an error correcting device for correcting errors of a received message in accordance with a processing program including a plurality of error correcting processes for correcting different numbers of errors, wherein a plurality of check codes which are used to discriminate the shift to either one of the plurality of error correcting processes for correcting different numbers of errors and which are formed by syndromes formed from the reception code are sequentially serially generated, the plurality of check codes are output in parallel and the shift of the process in the processing program is executed in accordance with the check codes which were output in parallel.

Abstract: A system and method is provided for testing a computer system main memory during system startup. An initial block of memory is tested and marked as valid or invalid during a startup sequence, with the remaining system memory initially marked as bad. An operating system and applications can be loaded into the initial block and operate normally, and a concurrent process is invoked to test the remaining system memory. This allows the remaining system memory to be tested and marked as valid during normal system operation.

Abstract: The invention relates to data generators producing output signals representative of data and in compliance with a predetermined telecommunications standard. A generator of the invention comprises a memory device programmed with data which produces signals representing control bits for controlling the configuration of output data, e.g. frame and multiframe synchronization signals, and additional signals which control a sequence generator producing a sequence of data to be inserted in the data pattern. Operation is completely programmable and may be adapted to numerous different telecommunications standards. The invention is applicable to testing telecommunications networks.

Abstract: A data transfer checking system includes a unit for writing a checking data pattern which is not identical with the data to be written in the same memory area; a unit for writing the data over the checking data pattern; and a unit for checking the memory area to see if there remains the checking data pattern, thereby providing high speed, low cost checking of the initial microprogram loading or data write conditions in an electronic computer system.

Abstract: Software simulators of logic design circuits run slowly but are capable of providing very finely detailed error trace analyses. On the other hand, hardware accelerators operating to perform similar functions are very fast in their execution but are not capable of practically isolating error states or other critical conditions. Accordingly, the present invention provides an interactive system combining software simulators and hardware accelerators so that when desired test results do not favorably compare with simulated results, a mechanism is provided for storing the current hardware accelerator state and restoring the accelerator to a previous checkpoint state which has been saved as a result of a prior periodic interruption. The hardware accelerator is then operated for a time sufficient to bring it up to a state that occurs just before the detected miscomparison. At this point, state information from the hardware accelerator is supplied to a software simulator for detailed error analysis and fault tracing.

Abstract: The data storage subsystem of the present invention uses a large plurality of small form factor disk drives to implement an inexpensive, high performance, high reliability disk drive memory that emulates the format and capability of large form factor disk drives. The data transmitted by the associated computer system is used to generate redundancy information which is written with the data across N+M disk drives in a redundancy group in the data storage subsystem. To clear the redundancy accumulator memory, an associated pointer memory is used to indicate the ones of the redundancy accumulator memory byte positions that were used in the previous redundancy calculation. As data is received from the computer system, the pointer memory is checked to determine whether this next byte position need be reset to erase the previously stored redundancy calculation residue. If not, the data is simply stored therein.

Abstract: A video signal processing circuit carries out error correction, error concealment and weighted mean processing sequentially on video signals reproduced by a video tape recorder. One and two dimensional error concealment modes are provided respectively utilizing sample data on the same line as erroneous sample data to be concealed, and sample data in peripheral and/or time displaced relation to the erroneous sample data. One of a plurality of error concealment modes is selected depending upon the state of error flags for the peripheral and/or time displaced sample data. In certain advantageous embodiments, original sample data for which a gray code has been set, is compared with error concealed data and the original sample data is output in place of the error concealed data where such comparison indicates that the difference between the two is within a predetermined acceptance threshold.

Abstract: The framing bit errors of a received digital communications signal are monitored and recorded. The framing bit error rate is determined and an audible alarm is sounded when the error rate exceeds a predetermined threshold value in a plurality of calculation modes. The framing bit error rate and the total framing bit errors detected over a predetermined fixed time period is also displayed. A link to a remote network monitor can be implemented for monitoring and displaying framing bit error rate at a remote location.

Abstract: Message Segments comprising Messages are stored in a flat file on disk. A unique Message Number is assigned to each Message and each Message Segment is stored at a flat file address (Segment Descriptor) in a record containing the Message Segment data and recovery information. the Recovery Information includes fields for an Available Marker, Message Number, Segment Sequence Number, Final Flag and Last Address. The Available Marker denotes whether the Message Segment is in-use or available. The Message Number field contains the Message Number identifying the Message which contains the Segment. The Segment Sequence Number donotes the order in a Message occupied by the Segment. The Final Flag field contains a flag if the Messge Segment is the Last Segment of the Message. The Last Address field contains the Segment Descriptor of the Last Message Segment of the Message containing the Segment. A data base for accessing the Message Segments is maintained on disk.

Abstract: A system for testing a RAM array bus transaction buffer without halting system operation or using a special protocol, including a RAM control selection circuit for providing to the RAM either a set of normal control, data and address signals or diagnostic control, data and address signals; a Diagnostics Mode Bit Register (DMBR); a Diagnostics Address Register (DAR); and means for recognizing instructions to write to those registers or to a fictitious Diagnostics Data Register (DDR). First a normal write operation is executed to the DMBR, to control a RAM control selection circuit. The RAM control selection circuit chooses as RAM control signal sources a set of diagnostic sources rather than normal system sources. Second, a selected RAM address is written to the DAR. Third, a write operation is performed to the DDR, causing the selected data to be written to the RAM at the address specified by the DAR. Data is similarly read from the RAM through the DDR.

Abstract: An integrated circuit having boundary-scan facilities in accordance with IEEE Standard 1149.1, has its boundary scan chain configured to permit fault insertion testing of diagnostic and maintenance software. Each Scan cell includes storage devices for storing a pair of bits of a binary vector shifted into the boundary scan chain. One bit comprises faulty data and the other bit serves to control application of the faulty data by the scan cell. A system incorporating such integrated circuits includes a controller for controlling the IEEE test interface to shift the binary vector into the boundary scan chain, and diagnostic and maintenance software for diagnosing the faults introduced into the integrated circuits.

Abstract: A memory system containing groups of random access memory (RAM) devices further includes apparatus for distributing input memory addresses so diffused so as to cause the selection of different relative physical cell locations within each RAM device being accessed to provide a single word of information.

Abstract: The parallel disk drive array data storage subsystem maps between virtual and physical data storage devices and schedules the writing of data to these devices. The data storage subsytem functions as a conventional large form factor disk drive memory, using an array of redundancy groups, each containing N+M disk drives. A performance improvement is obtained by eliminating redundancy data updates in the redundancy group by writing modified virtual track instances into previously emptied logical tracks and marking the data contained in the previous virtual track instance location as invalid. Logical cylinders containing a mixture of valid and invalid virtual tracks are emptied by writing all the valid virtual tracks into a previously emptied logical cylinder as a background process.

Abstract: A system provides for the testing of components which connect to one or more of programmable logic devices (PLDs), each of which is organized in a predetermined manner. Each PLD includes a plurality of programmable logic sections, each of which connect to I/O pins through driver and receiver circuits. An available section includes programmed means for causing its driver circuit to force the I/O pin to a first logic level when made operational. The other sections each include programmed means for connecting their associated driver circuits to be controlled by signals applied to the receiver circuit of the available section. During testing, means are externally applied to the I/O pin of the available section which drive the pin from the first logic level to a second logic level.

Abstract: A method and apparatus for reporting faults on a control line running through a plurality of processors to a control processor. Each processor having a failure provides a unique address onto the control line. The addresses are then sequentially shifted through each of the processors having a failure to the control processor.

Abstract: An expandable memory structure, both vertically and laterally, which uses a plurality of uniformly sized and duplicated chips which includes parity check functionality using an auxiliary parity memory chip of the same type and size. Selection circuitry permits choice of format for odd or even parity.