Abstract: In memory devices, and particularly in dynamic random access memory devices that use boosted word lines, voltage leakage in word lines and transfer gates to memory cells cause data error. A circuit, device, and method to detect voltage leakage is disclosed. The test circuit includes a sample and hold circuit that is connected to the word line of an addressed memory cell to store the voltage level on the word lines as it charges. A comparator is connected to compare the stored voltage level with the voltage level on the word line after it is charged and to indicate if the voltage level of the word line falls below a predetermined amount. The circuit can detect a voltage differential as small as 50 millivolts for a high resistance short as large as 2 megaohms in about 200 nanoseconds. The circuit can be incorporated into a random access memory device thereby significantly increasing the speed at which all memory cells and word lines can be tested.

Abstract: Troubleshooting expert systems are generally embodied in software for the purpose of solving difficult problems in some narrow domain of expertise. The prior art describes certain mechanics for developing or generating rules. That process is commonly known as the knowledge acquisition process. Having acquired the knowledge, our new troubleshooting arrangement eliminates the prior art separation between the expert system knowledge acquisition process and the expert system utilization process. Our new arrangement also detects and classifies invalid actions or other errors of the user in a manner that allows for the non-human expert system to advise the human user. Our arrangement interactively communicates between a user and a troubleshooting system, generates a learning knowledge base, identifies an object being tested by the user, utilizes the learning knowledge base for troubleshooting the test object, and classifies the test object as faulty or not faulty.

Abstract: A diagnostic system coupled to a programmable logic controller (PLC) via a serial data link monitors the operation of apparatus under the control of the PLC. Upon detection of a first event-initiating signal, a central processor unit (CPU) in the diagnostic system initiates a timer. The CPU then awaits receipt of a second confirming action signal representing completion of the event initiated by the first signal. The timer times out after a predetermined time interval determined by an operation parameter of the controlled apparatus. If the second confirming action signal is not received before the timer times out, the CPU provides an alarm signal to a video display such as a cathode ray tube (CRT) for displaying an alarm message.

Abstract: Self-testing of a read only memory (10') containing an m.times.n+1 array of single-bit storage cells (12') is accomplished by first loading the bits of a preselected quotient string into the n+0 column of the memory. The quotient string is typically preselected to yield an all-zero residue if no errors are present. Thereafter, a first polynomial division is performed on the entire contents of the memory by sequentially shifting out of the bits in the cells in each successive ROM row in a right-to-left direction into a separate one of the n+1 inputs of a bidirectional multiple input shift register (18'). A second polynomial division is then performed on the m.times.n contents of the memory (10') by sequentially shifting the bits out of each successive row into the shift register (18') in a left-to-right direction.

Abstract: Errors in a predetermined digital sequence are detected by utilizing a detector which includes memory elements such as a series shift register, and logic gates for detecting a predetermined subsequence. Errors are detected by comparing each bit in the data stream with the output of the memory. Logic gates inhibit the detection of an error in response to the subsequence detection.