Patents Examined by Henry Tsai
  • Patent number: 11030130
    Abstract: A storage device including a memory array and a peripheral logic circuit is provided. The memory array includes a plurality of banks and a data path. The peripheral logic circuit operates in a copy mode or a normal mode according to a mode-switch command. In the copy mode, the peripheral logic circuit directs a first bank to provide specific data to the data path and directs a second bank to receive specific data from the data path.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: June 8, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Chih-Wei Liang
  • Patent number: 11030129
    Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ramdas P. Kachare, Zvi Guz, Son T. Pham, Anahita Shayesteh, Xuebin Yao, Oscar Prem Pinto
  • Patent number: 11029749
    Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). At least one of the ASICs is configured to process incoming data packets and outgoing data packets. At least one of the ASICs is configured to move data between a respective networking module and a destination networking module. The system also includes a cable backplane having a number of parallel cables configured to transmit data between the number of ASICs.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 8, 2021
    Assignee: Platina Systems Corp.
    Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Mark Tehmin Yin
  • Patent number: 11023344
    Abstract: A data processing system includes a monitoring system, the monitoring system includes a processor and a data analysis block. The processor executes a monitoring application for monitoring an operation of a monitored system coupled to the monitoring system. When assistance is needed from the monitored system, the processor has an output coupled to the monitored system for providing an assistance request. When the assistance request is sent to the monitored system, the processor also sends a disturbance indication to the data analysis block. The disturbance indication indicates that the output data from the monitored system may be disturbed by the assistance request. The data analysis block can then take an action to reduce the effect the disturbance may have on the analysis results. A method for monitoring the monitored system is also provided.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 1, 2021
    Assignee: NXP B.V.
    Inventor: Jan Hoogerbrugge
  • Patent number: 11023007
    Abstract: Methods, structures, and apparatus that are able to detect the presence of a connection to a contact of an electronic device and are also able to detect the presence of moisture at the contact.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 1, 2021
    Assignee: Apple Inc.
    Inventors: Brandon J. Beckham, Gabriel Sanchez Barba, Isikcan Yilmaz
  • Patent number: 11023008
    Abstract: A hybrid docking station determines whether native video data exists and can be passed through to a video port or whether a virtual video processor should be activated to provide virtual video data to a video port. For example, a laptop is connected to a hybrid docking station using a USB™ 3.0 connection. The hybrid docking station recognizes that the USB™ 3.0 connection includes a native video data and passes the native video data to a DisplayPort™. By avoiding activating a virtualized video processor and using native video data, the laptop avoids installing software to communicate with the virtualized video processor and communicates with one or more displays using a native video channel. By avoiding installing software, it simplifies IT's and user's usage and experience with universal docking station.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: June 1, 2021
    Assignee: TARGUS INTERNATIONAL LLC
    Inventors: Ronald DeCamp, Dan Tsang
  • Patent number: 11023406
    Abstract: Information maintained in a port control block of an embedded port of a host bus adapter is stored in a host bus adapter memory, wherein the information corresponds to login attributes and state data of remote ports. In response to storing the information in the host bus adapter memory, code in the embedded port is updated. In response to the updating of the code in the embedded port, the stored information is restored from the host bus adapter memory to the port control block of the embedded port.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger G. Hathorn, Steven E. Klein, Mikel W. Welsh
  • Patent number: 11023410
    Abstract: A system is described that performs memory access operations. The system includes a processor in a first node, a memory in a second node, a communication interconnect coupled to the processor and the memory, and an interconnect controller in the first node coupled between the processor and the communication interconnect. Upon executing a multi-line memory access instruction, the processor prepares a memory access operation for accessing, in the memory, a block of data including at least some of each of at least two lines of data. The processor then causes the interconnect controller to use a single remote direct memory access memory transfer to perform the memory access operation for the block of data via the communication interconnect.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 1, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: David A. Roberts, Shenghsun Cho
  • Patent number: 11023258
    Abstract: Dynamically configurable server platforms and associated apparatus and methods. A server platform including a plurality of CPUs installed in respective sockets may be dynamically configured as multiple single-socket servers and as a multi-socket server. The CPUs are connected to a platform manager component comprising an SoC including one or more processors and an embedded FPGA. Following a platform reset, an FPGA image is loaded, dynamically configuring functional blocks and interfaces on the platform manager. The platform manager also includes pre-defined functional blocks and interfaces. During platform initialization the dynamically-configured functional blocks and interfaces are used to initialize the server platform, while both the pre-defined and dynamically-configured functional blocks and interfaces are used to support run-time operations.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Neeraj S. Upasani, Jeanne Guillory, Wojciech Powiertowski, Sergiu D Ghetie, Mohan J. Kumar, Murugasamy K. Nachimuthu
  • Patent number: 11023392
    Abstract: Access to a memory shared between a first interface and a second interface is arbitrated. Following a request to access the memory emanating from the second interface, while current access to the memory is granted to the first interface, a count is triggered having a maximum count time. A access to the memory is authorized for the second interface at the end of occupation of the access granted to the first interface if the end of occupation finishes before the end of the maximum count time, or otherwise at the end of the maximum count time.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: June 1, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jean-Louis Labyre
  • Patent number: 11023397
    Abstract: The present disclosure provides a system for monitoring I/O traffic. The system includes a memory storing information, a device, and a translation lookaside buffer (TLB). The device is configured to send a request for accessing information from the memory. The TLB includes a counter register file having counter registers, and entries having corresponding counter ID fields. The TLB is configured to receive a source identifier of the device and a virtual address associated with the request from the device, select an entry of the entries using the source identifier and the virtual address, select a counter register from the counter registers in accordance with information stored in the counter ID field of the selected entry, and update a value of the selected counter register in accordance with data transferred in association with the request.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: June 1, 2021
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Jian Chen, Li Zhao, Ying Zhang
  • Patent number: 11022708
    Abstract: A docking station for receiving different types of seismic nodes, the docking station including a frame; a control module attached to the frame plural docking modules attached to the frame, wherein each docking module includes plural docking bays; a monitor attached to the frame and configured to display information about the plural docking modules; and a network connection device attached to the frame and configured to provide data transfer capabilities for each docking bay of the plural docking bays. The plural docking bays are configured to accept interchangeable ports that are compatible with the different types of seismic nodes.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: June 1, 2021
    Assignee: SERCEL
    Inventors: Cyrille Bernard, Mathieu Sanche
  • Patent number: 11016781
    Abstract: Some example embodiments presented herein provide methods and memory modules for configuring vendor-specific registers in the memory modules to enable and/or disable vendor-specific functionality. The vendor-specific register space may be organized by a vendor-specific logic and accessed by a standard memory access command received while the memory is in a programming mode. A write command may be received from a host device to switch the memory module to a programming mode, and the memory module may be switched to the programming mode responsive to the command. A memory write command may be received from the host device involving the memory module switched to the programming mode, and a vendor-specific register may be configured based on the memory write command and the organization of the vendor-specific register indicated by the vendor-specific logic.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eldho Pathiyakkara Thombra Mathew, Yash Jajoo, Jai Babu Mahankud, Hari Babu Chimakurthy
  • Patent number: 11016790
    Abstract: State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Brian Lewis Brown
  • Patent number: 11016920
    Abstract: Aspects of the embodiments are directed to calibrating a cross-talk cancellation module. A data eye response for a first data channel can be acquired, and the left-side and right-side maximum transition edges can be determined while adjacent data channels are silent. The adjacent data channels can be activated, first using an even mode waveform. A strobe can be positioned at the left-side maximum boundary in anticipation of a right-shift due to even mode waveform cross talk. A summer circuit can sum the waveform from the first data channel with cross-talk induced voltage pulse having an opposite polarity from the even mode waveforms on the aggressor channels. A left-side edge can be determined by incrementally adjusting gain and detector parameters. These parameters can be locked once a left-side transition edge is located. The process can be repeated for a right-side transition edge with odd-mode aggressor waveforms.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Chenchu Punnarao Bandi, Amit Kumar Srivastava
  • Patent number: 11010327
    Abstract: Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 18, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Sharon Graif, Meital Zangvil, Lior Amarilio
  • Patent number: 11010318
    Abstract: Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct memory access engine by a second direct memory access engine to the data processing device via the second direct memory access engine is disclosed.
    Type: Grant
    Filed: May 14, 2016
    Date of Patent: May 18, 2021
    Assignee: CAVIUM INTERNATIONAL
    Inventors: Jason Daniel Zebchuk, Gregg Alan Bouchard, Tejas Maheshbhai Bhatt, Hong Jik Kim, Ahmed Shahid
  • Patent number: 11010313
    Abstract: A method, apparatus, and system for an architecture for machine learning acceleration is presented. An apparatus includes a plurality of processing elements, each including a tightly-coupled memory, and a memory system coupled to the processing elements. A global synchronization manager is coupled to the plurality of the processing elements and to the memory system. The processing elements do not implement a coherency protocol with respect to the memory system. The processing elements implement direct memory access with respect to the memory system, and the global synchronization manager is configured to synchronize operations of the plurality of processing elements through the TCMs.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 18, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Colin Beaton Verrilli, Natarajan Vaidhyanathan, Rexford Alan Hill
  • Patent number: 11010325
    Abstract: An adapter includes a first coupling component and a second coupling component to establish bidirectional communications between two processing devices by passing data signals through a memory card slot on one of the devices. The adapter includes a first coupling interface configured to couple with the memory card slot on a first one of the two processing devices and further includes a second coupling interface configured to couple with a second processing device. The second coupling interface is of a different form factor than the first coupling interface.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 18, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Adam Nelson Swett, Vlad Radu Calugaru
  • Patent number: 11003616
    Abstract: In a computer comprising a plurality of integrated circuits (ICs), each IC may be connected to all other ICs via a respective point-to-point interconnect. A source IC divides the data to be transmitted to a destination IC for a transaction to generate multiple data cells so that each data cell includes a different portion of the data. The source IC transmits one of the data cells to the destination IC and remaining data cells to intermediate ICs, wherein an intermediate IC is an IC other than the source IC or the destination IC. The intermediate ICs forward the remaining data cells to the destination IC.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 11, 2021
    Assignee: Amazon Technologies, Inc
    Inventors: Guy Nakibly, Adi Habusha, Yaniv Shapira, Daniel Joseph Grey