Abstract: An image processing apparatus that is capable of extending a function while guaranteeing performance and quality. The image processing apparatus has a USB host controller. A first USB host interface is installed inside the image processing apparatus. A storage unit stores device information about a USB storage device that can be used as a system storage device of the image processing apparatus. A memory device stores a set of instructions. A processor executes the set of instructions to obtain individual identification information about a USB storage device from the USB storage device in a case where the USB storage device is connected to the first USB host interface, and control to achieve a state where the USB storage device is available as the system storage device of the image processing apparatus in a case where the individual identification information is in the device information.

Abstract: The present disclosure provides a control method applied to an electronic device. The electronic device includes a first human-machine interaction area and a second human-machine interaction area, the first human-machine interaction area and the second human-machine interaction area being movable relative to each other.

Abstract: A convolutional accelerator framework (CAF) has a plurality of processing circuits including one or more convolution accelerators, a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, and a stream switch coupled to the plurality of processing circuits. The reconfigurable hardware buffer has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch. The control circuitry of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.

Abstract: An electronic device is provided. The electronic device includes a first power management integrated circuit (PMIC) with a first fault controller connected to a first node and a first interface circuit connected to a second node; a second PMIC with a second fault controller connected to the first node and a second interface circuit connected to the second node; and a third PMIC with a third fault controller connected to the first node and a third interface circuit connected to the second node. The first fault controller is configured to, during a power on sequence or a power off sequence, detect a change in a voltage level of the first node. The first interface circuit is configured to communicate with any one or any combination of the second interface circuit and communication and the third interface circuit based on the change in the voltage level of the first node.

Abstract: The present invention discloses a communication method having both defined and undefined bus communication mechanism used in an electronic that includes steps outlined below. A connection between an application program and the peripheral electronic equipment is established through a built-in driver. A proxy library and a proxy driver respectively corresponding to a user mode and a kernel mode are activated by the application program. A connection between a combination of the proxy library and the proxy driver and the peripheral electronic equipment are established by the application program. Defined commands defined by the built-in driver are transmitted to and received from the peripheral electronic equipment through a bus by the application program by using the built-in driver. Non-defined commands not defined by the built-in driver are transmitted to and received from the peripheral electronic equipment through the bus by the application program by using the proxy library and the proxy driver.

Abstract: Techniques are provided for asynchronous reservation of storage volumes in a storage system with persistent storage of reservation data. One method comprises obtaining, by a target storage device, a reservation command from a host device that requests to reserve a storage volume of the target storage device; creating a new execution thread to process the reservation command, wherein an execution of the reservation command is asynchronous; storing an intermediate result of the reservation command in a persistent storage, wherein the stored intermediate result allows the execution of the reservation command to restart from an execution point following the storage of the intermediate result; and initiating a notification to the host device of the reservation of the storage volume in response to a completion of the execution of the reservation command.

Abstract: A data processing method includes receiving, by a virtual machine, an I/O access request. The I/O access request is used to access data, the I/O access request includes a type of hardware data used to indicate a working status of a virtual I/O device, and the virtual I/O device is obtained after the I/O device is virtualized. The method also includes identifying, by the virtual machine, that the type of the hardware data in the I/O access request is first-type data. The first-type data is hardware data of the virtual I/O device that remains unchanged in a data processing process. The method further includes obtaining, by the virtual machine, to-be-accessed data from a first memory space. The first memory space is memory storage space in the data processing system.

Abstract: A flexibly configured multi-computing-node server mainboard structure and a method. A processing unit connects to PCIE devices via I2C concurrently. The processing unit analyzes whether the acquired data of the PCIE devices are abnormal. The processing unit connects to a baseboard management controller via I2C, when the data are normal, the processing unit polls to transmit analyzed data to the baseboard management controller via I2C. When the data are abnormal, the processing unit pauses polling and transmitting information, and preferentially transmits abnormality information to the baseboard management controller. The processing unit is provided with an internal clock assembly and an external clock assembly, the external clock assembly is connected to a PCH, the internal clock assembly and the external clock module are connected to a data selector, and an output of the data selector is electrically connected to the PCIE devices.

Abstract: A wheel information transfer apparatus, including: an information detection apparatus to detect and store wheel-related information; and an information transfer apparatus to transfer the wheel-related information over a transfer medium; in which the information transfer apparatus is configured to transfer at least a first portion of the wheel-related information parallel or quasi-parallel, and in which the information transfer apparatus is configured to transfer the at least first portion of the wheel-related information or a second portion of the wheel-related information serially within the parallel or quasi-parallel data transfer. Also described are a wheel information transfer method and a related vehicle.

Abstract: A smart card management device and a smart card management method are provided, the smart card management device includes: a main controller, a serial peripheral interface control module, and a plurality of card slot control modules; the master controller is configured to obtain a smart card access request and send the smart card access request to the serial peripheral interface control module; the serial peripheral interface control module is configured to send the smart card access request to a corresponding card slot control module according to the card slot identifier; the card slot control module is configured to access a corresponding smart card according to the smart card identifier, obtain an execution result of the smart card, and store the execution result to facilitate the master controller to read the execution result by polling. This device can process a plurality of smart cards in parallel.

Abstract: A probabilistic scheme that uses temperature to reload an LFSR at runtime introduces randomness to prevent row hammer attacks. In one example, a memory controller includes input/output (I/O) interface circuitry to receive memory access requests from a processor. A linear feedback shift register (LFSR) in the memory controller is shifted in response to receipt of a memory access request to a target address. The shift register is compared a value in the LFSR with a pre-determined value. If the value in the LFSR is equal to the predetermined value, a refresh is triggered to one or more neighboring addresses of the target address. The LFSR is reloaded with one of multiple seeds based on a temperature (for example, from an on-die thermal sensor, a DIMM sensor, and/or other temperature). Selecting one of multiple seeds based on temperature on the fly makes the scheme unpredictable and robust against row hammer.

Abstract: Provided are a data transmission control method and device and a non-transitory computer-readable medium. The data transmission control method includes: determining a multiple and a remainder according to a total data size of to-be-transmitted data and a set byte size, where the multiple is equal to a quotient obtained by dividing the total data size by the set byte size, and the remainder is equal to a remainder obtained by dividing the total data size by the set byte size; sequentially transmitting data whose size is the set byte size multiplied by the multiple in the to-be-transmitted data by transmitting data of the set byte size each time; and in response to the remainder being not zero, transmitting remaining data whose size is the remainder in the to-be-transmitted data.

Abstract: Provided are a method for processing data, an electronic device and a storage medium, which relate to the field of deep learning and data processing. The method may include: multiple target operators of a target model are acquired; the multiple target operators are divided into at least one operator group, according to an operation sequence of each of the multiple target operators in the target model, wherein at least one target operator in each of the at least one operator group is operated by the same processor and is operated within the same target operation period; and the at least one operator group is output.

Abstract: A processor for a cryptosystem. The processor comprises a hybrid processor architecture including a hardware processor, a software processor and an interconnection interface arranged to exchange data between the hardware processor and the software processor; wherein the hardware processor comprises a plurality of hardware accelerator modules arranged to perform computational tasks including at least one of number theoretic transforms (NTT) computation, arithmetic operations which are more time-consuming when being performed instead by the software-processor.

Abstract: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.

Abstract: Methods for USB signal communication over an optical link are described. One aspect includes detecting connection of a device circuit to a USB device. The detecting may further include transmitting an electrical pulse through a reactive network, and detecting a change in a delay associated with the electrical pulse responsive to connecting the device circuit to the USB device. An optical signal associated with the detected connection may be transmitted to a host circuit via an optical communication channel.

Abstract: A PCIe resource management system includes a PCIe resource registration subsystem and a PCIe resource monitoring subsystem. Assets register to use PCIe resources of other assets and to allow other assets to use their PCIe resources. Assets specify which types of PCIe resources it can borrow, when it can borrow those PCIe resources, and a logical group of other assets from which the asset can borrow the PCIe resources. Assets also specify which types of PCIe resources it will lend, when it will lend those PCIe resources, and a logical group of other assets to which the asset will lend the PCIe resources. The PCIe resource registration subsystem maintains a PCIe resource registration datastore maintaining PCIe borrow and lending rules associated with assets in logical groups of assets. PCIe resources are shared between assets in the logical groups as needed, as determined by the PCIe resource monitoring subsystem.

Abstract: Disclosed are a multi-mode virtual serial port chip, an implementation method, and a firmware downloading system and method thereof. The multi-mode virtual serial port chip comprises a normal operating mode and an enhanced operating mode, which are selected by a multiplexed auxiliary signal pin according to that whether there is a pull-down resistor connected thereto. The normal operating mode is compatible with the prior art and applications, and one-click automatic MCU firmware downloading can also be realized in the enhanced operating mode. In the present invention, no peripheral circuit is needed, the MCU also cannot unintentionally enter other modes, and the effects of automatically downloading firmware, improving downloading efficiency, reducing costs, reducing power consumption and decreasing product volume are achieved.

Abstract: System including at least one processor in communication with first and second port interfaces and one or more non-transitory computer-readable media. The first port interface may include a first communication port, and the second port interface may include a second communication port. The at least one processor is operative with the computer-readable program code to perform operations including setting the first and second port interfaces to passthrough mode by connecting the first port interface with the second port interface.