Abstract: An overlap detection unit for a user station of a serial bus system. The overlap detection unit includes a collision detection block for detecting bus states on a bus of the bus system, in which, in order to transmit a message, bus states of user stations of the bus system are generated on the bus with a first physical layer in a first communication phase, and are generated with a second physical layer in a second communication phase, the second physical layer being different from the first physical layer. The collision detection block generates a signal whose value indicates whether or not the bus states in the second communication phase have a level that corresponds to an overlap of the first and second physical layers or an overlap of two second physical layers, and the collision detection block is designed to output the signal for the user station.

Abstract: A cable includes a first plug, a second plug, and a controller. The first plug is configured to be connected with a host. The second plug is configured to be connected with a device. The controller is coupled between the first plug and the second plug, and is configured to monitor a connection message transferred between the host and the device, and to determine, according to the connection message, a transfer mode that the host and the device is to enter, and to set a plurality of electrical parameters to be a corresponding one set in a plurality of sets of predetermined parameters.

Abstract: A system for communication between BMSs of a battery pack including a plurality of BMSs connected to a parallel communication network, and a plurality of slave BMSs allocated with different communication identifiers, each having a variable field; and a master BMS for allocating a communication identifier to each of the plurality of slave BMSs through the parallel communication network, changing a priority determination value allocated to the variable field according to a predetermined condition, and performing communication with the plurality of slave BMSs based on the communication identifier.

Abstract: Disclosed is an industrial control device including a point-to-point backplane/point module architecture providing RIUP (Removal and Insertion Under Power) functionality where data communications between modules is maintained after the removal of a point module from the backplane. According to an exemplary embodiment, a backplane includes a plurality of passive mechanical bypass switches controlled by the insertion and removal of respective point modules, whereby data communicated bypass a removed point module interface and point-to-point data communications are provided to an inserted point module after an initial routine is executed by a microcontroller associated with the inserted point module.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a secure area and a non-secure area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a secure mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: An eyewear device that includes a plurality of SoCs that share processing workload, and a USB port configured to perform low-power debugging and automation of the plurality of SoCs, such as using either a Universal Asynchronous Receiver-Transmitter (UART) or a Serial Wire Debug (SWD). The eyewear includes a USB hub configured such that the USB port can simultaneously communicate with the plurality of SoCs. The USB hub can be shut down to disable the USB hub, and all the SoCs can enter their low-power modes without being kept awake by a persistent USB connection. The eyewear includes a first switch and a control logic, wherein the control logic controls the first switch and enables the USB port to perform low-power debugging and automation of the SoCs. The eyewear further includes a second switch, wherein the control logic controls the second switch to enable the USB port to perform low-power debugging and automation of the SoCs via a processor, or to enable the USB port to control each of the SoCs.

Abstract: A position-sensing method and device for sensing the installation location (F1, . . . , Fi) of slave units (SE1, . . . , SEi) in an operating region (A1, . . . , Ai) of a system (A) comprising a number i of adjacent operating regions (A1, . . . , Ai) each having a slave unit, wherein the individual slave units (SE1, SEi) have a changeable operating function for achieving or changing the physical state in the operating region in question of the system, and wherein a respective sensor (S1, . . . , Si) is provided in each operating region in question in order to sense a measurement variable (T) proportional to the physical state in the operating region in question and an evaluating device is provided in order to determine, upon the activation or changing of the operating function of at least one slave unit (SE1, . . . , SEi), the installation location (F1, . . . , Fi) of said slave unit from the change in the measurement variables (T) over time.

Abstract: A charging system includes a source terminal and a sink terminal. The control method of the charging system includes transmitting a bus voltage by the source terminal, determining whether the sink terminal has entered a sink attached state when the sink terminal receives the bus voltage, enabling a message transceiver of the sink terminal if the sink terminal has entered the sink attached state, transmitting a source message to the transceiver of the sink terminal by the source terminal, transmitting a request message to the source terminal by the message transceiver of the sink terminal while the source terminal transmits the source message, and continuing to enable a communication function for communicating with the sink terminal and continuing to transmit the bus voltage to the sink terminal by the source terminal when the source terminal receives the request message.

Abstract: Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners.

Abstract: The invention relates to a bus-capable device having an input interface and an output interface for connecting to a serial bus, particularly a CAN bus, wherein the input interface and the output interface each have at least one signal line connection, and further having a terminating resistor for terminating the bus and a switch apparatus for switching the terminating resistor active as a function of the connection status of the input and output interfaces, wherein the input interface and the output interface each having a supply voltage connection for providing a supply voltage to the output and/or input interfaces of a respective next bus-capable device and a feedback connection for receiving the supply voltage from an output and/or input interface of a respective next bus-capable device, wherein the switch apparatus has an evaluation circuit for determining the presence of the supply voltage at the feedback connections of the input and output interfaces and an activation circuit for switching the terminati

Abstract: Methods and servers for storing data associated with users and digital items of a recommendation system having access to non-distributed and distributed storages. The server trains a model based for generating first user and item embeddings. The server stores (i) the first user embeddings in the non-distributed storage, and (ii) the first item embeddings in the distributed storage. The server re-trains the model for generating second user and item embeddings. The server stores (i) the second user embeddings in the non-distributed storage in addition to the first user embeddings, and (ii) second item embeddings in the distributed storage instead of the respective first item embeddings by replacing the respective first item embeddings. When the second item embeddings are stored on each node of the distributed storage, the server removes the first user embeddings associated with the first value from the non-distributed storage.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Abstract: A method for operating a communications network that includes at least two users that are communicatively connected to one another via a descriptor-based communication system such as Ethernet. For writing data from a writing user into a user to be written, receive descriptors and data are transmitted from the writing user to the user to be written, in the user to be written, the data being written according to the received receive descriptors, and/or for reading data by a reading user from a user to be read, transmit descriptors are transmitted from the reading user to the user to be read, data being read by the user to be read according to the received transmit descriptors and transmitted to the reading user. A communications network and users are also described.

Abstract: The disclosure provides a USB device, a USB cable, and a USB repeater. The USB cable or the USB device includes a USB connector and the USB repeater. The USB repeater may gain a signal of a differential pin pair of the USB connector. The USB repeater may monitor a signal of a configuration channel pin of the USB connector. The USB repeater selectively runs in one of a plurality of working modes corresponding to a plurality of protocols according to a monitoring result.

Abstract: A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.

Abstract: A connector includes a first pin which is configured to indicate an in-service signal, a second pin which is configured to indicate a power supply signal, a third pin which is configured to indicate a clock signal, and a fourth pin; the first pin which is configured to indicate a PCIe port signal; the first pin, the second pin, the third pin, and the fourth pin have an equal length; and the connector includes a first face and a second face, a limiting structure is arranged on the first face, the limiting structure is a boss or a groove, and the first pin is located in the middle of the first face.

Abstract: An information handling system may include a management controller and information handling resources that are coupled to the management controller via a first communication channel and a second communication channel, each information handling resource having a first communication channel identifier, and each information handling resource having a second communication channel identifier. The management controller may query the information handling resources via the first communication channel to determine a first set of unique identifiers for the information handling resources; query the information handling resources via the second communication channel to determine a second set of unique identifiers for the information handling resources; and based on a comparison between the first set of unique identifiers and the second set of unique identifiers, create a mapping that correlates the first communication channel identifiers with the second communication channel identifiers.

Abstract: A device and a method for interlinking conventional fieldbus-based automatic control system with IoT at a subordinate position are provided. According to the present disclosure, the interlinking system device comprise a fieldbus connection unit connected to an operation device based on a fieldbus protocol and configured to operate as an input-output device, a fieldbus virtual input-output memory configured to memorize input-output information exchanged with the operation device, an IoT connection unit connected to an IoT platform based on an IoT protocol and configured to operate as an IoT device, a message formation unit configured to apply message metadata received from the IoT platform via the IoT connection unit and a message processing unit configured to process an input-output message based on the message metadata and the input-output information.

Abstract: A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.