Patents Examined by Henry W.H. Tsai
  • Patent number: 8627295
    Abstract: Methods and apparatus for testing user interfaces are disclosed herein. An example method includes extracting object data from a file associated with a user interface; storing a plurality of object definitions corresponding to the extracted object data in a computer readable storage medium; and generating, at a computer having a tangible memory, a test script for the user interface using the object definitions, wherein the test script is to be generated based on one or more test definitions defining one or more attributes of the object definitions to be tested in the test script, and wherein the test script is to be generated based on one or more automation rules defining how the object definitions are to be tested.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: January 7, 2014
    Assignee: General Electric Company
    Inventors: Harold Brooks Foley, Christine Peeters
  • Patent number: 8612653
    Abstract: An information processing apparatus includes a plurality of recording media, an operation unit receiving an operation from a user, a communication unit outputting data stored on the recording media to an external device, and a controller displaying, on a display unit, a setting screen for setting a mode for outputting data via the communication unit and to control the apparatus on the basis of information input on the setting screen. The controller displays, as the setting screen, a function selection screen enabling the user to simultaneously select a recording medium serving as a source from which data is output via the communication unit and a function to be executed. On the basis of information input on the function selection screen using the operation unit, the controller performs a setting operation to output data recorded on the selected recording medium in accordance with a communication mode based on the selected function.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: December 17, 2013
    Assignee: Sony Corporation
    Inventors: Kenichiro Nitta, Tatsuhito Tabuchi
  • Patent number: 8578068
    Abstract: Data communications with reduced latency, including: writing, by a producer, a descriptor and message data into at least two descriptor slots of a descriptor buffer, the descriptor buffer comprising allocated computer memory segmented into descriptor slots, each descriptor slot having a fixed size, the descriptor buffer having a header pointer that identifies a next descriptor slot to be processed by a DMA controller, the descriptor buffer having a tail pointer that identifies a descriptor slot for entry of a next descriptor in the descriptor buffer; recording, by the producer, in the descriptor a value signifying that message data has been written into descriptor slots; and setting, by the producer, in dependence upon the recorded value, a tail pointer to point to a next open descriptor slot.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Blocksome, Jeffrey J. Parker
  • Patent number: 8495583
    Abstract: A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to receive one or more risk factors, receive one or more contexts, identify one or more context relationships and associate the one or more contexts with the one or more risk factors. Additionally, the programming instructions are operable to map the one or more risk factors for an associated context to a software defect related risk consequence to determine a risk model and execute a risk-based testing based on the risk model to determine a defect related risk evaluation for a software development project.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kathryn A. Bassin, Howard M. Hess, Sheng Huang, Steven Kagan, Shao C. Li, Zhong J. Li, He H. Liu, Susan E. Skrabanek, Hua F. Tan, Jun Zhu
  • Patent number: 8402172
    Abstract: A method and system for processing an input/output request on a multiprocessor computer system comprises pinning a process down to a processor issuing the input/output request. An identity of the processor is passed to a device driver which selects a device adapter request queue whose interrupt is bound to the identified processor and issues the request on that queue. The device accepts the request from the device adapter, processes the request and raises a completion interrupt to the identified processor. On completion of the input/output request the process is un-pinned from the processor. In an embodiment the device driver associates a vector of the identified processor with the request and the device, on completion of the request, interrupts the processor indicated by the vector.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: March 19, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kishore Kumar Muppirala, Bhanu Gollapudi Venkata Prakash, Narayanan Ananthakrishnan Nellayi
  • Patent number: 8364862
    Abstract: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Michael J. Espig, Zhen Fang, Ravishankar Iyer, David J. Harriman
  • Patent number: 8332544
    Abstract: Systems, methods, and computer program products for assisting play are disclosed. In some examples, the system may include a portable computer including a user interface configured to receive input from a user, and a computer communication mechanism configured to transmit computer data based, at least in part, on the received user input; and a plurality of portable devices each including an enclosure, a device communication mechanism within the enclosure and configured to receive the computer data, a proximity sensor mechanism configured to detect proximity of one or more other portable devices of the plurality of portable devices, and an audiovisual output mechanism configured to generate at least one of an audio output and a visual output based on at least one of (1) the received computer data and (2) the detected proximity of the one or more other portable devices.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: December 11, 2012
    Assignee: Mattel, Inc.
    Inventors: Chaun J. Ralls, Andrew Cheeseman, Michael Young, Paul King, Peter Marx
  • Patent number: 8260977
    Abstract: The present invention provides a CEC communications device which eliminates a troublesome process to solve the CEC-related communication malfunction when the CEC communications device detects a CEC-related communication malfunction caused by a software malfunction and improves serviceability of the CEC communications by automatically resetting the CEC to execute a CEC communication recovery. In the CEC communications device, when a CEC communications line monitoring unit detects a CEC-related communication malfunction caused by a software malfunction, a CEC control unit determines a reset order of a CEC appliance found on a CEC network, and notifies the CEC resetting unit of a CEC resetting request. The CEC resetting unit resets the CEC of a CEC appliance found on the CEC network via an HDMI line (DDC in FIG. 1) other than the CEC to recover the CEC communications.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: September 4, 2012
    Assignee: Panasonic Corporation
    Inventors: Yasuharu Terauchi, Hideki Iwata, Futoshi Ushio, Yuji Hayashi
  • Patent number: 8255599
    Abstract: In PCI-Express and alike communications systems, data bandwidth per channel can vary as a result of negotiated port bifurcation during network bring-up. Disclosed are systems and methods for adjusting FIFO depths in response to negotiated bandwidth per channel so that data absorbing FIFO's of respective channels are not arbitrarily too deep or too shallow relative to the data bandwidths of the channels the FIFO's serve.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: August 28, 2012
    Assignee: Integrated Device Technology inc.
    Inventor: Nadim Shaikli
  • Patent number: 8108580
    Abstract: Technologies for efficient synchronous replication across heterogeneous storage nodes can provide the performance of high-speed storage units while leveraging low-cost and high-capacity backup storage units within the same system. The performance of low-cost, high-capacity hard disks may be improved by initially storing data into sequential physical locations. A sequential journal of I/Os may be used in a replicated secondary node to allow for rapid completion of I/Os. A separate background process can later scatter the sequentially logged I/O data into its proper location for storage. A programmable n-way router can be configured to route I/Os as needed to improve overall performance of the storage unit. A secondary node log device can also be used to provide continuous data protection (CDP). Lastly, packetizing together I/Os prior to delivery to a secondary node may reduce interrupts and context switches in the primary node, thereby improving performance of the storage system.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: January 31, 2012
    Assignee: American Megatrends, Inc.
    Inventors: Paresh Chatterjee, Loganathan Ranganathan, Narayanan Balakrishnan, Srikumar Subramanian
  • Patent number: 8095740
    Abstract: A method and an apparatus for accessing data of a message memory of a communication module by inputting or outputting data into or from the message memory, the message memory being connected to a buffer memory assemblage and the data being transferred to the message memory or from the message memory, the buffer memory assemblage having an input buffer memory in the first transfer direction and an output buffer memory in the second transfer direction; and the input buffer memory and the output buffer memory each being divided into a partial buffer memory and a shadow memory, the following steps being performed in each transfer direction: inputting data into the respective partial buffer memory, and transposing access to the partial buffer memory and shadow memory, so that subsequent data can be inputted into the shadow memory while the previously inputted data are already being outputted from the partial buffer memory in the stipulated transfer direction.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: January 10, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Florian Hartwich, Christian Horst, Franz Bailer
  • Patent number: 8024500
    Abstract: A universal peripheral connector apparatus for a mobile device and in communication with the mobile device. The universal peripheral connector apparatus including: at least one universal serial bus (USB) connector providing at least one connection; at least one USB host controller configured to control the at least one USB connection; a microprocessor configured to control the at least one USB host controller, the microprocessor having an operating system; a USB device control interface on the mobile device configured to communicate and control the universal connector apparatus; and a USB driver configured to operate within the operating system of the universal peripheral connector to enable the mobile device to connect to one or more peripherals via the at least one USB connector.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: September 20, 2011
    Assignee: Research In Motion Limited
    Inventors: Marcelo Varanda, Thanh Vinh Vuong, Luis Estable
  • Patent number: 7979264
    Abstract: A system comprising a media processing apparatus and a computer where the media processing apparatus emulates a mass storage device and interfaces with the computer is disclosed. In one embodiment the media processing apparatus appears to the computer as a Universal serial bus (USB) mass storage device, and the operating system (OS) on the computer, using its pre-installed USB mass storage device driver, establishes bi-directional communication channel with the media processing apparatus. Thus, the need to develop an OS specific kernel-mode device driver for the media processing apparatus is eliminated. The system may employ a proprietary communication protocol on the USB bus to send and receive data between the computer and the media processing apparatus.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: July 12, 2011
    Assignee: Streaming Networks (Pvt) Ltd
    Inventors: Mohammad Ayub Khan, Muhammad Israr Khan, Sved Muhammad Ziauddin, Haroon-ur-Rashid
  • Patent number: 7882280
    Abstract: A packet switching integrated circuit chip is configured to receive packets, e.g., RapidIO™-compliant packets, from a plurality of external sources, and selectively passes data in the received packets to a plurality of external recipients. The chip is configured to pass first received packets without modification and to terminate second received packets and preprocess payloads thereof to produce new packets. The chip may be configured to perform signal sample processing operations on the second received packets, such as bit extension, bit truncation, bit reordering and/or bit arithmetic operations. The chip may be further configured to manage the first and second received packets based on destination addresses in the received packets.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: February 1, 2011
    Assignee: Integrated Device Technology, inc.
    Inventors: Bertan Tezcan, William Terry Beane, Scott Darnell
  • Patent number: 7809867
    Abstract: An apparatus and method for de-bouncing keypad inputs is disclosed including interrupting a processor upon detecting a key press, reading input signals from the key pad to determine an initial port value and starting a timer. A keypad interrupt is disabled and processing resumes until expiration of the timer. The timer interrupts the processor and the input signals are read a second time and combined with the initial port value to determine a key identifier. The timer is started again and processing resumes. Upon expiration of the timer the processor checks for key release. If release is not detected, the timer is again started. If release occurs, the timer is disabled and the keypad interrupt is enabled.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: October 5, 2010
    Assignee: Fluke Corporation
    Inventors: Allen Erik Sjogren, Eric Nerdrum
  • Patent number: 7805550
    Abstract: A data processing apparatus and method are provided for managing polling loops. The data processing apparatus comprises a main processing unit and a subsidiary processing unit operable to perform a task on behalf of the main processing unit. The subsidiary processing unit is operable to set a completion field when the task has been completed and the main processing unit is operable to poll the completion field in order to determine whether the task has been completed. If on polling the completion field a threshold number of times the main processing unit determines that the task has not been completed, the main processing unit is operable to enter a power saving mode. The subsidiary processing unit is operable, when the task has been completed, to cause a notification to be issued on a path interconnecting the main processing unit and the subsidiary processing unit. The main processing unit is arranged, upon receipt of the notification to exit the power saving mode.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: September 28, 2010
    Assignee: ARM Limited
    Inventors: Paul Kimelman, Richard Roy Grisenthwaite
  • Patent number: 7805546
    Abstract: Methods, systems, and products are disclosed for chaining DMA data transfer operations for compute nodes in a parallel computer that include: receiving, by an origin DMA engine on an origin node in an origin injection FIFO buffer for the origin DMA engine, a RGET data descriptor specifying a DMA transfer operation data descriptor on the origin node and a second RGET data descriptor on the origin node, the second RGET data descriptor specifying a target RGET data descriptor on the target node, the target RGET data descriptor specifying an additional DMA transfer operation data descriptor on the origin node; creating, by the origin DMA engine, an RGET packet in dependence upon the RGET data descriptor, the RGET packet containing the DMA transfer operation data descriptor and the second RGET data descriptor; and transferring, by the origin DMA engine to a target DMA engine on the target node, the RGET packet.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: September 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, Michael A. Blocksome
  • Patent number: 7802023
    Abstract: Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: September 21, 2010
    Assignees: Sony Computer Entertainment Inc., International Business Machines Corporation
    Inventors: Takeshi Yamazaki, Scott Douglas Clark, Charles Ray Johns, James Allan Kahle
  • Patent number: 7802025
    Abstract: A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: September 21, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Alan G. Gara, Mark E. Giampapa, Philip Heidelberger, Burkhard Steinmacher-Burow, Pavlos Vranas
  • Patent number: 7801478
    Abstract: An electronic device includes a first communication interface operable to receive a decoded digital data set from an apparatus remote from the electronic device, and a first circuit coupled to the first communication interface and operable to enable an output device to provide an output representing the data set.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: September 21, 2010
    Assignee: Marvell International Technology Ltd.
    Inventor: Charles Evans