Abstract: An interface controller is connected to a host apparatus and a memory, and receiving multiple responses to one request. The interface controller includes a packet generation unit which adds header data to a request issued by the host apparatus to generate a request packet and outputs the request packet to the memory, a receive buffer which stores a response packet with respect to the request packet, a protocol generation unit which generates a response according to a prescribed protocol based on the response packet stored in the receive buffer, and outputs the response to the host apparatus, a maximum division number calculation unit which calculates a maximum division number of the request issued by the host apparatus, and a request issue control unit which gives a request issue permission to the host apparatus based on the maximum division number calculated by the maximum division number calculation unit, a maximum division number of processed request and a maximum division number of processed response.

Abstract: A processor arrangement having a strip structure for parallel data processing is configured so that local data from the individual processing units or strips is brought together in a rapid manner. Input data, intermediate data and/or output data from various processing units are linked together in an operation which is at least partially combinatory. The data linking operation is not clock controlled. The linking of the local data from various strips in this manner reduces delays in parallel data processing in the processor arrangement. The combinatory data linking operation can provide an overall data linking outcome within an individual clock cycle.

Abstract: A method of transmitting data between storage virtualization controllers (SVCs) in a computer system is disclosed, in which there is an inter-controller communication channel (ICC) between the storage virtualization controllers. The method comprises the steps of: a central processing unit (CPU) of one storage virtualization controller (SVC) sending a data transfer request to an interface that establishes the ICC when the CPU needs to transmit information to the other SVC; and transmitting the information to the other SVC after the interface that establishes the ICC receives the data transfer request, and obtains the information.

Abstract: An electronic apparatus that transmits error information about setting of a block size to a host device includes an interface section that transmits and receives a command, a response and data to and from the host device. When the data is a predetermined length or more, the interface section executes multi-block transmission. Moreover, the electronic apparatus includes a data buffer, and a storage section that stores information about a block size. When the interface section receives a block size setting command transmitted from the host device and the block size is larger than a capacity of the data buffer, it transmits a response including error information about incapability of accepting the block size at the time which has a predetermined relation to the block size setting command.

Abstract: Methods and apparatus provide for assigning an identifier to a DMA command, the identifier for association with an entry of a DMA table containing status information regarding the DMA command; receiving an indication that a DMA data transfer defined by the DMA command has been completed; and updating the status information of the entry of the DMA table associated with the DMA data transfer to indicate that the DMA data transfer has been completed.

Abstract: A DMA circuit operates a plurality of DMA channels in parallel, enabling reduction of the circuit scale and fewer development processes. A channel manager circuit reads in sequence the control information for each DMA channel from control memory, performs analysis, and according to the divided DMA control sequence, performs state processing (DMA control). Further, the channel manager circuit updates the control information, writes back the control information to the control memory, and executes time-division control of the plurality of DMA channels. Hence the circuit scale can be reduced, contributing to decreased costs, and the number of development processes can be reduced.

Abstract: A communication device may receive successive key inputs, determine an average time duration between successive key inputs, start a timeout, determine if a timeout was successful and adjust the timeout period based on the determined success of the timeout.

Abstract: A new audio playback architecture may be used, which allows the use of much larger buffering than that used by a typical audio subsystem in a computing system to improve power efficiency of the system and at the same time allows to maintain the quality (e.g., fidelity and responsiveness) of the audio playback. The audio controller in the new architecture may be made to report back to the host system a more accurate indication of which audio frame is being set to the audio codec than a currently available audio controller does. Additionally, the controller is capable of re-fetching previously buffered (but not yet transmitted) data. Furthermore, buffers in both the audio controller and the main memory may be dynamically adjusted during playback of audio data and/or for different applications.

Abstract: Method of managing interaction between a host subsystem and a peripheral device. Roughly described, the peripheral device writes an event into an individual event queue, and in conjunction therewith, also writes a wakeup event into an intermediary event queue. The wakeup event identifies the individual event queue. The host subsystem, in response to retrieval of the wakeup event from the intermediary event queue, activates an individual event handler to consume events from the individual event queue.

Abstract: Disclosed herein is a semiconductor storage device operable in a plurality of operation modes each having a separate maximum current consumption. The device includes: a data communication section configured to be capable of performing data communication in a plurality of communication modes; an attribute information storage section configured to store attribute information indicating the operation and communication modes; and a mode setting section configured to set the device to one of the operation modes and one of the communication modes. The data communication section transmits, to an electronic apparatus to which the device is attached, the information and receives from the apparatus a mode setting command for directing that the device be set to a combination of an operation mode and a communication mode selected from among the information. In accordance therewith, the mode setting section sets the device to the selected combination of modes.

Abstract: An apparatus, system, and method are disclosed for acceleration initiated association. A peripheral knock module receives a first knock command from a first accelerometer of a peripheral device. The first knock command comprises a plurality of peripheral time stamps for a plurality of peripheral device accelerations. A peripheral identifier module creates a peripheral identifier comprising time interval values of time intervals between the peripheral time stamps. A broadcast module broadcasts a discovery signal with a signal identifier that comprises the peripheral identifier.

Abstract: An electronic device includes a universal serial bus (USB) interface therein. This USB interface is configured to support at least first and second different USB interface standards. These different interface standards are selected by the electronic device in response to comparing a voltage level of a signal provided to said USB interface relative to a reference voltage generated within the electronic device. The signal provided to the USB may be a power supply signal, the first USB standard may be a USB 2.0 interface standard and the second USB standard may be an inter-chip USB interface standard.

Abstract: A software-defined radio (SDR) system comprising: 1) a reconfigurable baseband subsystem for supporting a plurality of wireless communication standards comprising a first plurality of reconfigurable context-based operation instruction set processors; and 2) a reconfigurable application subsystem for supporting a plurality of end-user applications comprising a second plurality of reconfigurable context-based operation instruction set processors. Each of the first and second pluralities of reconfigurable context-based operation instruction set processors comprises: i) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and ii) a programmable finite state machine that controls the reconfigurable data path, wherein the programmable finite state machine is capable of executing a plurality of instructions associated with a particular function.

Abstract: A method and apparatus for caching instructions for a processor having multiple operating states. At least two of the operating states of the processor supporting different instruction sets. A block of instructions may be retrieved from memory while the processor is operating in one of the states. The instructions may be pre-decoded in accordance with said one of the states and loaded into cache. The processor, or another entity, may be used to determine whether the current state of the processor is the same as said one of the states used to pre-decode the instructions when one of the pre-decoded instructions in the cache is needed by the processor.

Abstract: A data reading method includes the steps of: a reading request issuing step of issuing a reading request for reading predetermined stored data; and a reading request re-issuing step of re-issuing a reading request when read data responsive to the reading request has not arrived within a predetermined time period, wherein: in the reading request re-issuing step, a flag is attached to the re-reading request, and thus, the re-reading request is differed from the first issued reading request.

Abstract: An electronic apparatus which makes it possible to reduce start-up time for starting the electronic apparatus, without necessitating installment of a plurality of CPUs in the electronic apparatus. A main CPU 45 controls a digital camera implementing the electronic apparatus. A storage medium for storing information can be detachably attached to a connector 97. A medium detection circuit 85 monitors a status of attachment and detachment of the storage medium to and from the digital camera, irrespective of a status of operation of the main CPU 45. The sensed status of attachment and detachment of the storage medium is stored in a register 115 of the medium detection circuit 85.

Abstract: A telecommunications system and constituent two-wire interface module. The two wire interface module includes a logic component configured to communicate over the same pair of wires using different two-wire interface protocols depending on an input signal presented on a configuration input. This configurability allows the two-wire interface module to use the same two wires to communicate with a variety of other two-wire interface modules, even if those two-wire interface modules communicate using different two-wire interface protocols.

Abstract: Disclosed are methods for handling RDMA connections carried over packet stream connections. In one aspect, I/O completion events are distributed among a number of processors in a multi-processor computing device, eliminating processing bottlenecks. For each processor that will accept I/O completion events, at least one completion queue is created. When an I/O completion event is received on one of the completion queues, the processor associated with that queue processes the event. In a second aspect, semantics of the interactions among a packet stream handler, an RDMA layer, and an RNIC are defined to control RDMA closures and thus to avoid implementation errors. In a third aspect, semantics are defined for transferring an existing packet stream connection into RDMA mode while avoiding possible race conditions. The resulting RNIC architecture is simpler than is traditional because the RNIC never needs to process both streaming messages and RDMA-mode traffic at the same time.

Abstract: A communications buffer and control unit that configure a USB connection endpoint are provided connected by a USB bus to a host device. The control unit changes the receive buffer size of a receive buffer where the communications buffer stores receive data, based on an instruction that is sent from the host device side through USB virtual serial communication, to enable the reception of real-time execution commands by the communications device. This enables the reception of real-time execution commands when the receive buffer on the communications device side is in a buffer-full state in data communications between a host device and a communications device.

Abstract: A method for scheduling instructions for clustered digital signal processors comprising a plurality of clusters, each cluster including at least two functional units and a first register file having a first unit, a second unit and a single set of access ports shared by the functional units comprises steps of checking whether executing one instruction needs data to be read from the first unit and the second unit of the first register file, generating a copying instruction to transfer data from the first unit to the second unit of the first register file, checking whether there is a prior operation cycle available to perform the copying instruction, scheduling the copying instruction in the prior operation cycle, and scheduling the instruction after the copying instruction.