Abstract: Systems and methods for semiconductor wafer processing include irradiating a surface of a semiconductor wafer with a laser beam of sufficient energy to alter a band gap of semiconductor material thereby melting a portion of the wafer to generate a graphitic layer area. A metal layer is then depositing on the surface to create ohmic contacts at the area that where melted by the laser.

Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract: Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second serially-coupled transistors are formed. The first transistor includes a first well region having a first lateral edge partially forming the first transistor's base. The second transistor including a second well region having a second lateral edge partially forming the second transistor's base. Third and fourth well regions are formed in the first and second transistors, respectively, and extend a different distance into the substrate than do the well regions of the first and second transistors. The third well region has a third lateral edge separated from the first lateral edge by a first spacing dimension D1. The fourth well region has a fourth lateral edge separated from the second lateral edge by a second spacing dimension D2, which is different than D1.

Abstract: The invention concerns a silicon devices/heatsinks stack assembly and a method to pull apart a faulty silicon device in said stack assembly. Said silicon devices/heatsinks stack assembly comprises an arrangement of many silicon devices disks, two adjacent silicon devices disks being separated by a flat heatsink device, each silicon device disk and each heatsink comprising a centering hole on its both faces, a centering pin placed between the adjacent centering holes of a silicon device disk and an adjacent heatsink device. Each heatsink device is pierced with two guide holes, at two opposite ends of this one.

Abstract: The present application discloses a semiconductor Field-Effect Transistor (FET) structure and a method for manufacturing the same, wherein the method comprises: forming a semiconductor substrate comprising an SOI structure having a body-contact hole; forming a fin on the SOI structure of the semiconductor substrate; forming a gate stack structure on top and side faces of the fin; forming source/drain structures in the fin on both sides of the gate stack structure; and performing metallization. The present invention makes use of traditional quasi-planar based top-down processes, thus the manufacturing process thereof becomes simple to implement; the present invention exhibits good compatibility with CMOS planar process and can be easily integrated; the present invention also is favorable for suppressing short channel effects desirably, and boosts MOSFETs to develop towards a trend of downscaling size.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer and a light emitting part. The first semiconductor layer includes an n-type semiconductor layer. The second semiconductor layer includes a p-type semiconductor layer. The light emitting part is provided between the first semiconductor layer and the second semiconductor layer, and includes a plurality of barrier layers and a well layer provided between the plurality of barrier layers. The first semiconductor layer has a first irregularity and a second irregularity. The first irregularity is provided on a first major surface of the first semiconductor layer on an opposite side to the light emitting part. The second irregularity is provided on a bottom face and a top face of the first irregularity, and has a level difference smaller than a level difference between the bottom face and the top face.

Abstract: A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction.

Abstract: Transistors having sulfur-doped zinc oxynitride channel layers, and methods of manufacturing the same, include a ZnON channel layer with sulfur content ratio with respect to a zinc content of from about 0.1 at % to about 1.2 at %, a source electrode and a drain electrode respectively formed on a first region and a second region of the channel layer, a gate electrode corresponding to the channel layer, and a gate insulation layer between the channel layer and the gate electrode.

Abstract: A thin-film transistor (TFT) array substrate includes a first conductive layer of a TFT, a second conductive layer that partially overlaps the first conductive layer, a through hole in a layer between the first and second conductive layers, a node contact hole integrally formed to include a first contact hole in the first conductive layer and a second contact hole in the second conductive layer such that the first contact hole is continuous with the second contact hole and is not separated from the second contact hole by an insulation layer, and a connection node that is in another layer different from the first conductive layer and the second conductive layer. The connection node is connected to the first and second conductive layers through the through hole and the node contact hole.

Abstract: The present invention generally relates to a method for manufacturing an improved solar cell module, more particularly to a method for manufacturing the improved solar cell module that may not happen problems of power leakage and short circuit and save the cost to manufacturing.