Abstract: A display device includes a pixel circuit, a first insulation layer covering the pixel circuit, a first electrode disposed on the first insulation layer, a second electrode disposed on the first insulation layer while being spaced apart from the first electrode, a second insulation layer covering the first electrode, the second electrode, and the first insulation layer disposed between the first electrode and the second electrode, and a light emitting element electrically connected to the first electrode and the second electrode on the second insulation layer and disposed between the first electrode and the second electrode. Here, the second insulation layer includes a first area overlapping the first electrode, a second area overlapping the second electrode, and a stopper area disposed between the first electrode and the second electrode, and the stopper area has a thickness different from that of each of the first area and the second area.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: In a method of manufacturing a semiconductor device, a gate structure is formed over a fin structure. A source/drain region of the fin structure is recessed. A first semiconductor layer is formed over the recessed source/drain region. A second semiconductor layer is formed over the first semiconductor layer. The fin structure is made of SixGe1-x, where 0?x?0.3, the first semiconductor layer is made of SiyGe1-y, where 0.45?y?1.0, and the second semiconductor layer is made of SizGe1-z, where 0?z?0.3.

Abstract: An organic light-emitting display apparatus including an organic light-emitting diode emitting visible light, a driving thin film transistor driving the organic light-emitting diode, and a compensation thin film transistor. The compensation thin film transistor includes a compensation gate electrode, a compensation semiconductor layer, a compensation source electrode, and a compensation drain electrode. The compensation gate electrode includes a first gate electrode, and a second gate electrode electrically connected to the first gate electrode. The compensation drain electrode is electrically connected to the driving gate electrode of the driving thin film transistor.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate; forming an insulating layer above the substrate; forming a first opening in the insulating layer; conformally forming a first framework layer in the first opening; forming an energy-removable layer on the first framework layer and filling the first opening; forming a second opening along the energy-removable layer and the first framework layer; conformally forming a second framework layer in the second opening; forming a top contact on the second framework layer and filling the second opening and forming a top conductive layer on the top contact; and performing an energy treatment to transform the energy-removable layer into porous insulating layers on two sides of the top contact.

Abstract: The disclosed current-distribution inductor may include (1) a magnetic core and (2) a conductor electrically coupled between a power source and an electrical component of a circuit board, wherein the conductor comprises (A) a bend that passes through the magnetic core and (B) a flying lead that extends from the bend to the electrical component of the circuit board and runs parallel with the circuit board. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region, wherein the active region comprises multiple alternating well layers and barrier layers, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies at a distance of between 15 nm and 60 nm from the upper surface of the active region.

Abstract: A semiconductor device includes a substrate, a lower structure on the substrate, the lower structure including a first wiring structure, a second wiring structure, and a lower insulating structure covering the first and second wiring structures, a first pattern layer including a plate portion and a via portion, the plate portion being on the lower insulating structure and the via portion extending into the lower insulating structure from a lower portion of the plate portion and overlapping the first wiring structure, a graphene-like carbon material layer in contact with the via portion and the first wiring structure between the via portion and the first wiring structure, gate layers stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other on the first pattern layer, and a memory vertical structure penetrating through the gate layers in the vertical direction.

Abstract: Semiconductor structure and its fabrication method are provided. The method includes providing a substrate, where the substrate includes a first region having a first metal structure and a second region having a second metal structure; forming a device layer on each of top surfaces of the substrate, the first metal structure and the second metal structure; forming a first through hole in the device layer at the first region, where the first through hole exposes at least a portion of surfaces of the first metal structure, and forming a second through hole in the device layer at the second region, where the second through hole passes through the first device and exposes at least a portion of surfaces of the second metal structure; and using a selective metal growth process, forming a first plug in the first through hole and forming a second plug in the second through hole.

Abstract: A Hall sensor includes a Hall well, such as an implanted region in a surface layer of a semiconductor structure, and four doped regions spaced apart from one another in the implanted region. The implanted region and the doped regions include majority carriers of the same conductivity type. The sensor also includes a dielectric layer that extends over the implanted region, and an electrode layer over the dielectric layer to operate as a control gate to set or adjust the sensor performance. A first supply circuit provides a first bias signal to a first pair of the terminals, and a second supply circuit provides a second bias signal to the electrode layer.

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

Abstract: According to one embodiment, a semiconductor storage device includes: first and second plate-shaped portions which extend in a stacking direction of each layer of a first stacked body and a first direction intersecting the stacking direction and are arranged between the first stacked body and a second stacked body on both sides of the second stacked body in a second direction intersecting the stacking direction and the first direction; and an isolation layer that penetrates at least the uppermost conductive layer among a plurality of conductive layers and isolates the uppermost conductive layer in the second direction. The isolation layer extends in a portion of the first stacked body in the first direction toward the second stacked body, and is connected to a side surface of the first plate-shaped portion from a first region on an inner side of the first and second plate-shaped portions.

Abstract: In a method of manufacturing a semiconductor device, a gate structure is formed over a fin structure. A source/drain region of the fin structure is recessed. A first semiconductor layer is formed over the recessed source/drain region. A second semiconductor layer is formed over the first semiconductor layer. The fin structure is made of SixGe1-x, where 0?x?0.3, the first semiconductor layer is made of SiyGe1-y, where 0.45?y?1.0, and the second semiconductor layer is made of SizGe1-z, where 0?z?0.3.

Abstract: An image sensor device is disclosed, which blocks noise of a pad region. The image sensor device includes a substrate including a first surface and a second surface that are arranged to face each other, a pad disposed over the first surface of the substrate, and a through silicon via (TSV) formed to penetrate the substrate, and disposed at both sides of the pad in a first direction.

Abstract: The present disclosure provides a photodiode, a display substrate, and manufacturing methods thereof, and a display device. The method for manufacturing the photodiode includes: forming a semiconductor material layer on a base substrate in a non-display region of a display substrate, the semiconductor material layer including a first contact area, a second contact area, and a semiconductor area sandwiched therebetween; processing the first contact area of the semiconductor material layer to form a first contact electrode; processing portions of the semiconductor material layer and the second contact area away from the base substrate in the semiconductor area, to form a first semiconductor layer and a second semiconductor layer stacked, the second semiconductor layer being located on a side of the first semiconductor layer away from the base substrate; and processing the second semiconductor layer in the second contact area to form a second contact electrode.

Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate having merged cavities in the substrate. An active region is over the merged cavities in the substrate. A thermally conductive layer is in the merged cavities in the substrate, whereby the thermally conductive layer at least partially fills up the merged cavities in the substrate. A first contact pillar connects the thermally conductive layer in the merged cavities in the substrate with a metallization layer above the active region.

Abstract: In an illuminance sensor, a slow axis of a first quarter-wave plate has a relation of +45° or ?45° in regard to a polarization direction of a first linear polarization plate; a relation of a slow axis of a first portion of a second quarter-wave plate in regard to a polarization direction of a second linear polarization plate is the same with relation of the slow axis of the first quarter-wave plate in regard to the polarization direction of the first linear polarization plate, that is, +45° or ?45°; and a relation of a slow axis of a second portion of the second quarter plate in regard to the polarization direction of the second linear polarization plate is ?45° or +45° that is opposite in sign to the relation of the slow axis of the first quarter-plate in regard to the polarization direction of the first linear polarization plate.

Abstract: An electronic chip includes at least an electronic circuit disposed on a front face of a substrate; and an embrittlement structure comprising at least blind holes, each extending through a rear face of the substrate and a portion of the thickness of the substrate and each having a section, in a plane parallel to the rear face of the substrate, of surface area S and having a closed outer contour, the shape of which includes at least one radius of curvature R, such that S>?·R2.

Abstract: According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.