Abstract: A memory device includes a nonvolatile memory and a memory controller. The memory controller receives first data from a host file system; stores the first data in a first physical block of the nonvolatile memory identified by a first physical page number (PPN); associates the first PPN with a first virtual page number (VPN); and communicates the first VPN to the host file system in response to receiving the first data.

Abstract: A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.

Abstract: A system and method facilitate processing atomic storage requests. The method includes receiving, from a storage client, an atomic storage request for a first storage device that is incapable of processing atomic write operations. The method also includes processing the atomic storage request at a translation interface. The method also includes storing the atomic storage request in one or more storage operations in a second storage device capable of processing the atomic storage request.

Abstract: Accessing a hybrid memory using a translation line is disclosed. The hybrid memory comprises a first portion. The translation line maps a first physical memory address to a first line in the first portion. Said mapping provides an indication that the first line is not immediately accessible in the first portion.

Abstract: A page compression strategy classifies uncompressed pages selected for compression. Similarly classified pages are compressed and bound into a single logical page. For logical pages having pages with more than one classification, a weighting factor is determined for the logical page.

Abstract: A solid state drive includes a nonvolatile memory, a random access memory, and a memory controller. The nonvolatile memory contains a plurality of nonvolatile memories chips and a buffer chip. The memory controller is formed of an internal bus, a host interface, a memory interface, a buffer control circuit, and a processor.

Abstract: A page compression strategy classifies uncompressed pages selected for compression. Similarly classified pages are compressed and bound into a single logical page. For logical pages having pages with more than one classification, a weighting factor is determined for the logical page.

Abstract: Live updating of a changed block tracking (CBT) driver. In one example embodiment, a method for live updating of a CBT driver may include loading a CBT driver into a running operating system and then performing various acts without rebooting the running operating system. These acts may include tracking, using the CBT driver, writes to blocks of a source storage, loading an updated CBT driver into the running operating system with the updated CBT driver having a different name than the CBT driver, handing over the tracking of writes to blocks of the source storage from the CBT driver to the updated CBT driver, and tracking, using the updated CBT driver, writes to blocks of the source storage.

Abstract: Systems, methods, and/or devices are used to manage a storage system. In one aspect, the method includes receiving, from a host to which a storage device of the storage system is operatively coupled, a request to perform a first memory operation on one or more memory devices of the storage device. The method includes determining a count of credits corresponding to the first memory operation. If a current count of credits in the first credit pool is greater than or equal to the count of credits corresponding to the first memory operation and a current count of credits in the second credit pool is greater than or equal to the count of credits corresponding to the first memory operation, the method includes: performing the first memory operation; and decrementing the first and second credit pools according to the count of credits corresponding to the first memory operation.

Abstract: A multiprocessor system providing transactional memory. A first processor initiates a transaction which includes reading first data into a private cache of the first processor, and performing a write operation on the first data in the private cache of the first processor. In response to detecting that prior to the write operation the first data was last modified by a second processor, the first processor writes the modified first data into a last level cache (LLC) accessible by the multiple processors. The system sets a cache line state index string to indicate that the first data written into the LLC was last modified by the first processor, invalidates the first data in the private cache of the first processor, and commits the transaction to the transactional memory system. This allows more efficient accesses to the data by the multiple processors.

Abstract: A method for implementing nonvolatile memory array logic includes configuring a crosspoint memory array in a first configuration and applying an input voltage to the crosspoint array in the first configuration to produce a setup voltage. The crosspoint array is configured in a second configuration and an input voltage is applied to the crosspoint array in the second configuration to produce a sense voltage. The setup voltage and the sense voltage compared to perform a logical operation on data stored in the crosspoint array. A system for performing nonvolatile memory array logic is also provided.

Abstract: A method and apparatus for power management of cache duplicate tags is disclosed. An IC includes a cache, a coherence circuit, and a duplicate tags memory that may store duplicates of the tags stored in the cache. The cache includes a number of ways that are separately and independently power controllable. The duplicate tags memory may be similarly organized, with portions that are power controllable separately and independently of others. The coherence circuit is also power controllable, and may be placed into a sleep mode when idle. The IC also includes a power management circuit. During operation, the cache may change power states and provide a corresponding indication to the power management circuit. Responsive to the indication, the power management circuit may awaken the coherence circuit if in a sleep state. The coherence circuit may then power manage the duplicate tags in accordance with the change in power state.

Abstract: When the capacity of a buffer region runs short, storing a first generation data set, a second generation data set, and a third generation data set, a control unit selects the first generation data set as a designated data set. The control unit creates, and stores in a storage unit, update record information based on the first generation data set. The control unit identifies the position where the first generation data set is to be stored in the copy source volume according to correspondence relation information, and updates the copy source volume with the first generation data set. The control unit deletes the first generation data set from the buffer region, and also deletes the correspondence relation information corresponding to the first generation data set from the storage unit.

Abstract: A transactional memory (TM) receives an Atomic Look-up, Add and Lock (ALAL) command across a bus from a client. The command includes a first value. The TM pulls a second value. The TM uses the first value to read a set of memory locations, and determines if any of the locations contains the second value. If no location contains the second value, then the TM locks a vacant location, adds the second value to the vacant location, and sends a result to the client. If a location contains the second value and it is not locked, then the TM locks the location and returns a result to the client. If a location contains the second value and it is locked, then the TM returns a result to the client. Each location has an associated data structure. Setting the lock field of a location locks access to its associated data structure.

Abstract: In response to receiving a write request directed to a particular logical block of a storage object, a page of free space (sufficient to accommodate the payload of the write request, but smaller in size than the logical block) of a particular extent that has been selected to store contents of the logical block is allocated. The current size of the extent is smaller than the combined sizes of logical blocks that are mapped to the extent. The page is modified in accordance with a payload indicated in the write request. In response to a subsequent write request directed to the particular extent, a determination is made that the particular extent would violate a free space threshold criterion if the payload of the write request were accommodated, and an extent expansion operation is initiated.

Abstract: An address translation capability in which a processor obtains an address to be translated, and translates the address from the address to the another address. The translating includes determining an attribute of the address to be translated, and based on the attribute being a first attribute, first information is selected to be used in translating the address. Further, based on the attribute being a second attribute, second information is selected to be used in translating the address. The selected information is used to translate the address to the another address. The another address indicates one memory location based on the selected information being the selected first information, and another memory location based on the selected information being the selected second information.

Abstract: An address translation capability in which a processor obtains an address to be translated, and translates the address from the address to the another address. The translating includes determining an attribute of the address to be translated, and based on the attribute being a first attribute, first information is selected to be used in translating the address. Further, based on the attribute being a second attribute, second information is selected to be used in translating the address. The selected information is used to translate the address to the another address. The another address indicates one memory location based on the selected information being the selected first information, and another memory location based on the selected information being the selected second information.

Abstract: A multiprocessor system providing transactional memory. A first processor initiates a transaction which includes reading first data into a private cache of the first processor, and performing a write operation on the first data in the private cache of the first processor. In response to detecting that prior to the write operation the first data was last modified by a second processor, the first processor writes the modified first data into a last level cache (LLC) accessible by the multiple processors. The system sets a cache line state index string to indicate that the first data written into the LLC was last modified by the first processor, invalidates the first data in the private cache of the first processor, and commits the transaction to the transactional memory system. This allows more efficient accesses to the data by the multiple processors.

Abstract: A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.

Abstract: A page compression strategy classifies uncompressed pages selected for compression. Similarly classified pages are compressed and bound into a single logical page. For logical pages having pages with more than one classification, a weighting factor is determined for the logical page.