Patents Examined by Hewy Li
  • Patent number: 9165650
    Abstract: The hybrid dynamic-static encoder described herein may combine dynamic and static structural and logical design features that strategically partition dynamic nets and logic to substantially eliminate redundancy and thereby provide area, power, and leakage savings relative to a fully dynamic encoder with an equivalent logic delay. For example, the hybrid dynamic-static encoder may include identical top and bottom halves, which may be combined to produce final encoded index, hit, and multi-hit outputs. Each encoder half may use a dynamic net for each index bit with rows that match a search key dotted. If a row has been dotted to indicate that the row matches the search key, the dynamic nets associated therewith may be evaluated to reflect the index associated with the row. Accordingly, the hybrid dynamic-static encoder may have a reduced set of smaller dynamic nets that leverage redundant pull-down structures across the index, hit, and multi-hit dynamic nets.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 20, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: David Paul Hoff, Tracey A. Della Rova, Jason P. Martzloff
  • Patent number: 9146920
    Abstract: A transactional memory (TM) receives an Atomic Look-up, Add and Lock (ALAL) command across a bus from a client. The command includes a first value. The TM pulls a second value. The TM uses the first value to read a set of memory locations, and determines if any of the locations contains the second value. If no location contains the second value, then the TM locks a vacant location, adds the second value to the vacant location, and sends a result to the client. If a location contains the second value and it is not locked, then the TM locks the location and returns a result to the client. If a location contains the second value and it is locked, then the TM returns a result to the client. Each location has an associated data structure. Setting the lock field of a location locks access to its associated data structure.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: September 29, 2015
    Assignee: NETRONOME SYSTEMS, INC.
    Inventors: Gavin J. Stark, Johann Heinrich Tönsing
  • Patent number: 9122418
    Abstract: A method of controlling the capacity of a virtual storage system provided on a physical storage system, the method including: providing a control program on the physical storage system; coupling additional virtual storage to the virtual storage system on the physical storage system; providing control data on the additional virtual storage; with the control program, reading the control data and configuring the virtual storage system accordingly. A corresponding virtual storage system is also provided.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: September 1, 2015
    Assignee: XYRATEX TECHNOLOGY LIMITED—A SEAGATE COMPANY
    Inventor: James S. M. Morse
  • Patent number: 9122400
    Abstract: For managing a data set volume table of contents, a management module creates a data set volume table of contents (DSVTOC) for a data set residing on a volume. The DSVTOC resides in a virtual storage access method (VSAM) system and includes a DSVTOC index, DSVTOC cluster data, and DSVTOC data for the data set. A copy module maintains a copy of the DSVTOC on the volume.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dustin A. Helak, Miguel A. Perez, David C. Reed, Max D. Smith
  • Patent number: 9086882
    Abstract: An application program identifies a plurality of least recently accessed constructs of the application program that reside in DRAM memory. The application program causes the aggregation of at least a portion of the identified least recently accessed constructs onto one or more pages of the DRAM memory. The application program then causes the one or more memory pages of the DRAM memory to be put into self-refresh operation mode.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventor: Indrajit Poddar
  • Patent number: 9086987
    Abstract: There is provided a system and a computer program product for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: July 21, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold W. Cain, III, Hung Q. Le, Bryan Lloyd, Shih-Hsiung Tung
  • Patent number: 9086986
    Abstract: There is provided a method for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 21, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold W. Cain, III, Hung Q. Le, Bryan Lloyd, Shih-Hsiung Tung
  • Patent number: 8954652
    Abstract: In a method for identifying a unit in a solid state memory device for writing data to a tier structure is maintained the tier structure comprising at least two tiers for assigning units available for writing data to. In response to receiving a request for writing data it is determined if a unit for writing data to is available in a first tier of the at least two tiers. In response to determining that a unit is available for writing data to in the first tier this unit is identified for writing data to, and in response to determining that no unit is available for writing the data to in the first tier it is determined if a unit is available for writing data to in a second tier of the at least two tiers subject to a priority of the write request.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert Haas, Roman Pletka