Abstract: According to the semiconductor device and method of the present invention, because regular cache memories subjected to hit checks are distinguished from spare cache memories not subjected to hit checks, and because sense amplifiers are also used as cache memories, built-in cache memories are operated faster and at low power consumption. A memory control unit is capable of distinguishing regular memories subjected to hit checks and spare memories not subjected to hit checks. This way, if a hit check is a miss, one of the cache memories not subjected to a hit checks is subjected to a subsequent hit operation and another one of the cache memories not subjected to hit checks is not subjected to the next hit check operation.

Abstract: We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. An interesting feature of our obstruction-free STM implementation is its ability to use of modular contention managers to ensure progress in practice.

Abstract: Non-volatile memory device, driver, and method is described that utilizes write or erase cycle tracking to interrupt or stop a non-volatile memory programming or erase operation at a selected point to interrupt/stop execution or simulate power loss at a specific point. This ability allows for a deterministic and repeatable testing process of all write or erase cycles of a non-volatile command where the state of floating gate memory cells are changed in the non-volatile memory device. Additionally, this ability to utilize write or erase cycle tracking to interrupt or stop a non-volatile memory programming operation or erasing operation at any selected point enables simulation of power loss at each point in a selected operation that a non-volatile floating gate memory cell is programmed or erased, allowing for improved, deterministic testing of the power loss recovery cycle and faster code/design change verification.

Abstract: Methods and apparatus for providing seamless functionality in a computer are disclosed. For example, a Redundant Array of Independent Disks (RAID) configuration manager provides an operating system with a content of a virtual disk interface to enable a commensurate software RAID to be utilized after the operating system is loaded, loads a driver to abstract a plurality of disk interfaces for a plurality of disks, publishes a physical access abstraction interface and a device path protocol for each disk, obtains a global variable to obtain a specific RAID technique, publishes a virtual disk interface for the plurality of disks and maps the plurality of disks according to the specific RAID technique. An encrypted file system manager is also included to layer an encoded File Allocation Table on top of a disk and to pass to the operating system an Embedded Root Key to provide access to an encrypted Firmware Interface System Partition.

Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data.

Abstract: A method, apparatus, and computer instructions for generating coverage data during execution of code in the data processing system. During execution of the code, a determination is made as to whether an access indicator is associated with an instruction in response to executing the instruction in the code by a processor in the data processing system. If the access indicator is associated with the instruction, a state of the access indicator is changed, by the processor, when the instruction is executed. In this manner, coverage data for executed instructions is generated by the processor during execution of the code.

Abstract: Using a snapshot function, a remote copy is efficiently created. Data for a snapshot is converted into a first bitmap of differential data for a remote copy. The conversion is performed in advance at appropriate chronological intervals. Furthermore, when the snapshot function splits, a second bitmap of cascade differential data, which is new differential data, is created simultaneously with creation of the data for the snapshot. This second bitmap of cascade differential data is created in the same format as the first bitmap of differential data for the remote copy. Then, when the snapshot function shifts from split status to pair status, the second bitmap of cascade differential data is added to the first bitmap of differential data for the remote copy (to produce a logical sum), and a remote copy is created based on this bitmap that was added.

Abstract: A system for optimizing storage operations by operating only on mapped blocks may include a first and a second set of one or more storage devices, a virtual device client and a virtual device server. The virtual device server may be configured to aggregate storage in the first set of one or more storage devices into a virtual storage device, and make the virtual device accessible to the virtual device server. In preparation for a synchronization operation, the virtual device server may obtain a map identifying one or more in-use regions of the virtual storage device from the virtual device client. The virtual device server may then perform the synchronization operation by copying the one or more in-use regions of the virtual storage device to the second set of one or more storage devices.

Abstract: An apparatus and method for mapping memory addresses to reduce or avoid conflicting memory accesses in memory systems such as cache memories is described in connection with a multithreaded multiprocessor chip. A CMT processor reduces the probability of hot-spots in cache operations by hashing certain bits of a physical cache address to form a hashed cache address. By using exclusive OR functionality to hash the index bits, an efficient address transformation is achieved for indexing into an L2 cache memory.

Abstract: A method for optimizing the operation of a data storage system utilizes a genetic algorithm to adjust internal parameters of the system. The method involves determining a set of optimum values of each of two or more different data array parameters, such as data request types that will be processed concurrently, to achieve performance goals that are set by the user for the system. The optimum values are determined by iteratively evaluating the performance of the system while it processes the different combinations of values of the two or more data requests, saving the combinations of numbers that yield performance parameters that approach the goal and eliminating combinations of number of data request types that do not.

Abstract: An input/output data pipeline circuit of a semiconductor memory device includes a first transmitting unit, a control signal generating unit, and a second transmitting unit. The first transmitting unit receives data stored in a memory cell and transmits data to an input/output driver in response to activation of a first switching signal and a second switching signal. The control signal generating unit receives a clock signal from the semiconductor memory device and, corresponding to the frequency of the clock signal, outputs a control signal, the first switching signal, and the second switching signal. The second transmitting unit transmits data to the input/output driver in response to activation of the control signal. The first transmitting unit and the second transmitting unit are alternatively activated.

Abstract: A system and method for managing disk space in a thin-provisioned storage subsystem. If a number of free segments in a free segment pool at a storage subsystem is detected as below a desired minimum, one or more of the following is performed: selecting and adding logical devices (LDEVs) from an internal storage as free segments to the free segment pool, transitioning LDEVs to a virtual device (VDEV), and/or selecting and adding LDEVs from an external storage as free segments to the free segment pool. The transitioning includes identifying partially used or completely used LDEVs and transitioning these to the VDEV. Data migration may also occur by: selecting a source segment at a VDEV for migration, reading data from the source segment, writing the data to a target segment, the target segment being a free segment from the free segment pool, and assigning the target segment to the VDEV.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Abstract: The data processing system controls, from the database management system on a host computer, the storage device subsystem which stores log data supplied from the database management system; allocates on a disk cache in the storage device subsystem in advance a log-dedicated buffer area of a size equal to that of the log data output between checkpoints; writes log data into the buffer area; and, in the event of a host computer failure, reads out the log data from the disk cache without making access to a disk device. Since the log information required for the recovery of the data processing device is cached on the storage device side, the time it takes to read the necessary log information can be shortened, which in turn reduces the system recovery time.

Abstract: A system including a direct virtual memory access engine configured to request that data is stored in a memory, wherein a request for the data includes a I/O virtual address, a mapping table configured to store at least one entry includes a virtual-to-physical address mapping, a cache configured to store at least one tracking data structure associated with the at least one entry, and an input/output memory management unit storing the mapping table, operatively connected to the cache and configured to provide a physical address corresponding to the I/O virtual address to the direct virtual memory access engine, wherein the virtual-to-physical address mapping is generated prior to the direct virtual memory access engine requesting that data be stored, wherein the at least one entry and the at least one tracking structure persist for at least two direct memory address requests.

Abstract: A tape mirror interface comprises an input terminal coupled to at least one input node and capable of receiving data transfer requests, a plurality of output terminals coupled to a plurality of tape storage devices, and a control element coupled to the input terminal and plurality of output terminals. The control element presents the plurality of tape storage devices as separate media devices and selectively controls data transfer in a synchronous mode and a split mode. In the synchronous mode, writes to a target tape storage media are mirrored to a mirrored tape storage media. In the split mode, writes are written to tape storage devices independently.

Abstract: To provide a file system including: a storage system having a plurality of volumes; a volume allocation table adapted to set the plurality of volumes for each directory; a file allocation table that stores attributes and divided block information of the file; a block reading table in which numbers of blocks read out in one reading operation for each volume are respectively set; and a read control module that controls to read data from the volume; wherein a read control module, when a read command is received, determines a volume to be read from the volume allocation table, determines the number of blocks read for each volume by referring to the block reading table, determines the blocks read for each volume based on the volume, the number of blocks, and the block information, and reads from each volume in parallel.

Abstract: The storage system creates a volume for storing information specific to a user, and a volume for storing software shared by a plurality of users, links these volumes on the basis of the software usage status of the users, and virtually builds one region and supplies same to the users.

Abstract: A file is striped across multiple filers, file servers or other devices, to create a sparsely striped multi-component file. Each filer stores one sparse component. In particular, each component physically stores only those stripes allocated to that component. The other stripes are represented as holes. Thus, instead of contiguously packing each component's stripes at the block level, each component is a file having the same logical structure. A component of a sparsely striped multi-component file can be easily converted to a mirror by filling in its holes. Similarly, a mirror can be easily converted to one component of a sparsely striped multi-component file by removing or ignoring it unallocated stripes. In either case, the layout or logical of the component does not need to be reconfigured.

Abstract: A smart card contains potentially multiple applications, each containing an application identifier (AID). Each application also incorporates an AID interpreter for providing access to the AID. This is achieved by making a request to the AID interpreter to provide the AID for the application. In response, the AID interpreter retrieves a first component of the AID. This first component is logically internal to the AID interpreter. The AID interpreter also retrieves a second component of the AID. This second component is logically external to the AID interpreter and is indicative of a state relevant to the application, such as a current balance in the card. The first and second components of the AID are then combined in order to generate the AID for providing in response to the request.