Patents Examined by Hrayr A. Sayadian
  • Patent number: 10607860
    Abstract: A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 31, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin
  • Patent number: 10593751
    Abstract: An object of the present invention is to provide a semiconductor device capable of satisfactorily securing a breakdown voltage not only in a cell region but also in an edge termination region in a super junction structure. A semiconductor device according to the present invention includes a drift region of a first conductivity type and a pillar region of a second conductivity type a RESURF layer formed across a plurality of the pillar regions in an edge termination region and extending in the thickness direction from surfaces of the drift region and the pillar region, and a high-concentration region of the second conductivity type formed in a surface of the RESURF layer, the high-concentration region being higher in impurity concentration than the RESURF layer, no pillar region being formed under the high-concentration region in the thickness direction.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: March 17, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Hamada, Kohei Ebihara
  • Patent number: 10586732
    Abstract: A method includes forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer and forming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yann A. M. Mignot, Chih-Chao Yang
  • Patent number: 10578819
    Abstract: A surface light emitting semiconductor laser element, comprises a substrate, a lower reflector including a semiconductor multi-layer disposed on the substrate, an active layer disposed on the lower reflector, an upper reflector including a semiconductor multi-layer disposed on the active layer, a compound semiconductor layer having a first opening for exposing the upper reflector and extending over the upper reflector, and a metal film having a second opening for exposing the upper reflector disposed inside of the first opening and extending over the compound semiconductor layer, wherein the metal film and the compound semiconductor layer constitute a complex refractive index distribution structure where a complex refractive index is changed from the center of the second opening towards the outside. A method of emitting laser light in a single-peak transverse mode is also provided.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: March 3, 2020
    Assignee: Sony Corporation
    Inventors: Yoshiaki Watanabe, Hironobu Narui, Yuichi Kuromizu, Yoshinori Yamauchi, Yoshiyuki Tanaka
  • Patent number: 10573769
    Abstract: A back-illuminated energy ray detecting element 1 includes a semiconductor substrate and a protective film. The semiconductor substrate has a first principal surface as an energy ray incident surface and a second principal surface opposite to the first principal surface, and a charge generating region configured to generate an electric charge according to incidence of an energy ray is disposed on the second principal surface side. The protective film is disposed on the second principal surface side of the semiconductor substrate to cover at least the charge generating region, and includes silicon nitride or silicon nitride oxide. The protective film has a stress alleviating section configured to alleviate stress generated in the protective film.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: February 25, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Yasuhito Miyazaki, Kentaro Maeta, Masaharu Muramatsu
  • Patent number: 10564356
    Abstract: A heterogeneous semiconductor structure, including a first integrated circuit and a second integrated circuit, the second integrated circuit being a photonic integrated circuit. The heterogeneous semiconductor structure may be fabricated by bonding a multi-layer source die, in a flip-chip manner, to the first integrated circuit, removing the substrate of the source die, and fabricating one or more components on the source die, using etch and/or deposition processes, to form the second integrated circuit. The second integrated circuit may include components fabricated from cubic phase gallium nitride compounds, and configured to operate at wavelengths shorter than 450 nm.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Daniel N. Carothers
  • Patent number: 10566367
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a transfer transistor and a photodiode. The photodiode has an n type semiconductor region, an n+ type semiconductor region, and a second p type semiconductor region surrounded by a first p type semiconductor region of an interpixel isolation region. The n+ type semiconductor region is formed on the main surface side of the semiconductor substrate, and the n type semiconductor region is formed under the n+ type semiconductor region via the second p type semiconductor region. In the channel length direction of the transfer transistor, in the n type semiconductor region, an n?? type semiconductor region having a lower impurity density than that of the n type semiconductor region is arranged, to improve the transfer efficiency of electric charges accumulated in the photodiode.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yotaro Goto, Takeshi Kamino, Fumitoshi Takahashi
  • Patent number: 10566361
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: February 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Patent number: 10559504
    Abstract: High-mobility semiconductor fins are formed on an insulator layer using techniques allowing precise control of fin heights. Lattice-matched fins are grown epitaxially on sidewalls of an essentially defect-free portion of a semiconductor template. The fins are formed within laterally extending trenches in a top dielectric layer, the thickness of which determines fin height. The trenches extend orthogonally to the template. Epitaxial overgrowth above the top dielectric layer is removed by planarization. The fin template and top dielectric layer are removed, leaving sets of parallel fins on the insulator layer. The fin template can be replaced by an isolation region for electrically isolating sets of fins.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10553782
    Abstract: A passive magnetic device (PMD) has a base electrode, a multi-port signal structure (MPSS), and a substrate therebetween. The MPSS has a central plate residing in a second plane and at least two port tabs spaced apart from one another and extending from the central plate. The substrate has a central portion that defines a mesh structure between the base electrode and the central plate of the multi-port signal structure. A plurality of magnetic pillars are provided within the mesh structure, wherein each of the plurality of the magnetic pillars are spaced apart from one another and surrounded by a corresponding portion of the mesh structure. The PMD may provide a magnetically self-biased device that may be used as a radio frequency (RF) circulator, an RF isolator, and the like.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: February 4, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Andrew Arthur Ketterson, Xing Gu, Yongjie Cui, Xing Chen
  • Patent number: 10553577
    Abstract: A layout of a semiconductor device, a semiconductor device and a method of forming the same, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: February 4, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yu-Cheng Tung
  • Patent number: 10553661
    Abstract: A display substrate includes a data line extending in a first direction, a first transistor including a first channel area overlapping the data line and a first control electrode which overlaps the first channel area and has a substantially same shape as that of the first channel area in an overlap area in which the first control electrode overlaps the first channel area, a scan line extending in a second direction crossing the first direction, a first voltage line extending in the first direction and transfers a first driving signal, a first capacitor including an extension electrode which overlaps the first control electrode and extends in the second direction from the first voltage line and a second capacitor including an overlap electrode overlapping the data line.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sung-Eun Lee, Jin-Taek Kim, Ki-Wan Ahn, Joo-Sun Yoon, Yong-Jae Jang, Kwang-Young Choi
  • Patent number: 10546803
    Abstract: A semiconductor device includes an insulating circuit-substrate on which a semiconductor chip is mounted, a casing accommodating the insulating circuit-substrate, and a plate-shaped terminal-connecting member having both ends suspended so that the terminal-connecting member extends between two opposite side-walls of the casing, the terminal-connecting member having a connection-terminal and load-absorbing portions, the connection-terminal being provided in a central region between the both ends so as to be connected to the semiconductor chip, the load-absorbing portions being provided between fixing points to the casing and the central region, the rigidity of the load-absorbing portions in a longitudinal direction being equal to or less than 50% of the rigidity of the central region so that the load-absorbing portions absorb load applied from the two side-walls and are deformed.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: January 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tomonori Katano
  • Patent number: 10535653
    Abstract: A semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate, and a barrier layer between the work function metal and the gate. The isolation structure is disposed between the gate structures. The barrier layer covers a sidewall of the isolation structure.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jen Chen, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Hsin-Che Chiang
  • Patent number: 10529825
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact structure, a first dielectric layer, a first spacer, and a first connection structure. The gate structure is disposed on the semiconductor substrate. The source/drain region is disposed in the semiconductor substrate and disposed at a side of the gate structure. The source/drain contact structure is disposed on the source/drain region. The first dielectric layer is disposed on the source/drain contact structure and the gate structure. The first spacer is disposed in a first contact hole penetrating the first dielectric layer on the source/drain contact structure. The first connection structure is disposed in the first contact hole. The first connection structure is surrounded by the first spacer in the first contact hole, and the first connection structure is connected with the source/drain contact structure.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Patent number: 10522727
    Abstract: A light emitting apparatus includes a mount substrate; two or more light emitting devices mounted on the mount substrate such that adjacent light emitting devices face each other at lateral surfaces thereof; a light transparent member positioned on upper surfaces of the light emitting devices, the light transparent member having a plate shape and being positioned to receive incident light emitted from the light emitting devices; and a covering member. In a plan view, the light transparent member is larger than each of the light emitting devices. The covering member contains a light reflective material and covers at least a lateral surface of the light transparent member.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: December 31, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Shunsuke Minato, Masahiko Sano
  • Patent number: 10515912
    Abstract: Substrateless integrated circuit (IC) packages having a die with direct diagonal connections, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include: a die having a face with a plurality of contacts thereon, a dielectric layer in contact with the face, and a conductive pathway extending diagonally through the dielectric layer and coupling to an individual contact of the plurality of contacts on the die. In some embodiments, a conductive pathway may fan out to translate the contacts from a more dense layout to a less dense layout. In some embodiments, a conductive pathway may fan in to translate the contacts from a less dense layout to a more dense layout. In some embodiments, the dielectric layer and the conductive pathway may extend beyond the footprint of the die on one or more edges.
    Type: Grant
    Filed: September 24, 2017
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Min Suet Lim, Jiun Hann Sir, Eng Huat Eh Goh, Mooi Ling Chang
  • Patent number: 10510560
    Abstract: A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: December 17, 2019
    Assignees: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Eng Kian Kenneth Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Viet Cuong Nguyen
  • Patent number: 10504956
    Abstract: An image sensor includes a substrate and a plurality of infrared pixels formed in a front side of the substrate and configured to detect infrared light incident on the front side of the substrate. Each of the infrared pixels includes a photodiode, a region free of implants located above the photodiode, and a photogate formed over the substrate and above the photodiode. The image sensor also includes a plurality of color pixels dispersed among the infrared pixels, where each of the color pixels includes a pinned photodiode and is configured to detect visible light. The photodiode of each of the infrared pixels can include a deep charge-accumulation region underlying the pinned photodiode(s) of one or more neighboring color pixel(s). Methods of manufacturing also described and include forming the deep charge-accumulation regions and associated elements prior to forming any implant-blocking elements (e.g., polysilicon photogates) over the substrate.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 10, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: Takayuki Goto, Dajiang Yang, Keiji Mabuchi, Sohei Manabe
  • Patent number: 10483258
    Abstract: The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure that is essentially immune to latch-up and possess high ESD robustness and reliability. In an aspect, the present disclosure provides a mixed silicidation and selective epitaxy (epi) FinFET processes for latch-up immunity together with ESD robustness, thereby allowing achievement of ESD efficient parasitic structures together with latch-up immune and reliable functional devices. The present disclosure provides a dual silicidation scheme where ESD protection element(s) have fins that are partially silicided, and functional devices have fins that are fully silicided.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: November 19, 2019
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Mayank Shrivastava, Milova Paul, Harald Gossner