Patents Examined by Hrayr A. Sayadian
  • Patent number: 11373899
    Abstract: According to the present embodiment, the pattern generation device includes a misalignment value calculation unit configured to acquire a layout information, calculate a layout function from the layout information, and calculate a misalignment value by a convolution of the layout function and an integral kernel having a predetermined parameter, and a pattern correction unit configured to correct a pattern to generate a modified layout information using a calculated result by the misalignment value calculation unit, and output the modified layout information.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: June 28, 2022
    Assignee: Kioxia Corporation
    Inventors: Taiki Kimura, Tetsuaki Matsunawa
  • Patent number: 11355729
    Abstract: A highly reliable flexible light-emitting device is provided. The light-emitting device includes a first flexible substrate, a second flexible substrate, a light-emitting element between the first flexible substrate and the second flexible substrate, a first bonding layer; and a second bonding layer in a frame shape surrounding the first bonding layer. The first bonding layer and the second bonding layer are between the second flexible substrate and the light-emitting element. The light-emitting element includes layer containing a light-emitting organic compound between the pair of electrodes. The second bonding layer has a higher gas barrier property than the first bonding layer.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: June 7, 2022
    Inventors: Akihiro Chida, Tomoya Aoyama
  • Patent number: 11342373
    Abstract: A method for manufacturing an image sensing device includes forming an interconnection layer over a front surface of a semiconductor substrate. A trench is formed to extend from a back surface of the semiconductor substrate. An etch stop layer is formed along the trench. A buffer layer is formed over the etch stop layer. An etch process is performed for etching the buffer layer. The buffer layer and the etch stop layer include different materials.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chuang Wu, Ming-Tsong Wang, Feng-Chi Hung, Ching-Chun Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 11337010
    Abstract: The present disclosure describes techniques for altering the epoxy wettability of a surface of a MEMS device. Particularly applicable to flip-chip bonding arrangements in which a top surface of a MEMS device is adhered to a package substrate. A barrier region is provided on a top surface of the MEMs device, laterally outside a region which forms, or overlies, the backplate and/or the cavity in the transducer substrate. The barrier region comprises a plurality of discontinuities, e.g. dimples, which inhibit the flow of epoxy.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: May 17, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Marek Sebastian Piechocinski, Roberto Brioschi, Rkia Achehboune
  • Patent number: 11295981
    Abstract: Disclosed are semiconductor devices including through vias and methods of fabricating the same. The methods may include forming a first structure including a metal pattern and a second structure on the first structure. The metal pattern includes an upper surface facing the second structure. The methods may also include etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. After removing the oxidized first etch residue, the upper surface of the metal pattern may include a first portion that includes a recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 5, 2022
    Inventors: Yi Koan Hong, Taeseong Kim, Kwangjin Moon
  • Patent number: 11282852
    Abstract: A vertical memory device includes a gate line structure including a cell region in which a vertical channel structure is formed, and a first connection region and a second connection region which are respectively arranged at first and second ends of the cell region in a first direction. Each of the first connection region and the second connection region includes a first protrusion of the first gate line and a second protrusion of the second gate line which are parallel to a top surface of the substrate and arranged as steps in a second direction perpendicular to the first direction. The first protrusion of the second connection region is arranged diagonally from the first protrusion of the first connection region with respect to a center line of the cell region which is parallel to the first direction.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Bum Kim, Sung-Hoon Kim
  • Patent number: 11282784
    Abstract: The present disclosure provides a semiconductor package, including a first semiconductor structure, including an active region in a first substrate portion, wherein the active region includes at least one of a transistor, a diode, and a photodiode, a first bonding metallization over the first semiconductor structure, a first bonding dielectric over the first semiconductor structure, surrounding and directly contacting the first bonding metallization, a second semiconductor structure over a first portion of the first semiconductor structure, a second bonding metallization at a front surface of the second semiconductor structure, a second bonding dielectric surrounding and directly contacting the second bonding metallization, a conductive through via over a second portion of the first semiconductor structure different from the first portion, and a passive device directly over the conductive through via.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Chen-Hua Yu
  • Patent number: 11276630
    Abstract: Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Sanka Ganesan
  • Patent number: 11271160
    Abstract: A technology called RINSE (Removal of Incubated Nanotubes through Selective Exfoliation) is demonstrated. RINSE removes carbon nanotube (CNT) aggregates in CNFETs without compromising CNFET performance. In RINSE, CNTs are deposited on a substrate, coated with a thin adhesive layer, and sonicated. The adhesive layer is strong enough to keep the individual CNTs on the substrate, but not the larger CNT aggregates. When combined with a CNFET CMOS process as disclosed here, record CNFET CMOS yield and uniformity can be realized.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: March 8, 2022
    Assignee: Massachusetts Institute of Technology
    Inventors: Christian Lau, Max Shulaker
  • Patent number: 11271026
    Abstract: Imaging devices and electronic apparatuses incorporating imaging devices or image pick-up elements are provided. An imaging device as disclosed can include a substrate, a first opto-electronic converter having a first area formed in the substrate, and a second opto-electronic converter having a second area formed in the substrate. The first area is larger than the second area. In addition, a light blocking wall can extend from a first surface of the substrate such that at least a portion of the light blocking wall is between the first opto-electronic converter and the second opto-electronic converter.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: March 8, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Takeshi Yanagita, Taichi Natori, Hirotsugu Takahashi, Shunsuke Maruyama, Yasushi Maruyama
  • Patent number: 11257996
    Abstract: A light emitting apparatus includes: a mount substrate; a first light emitting device mounted on the mount substrate; a light transparent member, wherein a lower surface of the light transparent member is attached to an upper surface of the first light emitting device via an adhesive material, wherein the light transparent member has a plate shape and is positioned to receive incident light emitted from the first light emitting device, and wherein a first lateral surface of the light transparent member is located laterally inward of a lateral surface of the first light emitting device; and a covering member that contains a light reflective material and covers at least the lateral surface of the light transparent member.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: February 22, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Shunsuke Minato, Masahiko Sano
  • Patent number: 11257896
    Abstract: A display device is disclosed, and the display device includes a substrate including first to third display regions, the second and the third display regions being spaced from each other, each of the second and third display regions having an area smaller than that of the first display region and being continuous to the first display region, first to third pixels in the first to third display regions, first to third lines connected to the first to third pixels, and a dummy part configured to compensate for a difference between a load value of the first lines and load values of the second and third lines, wherein the second display region includes a first sub-region adjacent to the first display region and a second sub-region spaced from the first display region, and the third display region includes a third sub-region adjacent to the first display region and a fourth sub-region spaced from the first display region.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 22, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyung Jun Park, Yang Wan Kim, Byung Sun Kim, Su Jin Lee, Jae Yong Lee, Ji Hyun Ka, Tae Hoon Kwon, Jin Tae Jeong, Seung Ji Cha
  • Patent number: 11251326
    Abstract: The invention relates to a method of fabrication of a photonic chip 1 comprising an avalanche photodiode 20 of the SACM type optically coupled to an integrated waveguide 40, comprising a step for forming a first spacer 24 allowing a constant peripheral recessing drzc of the charge region 23 to be defined later on with respect to an edge of the multiplication portion 22, then a step for forming a second spacer 26 allowing a constant peripheral recessing drpa of the absorption portion 27 to be defined later on with respect to an edge of the charge region 23.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: February 15, 2022
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Bertrand Szelag, Laetitia Adelmini, Stephane Brision
  • Patent number: 11244855
    Abstract: Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, a sacrificial layer may be deposited in a trench that forms a serpentine shape. Portions of the sacrificial layer may be removed to form openings, into which cell material is deposited. An insulative material may be formed in contact with the sacrificial layer. The conductive pillars extend substantially perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. A chalcogenide material may be formed in the recesses partially around the conductive pillars.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: February 8, 2022
    Inventors: Lorenzo Fratin, Enrico Varesi, Paolo Fantini
  • Patent number: 11239326
    Abstract: A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: February 1, 2022
    Assignee: RAYTHEON COMPANY
    Inventors: Jeffrey R. LaRoche, Kelly P. Ip, Thomas E. Kazior, Kamal Tabatabaie Alavi
  • Patent number: 11239333
    Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 11227960
    Abstract: One illustrative optical device disclosed herein includes a base layer comprising a semiconductor material and a photodetector-coupler that comprises a detector-coupler element. The device also includes a first diode structure that is positioned in the detector-coupler element and a second diode structure that is positioned in the base layer, wherein the second diode structure is positioned vertically below at least a portion of detector-coupler element.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: January 18, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob
  • Patent number: 11195952
    Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: December 7, 2021
    Inventors: Sung Min Kim, Hyo Jin Kim, Dae Won Ha
  • Patent number: 11195845
    Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: December 7, 2021
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
  • Patent number: 11177465
    Abstract: Devices, structures, materials and methods for vertical light emitting transistors (VLETs) and light emitting displays (LEDs) are provided. In particular, architectures for vertical polymer light emitting transistors (VPLETs) for active matrix organic light emitting displays (AMOLEDs) and AMOLEDs incorporating such VPLETs are described. Porous conductive transparent electrodes (such as from nanowires (NW)) alone or in combination with conjugated light emitting polymers (LEPs) and dielectric materials are utilized in forming organic light emitting transistors (OLETs). Combinations of thin films of ionic gels, LEDs, porous conductive electrodes and relevant substrates and gates are utilized to construct LETs, including singly and doubly gated VPLETs. In addition, printing processes are utilized to deposit layers of one or more of porous conductive electrodes, LEDs, and dielectric materials on various substrates to construct LETs, including singly and doubly gated VPLETs.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: November 16, 2021
    Assignee: Atom H2O, LLC
    Inventor: Huaping Li