Abstract: A semiconductor memory device includes a memory array provided above a substrate in a first direction intersecting a surface of the substrate. A first peripheral circuit is provided between the substrate and the memory array. A second peripheral circuit is provided between the substrate and the memory array and apart from the first peripheral circuit in a second direction parallel to the surface of the substrate. A sense amplifier is provided between the substrate and the memory array and between the first and second peripheral circuits, and a word line switch circuit extending in the second direction is also provided. A length of the second peripheral circuit in the second direction is smaller than half of a length of the sense amplifier in the second direction.

Abstract: Techniques to form self-aligned lateral contacts. In an example, a first trench contact contacts a source or drain region of a transistor. A second trench contact includes non-contiguous first and second portions, each portion having a top surface that is co-planar with a top surface of the first trench contact as well as a top surface of the gate structure. A sidewall of the second trench contact is self-aligned to, and interfaces with, a sidewall of the first trench contact. A via extends from the first portion of the second trench contact to an underlying power rail. In some cases, the second portion of the second trench contact extends over a source or drain region of another transistor, without contacting that source or drain region. The fly-over portion of the second trench contact has a maximum height that is shorter than a maximum height of the first trench contact.

Abstract: A method of operating a microelectromechanical system (MEMS) includes, in a first operational mode, converting an analog output of the MEMS into a first internal data stream and a first external data stream having a first sampling rate; transitioning from the first operational mode to a second operation mode without restarting the MEMS; and in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and performing a sampling rate conversion of the second internal data stream to generate a second external data stream.

Abstract: A dynamic random access memory device includes a substrate having a first active region, a first isolation region, a second active region, and a second isolation region arranged in order along a first direction. A first bit line is disposed on the first active region and in direct contact with the first active region. A second bit line is disposed on the second isolation region. An insulating layer is disposed between and separate the second bit line and the second isolation region. A storage node contact structure is disposed between the first bit line and the second bit line and is in direct contact with a top surface of the second active region, a sidewall of the first isolation region, and a sidewall of the second isolation region.

Abstract: A micro-electro-mechanical systems (MEMS) die includes a piston; an electrode facing the piston, wherein a capacitance between the piston and the electrode changes as the distance between the piston and the electrode changes; and a resilient structure (e.g., a gasket or a pleated wall) disposed between the piston and the electrode, wherein the resilient structure supports the piston and resists the movement of the piston with respect to the electrode. A back volume is bounded by the piston and the resilient structure and the resilient structure blocks air from leaving the back volume. The piston may be a rigid body made of a conductive material, such as metal or a doped semiconductor. The MEMS die may also include a second resilient structure, which provides further support to the piston and is disposed within the back volume.

Abstract: A semiconductor device includes: a substrate; a conductive line extending on the substrate in a first horizontal direction; an isolation insulating layer extending on the substrate and the conductive line in a second horizontal direction intersecting with the first horizontal direction, and defining a channel trench extending through the isolation insulating layer from an upper surface of the isolation insulating layer to a lower surface of the isolation insulating layer; a crystalline oxide semiconductor layer extending along at least a portion of an inner side surface of the channel trench and at least a portion of a bottom surface of the channel trench and coming in contact with the conductive line; and a gate electrode extending on the crystalline oxide semiconductor layer inside the channel trench in the second horizontal direction.

Abstract: A semiconductor device includes a semiconductor substrate with active regions and a first buried metal layer provided below the semiconductor substrate. The first buried metal layer includes a first buried conductive rail, a first set of buried conductive fingers that extends from the first buried conductive rail, and a second set of buried conductive fingers that are interleaved with the first set of buried conductive fingers. The first set and the second set of buried conductive fingers extends beneath more than one of the active regions. In this manner, the first set and the second set of buried conductive fingers can be utilized to distribute different voltages, such as an ungated reference voltage TVDD and a gated reference voltage VVDD in a header circuit with reduced resistance.

Abstract: A microelectromechanical system (MEMS) device contains a movable MEMS structure, a first support structure in which an edge of the MEMS structure is attached, a cavity which is bounded by the MEMS structure and the first support structure, and a second support structure which is attached in the cavity and at the edge of the MEMS structure and is configured so as to support the edge of the MEMS structure mechanically.

Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.

Abstract: A memory device includes a first programming gate-strip for a first anti-fuse structure and a second programming gate-strip for a second anti-fuse structure. In the memory device, a terminal conductor overlies a terminal region between the channel regions of a first transistor and a second transistor. The memory device also includes a group of first programming conducting and a group of second programming conducting lines. The first programming conducting lines are conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors. The second programming conducting lines are conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors.

Abstract: In a semiconductor memory device, a first plane includes a first memory cell array provided above a substrate in a first direction. A first power supply circuit is provided between the substrate and the first memory cell array, and a first sense amplifier is provided between the substrate and the first memory cell array. A second plane includes a second memory cell array provided above the substrate and a second power supply circuit provided between the substrate and the second memory cell array. A second sense amplifier is provided between the substrate and the second memory cell array. When viewed in the first direction, the first power supply circuit and the first sense amplifier overlap the first memory cell array, and the second power supply circuit and the second sense amplifier overlap the second memory cell array.

Abstract: An integrated semiconductor device includes a silicon body that includes <111> single crystal silicon, a semiconductor device that is disposed within the silicon body, a III-nitride body disposed on the silicon body, and a III-nitride device that is disposed within the III-nitride body, wherein the semiconductor device is operatively coupled to the III-nitride device.

Abstract: A microelectromechanical system includes a lower membrane including a plurality of troughs and crests arranged alternately, an upper membrane including a plurality of troughs and crests arranged alternately, and a spacer layer disposed between the lower membrane and the upper membrane. The spacer layer includes counter electrode walls and support walls made of nitride, the counter electrode walls being provided with conductive elements. Chambers are formed between the troughs of the lower membrane and the crest of the upper membrane and the counter electrode walls are suspended in the chambers respectively. The support walls are sandwiched between the crests of the lower membrane and the troughs of the upper membrane with a space formed between adjacent support walls. The spaces between adjacent support walls may be empty or filled with oxide. Unwanted capacitance between the upper and lower membranes is reduced significantly.

Abstract: According to one embodiment, a semiconductor memory device includes a first cell region including a plurality of memory cells, a second cell region including a plurality of memory cells, a connection region between the first cell region and the second cell region, and a row decoder for propagating a voltage to word lines in the first and second cell regions via the connection region.

Abstract: The present technology relates to a solid-state imaging device, a manufacturing method, and an electronic device, which can improve sensitivity while improving color mixing. The solid-state imaging device includes a first wall provided between a pixel and a pixel arranged two-dimensionally to isolate the pixels, in which the first wall includes at least two layers including a light shielding film of a lowermost layer and a low refractive index film of which refractive index is lower than the light shielding film. The present technology can be applied to, for example, a solid-state imaging device, an electronic device having an imaging function, and the like.

Abstract: A heterogeneous semiconductor structure, including a first integrated circuit and a second integrated circuit, the second integrated circuit being a photonic integrated circuit. The heterogeneous semiconductor structure may be fabricated by bonding a multi-layer source die, in a flip-chip manner, to the first integrated circuit, removing the substrate of the source die, and fabricating one or more components on the source die, using etch and/or deposition processes, to form the second integrated circuit. The second integrated circuit may include components fabricated from cubic phase gallium nitride compounds, and configured to operate at wavelengths shorter than 450 nm.

Abstract: Methods for selective deposition are described herein. Further, methods for improving selectivity comprising an ammonia plasma pre-clean process are also described. In some embodiments, a silyl amine is used to selectively form a surfactant layer on a dielectric surface. A ruthenium film may then be selectively deposited on a conductive surface. In some embodiments, the ammonia plasma removes oxide contaminations from conductive surfaces without adversely affecting the dielectric surface.

Abstract: The application discloses a semiconductor device and a semiconductor device manufacturing method. The semiconductor device includes: a substrate; a circuit macro on the substrate; a plurality of metal layers over the substrate, wherein the plurality of metal layers include a first power mesh; and a plurality of power switch circuits on the substrate, wherein the power switch circuits selectively couple a power to the first power mesh according to a control signal, and the power switch circuits are arranged in sequence, wherein a control signal output terminal of each first power switch circuit is coupled to a control signal input terminal of a following first power switch circuit, so that the control signal passes through the first power switch circuits sequentially.

Abstract: Disclosed herein are related to an integrated circuit having a dual power structure with an efficient layout and a method of forming the integrated circuit. In one aspect, the integrated circuit includes a substrate, a first layer facing the substrate, and a second layer facing the first layer. In one aspect, the first layer includes a set of first metal rails, where each of the set of first metal rails may be separated from its adjacent one of the set of first metal rails according to a uniform pitch along a direction. In one aspect, the second layer includes a set of second metal rails, where the set of second metal rails may include two adjacent second metal rails separated according to a first pitch along the direction and additional two adjacent second metal rails separated according to a second pitch along the direction.

Abstract: A method of fabricating a magnetoresistive device includes forming a magnetically fixed region on one side of an intermediate region. Forming the magnetically fixed region may include forming a first ferromagnetic region and forming an antiferromagnetic coupling region on one side of the first ferromagnetic region. The method may also include treating a surface of the coupling region by exposing the surface to a gas, and forming a second ferromagnetic region on the treated surface of the coupling region.