Patents Examined by Hsin-Yi Hsieh
  • Patent number: 8084815
    Abstract: A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners surrounding the active region. The active region includes an active n region and active p pillars having vertical stripe shapes disposed at regular intervals in the active n region. The top and bottom ends of the active p pillars are separated from the edge p pillar. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar. Surplus p charges that are not used to balance the quantity of p charges and the quantity of n charges among p charges included in the upper and lower parts of the edge p pillar are eliminated or n charges are supplemented to balance the quantity of p charges and the quantity of n charges.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: December 27, 2011
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Jae-gil Lee, Jin-young Jung, Ho-cheol Jang, Chong-man Yun
  • Patent number: 8076694
    Abstract: It is an object of the present invention to provide a nitride semiconductor element, which uses Si as a substrate, and whose voltage in the forward direction (Vf) is lower than in the prior art. In the nitride semiconductor element which has a nitride semiconductor layer over an Si substrate, at least a portion of the Si substrate and the nitride semiconductor layer are included in an current pass region, and the electrical conductivity type of the current pass region on the Si substrate is p-type. Furthermore, in the nitride semiconductor element which has a nitride semiconductor layer over an Si substrate, at least a portion of the Si substrate and the nitride semiconductor layer are included in an current pass region, and the majority carriers of the current pass region of the Si substrate are holes.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: December 13, 2011
    Assignee: Nichia Corporation
    Inventors: Yukio Narukawa, Tomotsugu Mitani, Masatsugu Ichikawa, Akira Kitano, Takao Misaki
  • Patent number: 8053855
    Abstract: A CMOS image sensor for improving light sensitivity and peripheral brightness ratio, and a method for fabricating the same. The CMOS image sensor includes a substrate on which a light sensor and device isolating insulation films are formed, in which the top of the substrate is coated with a plurality of metal layers and oxide films; a plurality of reflective layers formed inside the metal layers, each being spaced apart; a color filter embedded in a groove formed by etching the oxide films inside the reflective layers by a predetermined thickness; a plurality of protrusions formed on both sides of the top of the color filter, each arranged at a predetermined distance from one another; a flat layer formed on the top of the protrusions and the oxide films; and a micro-lens formed on the top of the flat layer. The reflective layer disposed at the top of the photodiode is made of a material having a high reflectance and low absorptivity.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-ho Nam, Jin-hwan Kim, Gee-young Sung
  • Patent number: 8044450
    Abstract: A semiconductor device comprising a resistance element with a high resistance and high resistance accuracy and a non-volatile semiconductor storage element is rationally realized by comprising the non-volatile semiconductor storage element comprising a first isolation formed to isolate a first semiconductor area, a first insulator, and a first electrode in a self-aligned manner, and a second electrode, and the resistance element comprising a second isolation formed to isolate a second semiconductor area, a third insulator and a conductor layer in a self-aligned manner, and third and fourth electrodes formed on each end of the conductor layer via a fourth insulator, and connected with the conductor layer. The conductor layer or the third and fourth electrodes include the same material with the first or second electrode, respectively.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Noguchi, Susumu Yoshikawa, Koichi Fukuda