Abstract: A storage device includes: a non-volatile memory; a parameter storage unit that stores a plurality of parameters for setting different operating conditions in the non-volatile memory; an access pattern analysis unit that analyzes an access pattern indicating a tendency to access the non-volatile memory by a command from a host device; a parameter selection unit that selects an optimal parameter from among the plurality of parameters based on the access pattern analyzed by the access pattern analysis unit; and an access control unit that accesses the non-volatile memory in a state where the optimal parameter is set in the non-volatile memory.

Abstract: Omitting or obfuscating physical memory addresses within an execution trace. A microprocessor identifies a first translation lookaside buffer (TLB) entry mapping a first virtual memory page to a physical memory page, and initiates logging of the first TLB entry by initiating logging of at least a first virtual address of the first virtual memory page and a first identifier. The microprocessor identifies a second TLB entry mapping a second virtual memory page to the physical memory page, and initiates logging of the second TLB entry by initiating logging of at least a second virtual address of the second virtual memory page and a second identifier. The microprocessor determines that the first and second TLB entries are each live, logged into the execution trace, and mapped to the same physical address, and ensures that the execution trace indicates that the first and second TLB entries each map to the physical address.

Abstract: Systems, methods, and a multipath initiator for a data storage device array that presents a single path host interface are described. The multipath initiator includes at least two backend paths to multiport data storage devices and a single path host interface. The initiator may determine a queue pair identifier for a host connection and storage commands to that host connection. The initiator may assign a path identifier, such as for a first backend path or a second backend path, to use for storage commands and send the storage commands to the data storage devices using the selected backend path.

Abstract: A method includes: creating a logical-to-physical address translation (L2P) bitmap for each respective virtual block programmed across a plane of multiple dice of a memory device, each L2P bitmap identifying logical addresses, within each respective L2P table of a plurality of L2P tables, that belong to a respective virtual block; creating a virtual block (VB) bitmap for each respective L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table, of the plurality of L2P tables, based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular virtual block; and identifying and updating, by the processing device, an L2P bitmap associated with the particular virtual block for an L2P mapping corresponding to the entry.

Abstract: Data routing for efficient decompressor use is described. In accordance with the described techniques, a cache controller receives requests from multiple requestors for elements of data stored in a compressed format in a cache. The requests include at least a first request from a first requestor and a second request from a second requestor. A decompression routing system identifies a redundant element of data requested by both the first requestor and the second requestor and causes decompressors to decompress the requested elements of data. The decompression includes performing a single decompression of the redundant element. After the decompression, the decompression routing system routes the decompressed elements to the plurality of requestors, which includes routing the decompressed redundant element to both the first requestor and the second requestor.

Abstract: In some examples, based on the information relating to the wear of physical memories in computer nodes of the distributed system, a system initiates a migration of a memory page from a first physical memory in a first computer node to a second physical memory in a second computer node. As part of the migration, the system updates a mapping between a first address space accessible by programs in the distributed system and a physical address space comprising memory locations in the physical memories.

Abstract: A data search apparatus includes a logical search circuit and a memory, and the logical search circuit is connected to the memory through a databus. The databus can access all memory resources, and each part of databus resource can access all the memory resources. A logical search resource provided by the logical search circuit can be divided into a plurality of parts as required, and each part of logical resource can access node data in the memory through the bus resource.

Abstract: An integrated circuit device includes a first memory to support address translation between local addresses and fabric addresses and a processing circuit, operatively coupled to the first memory. The processing circuit allocates, on a dynamic basis as a donor, a portion of first local memory of a local server as first far memory for access for a first remote server, or as a requester receives allocation of second far memory from the first remote server or a second remote server for access by the local server. The processing circuit bridges the access by the first remote server to the allocated portion of first local memory as the first far memory, through the fabric addresses and the address translation supported by the first memory, or bridge the access by the local server to the second far memory, through the address translation supported by the first memory, and the fabric addresses.

Abstract: In at least one embodiment, processing can include: storing a metadata page at new physical location PA2 on non-volatile storage; and recording in a translation table (TT) log, a TT update to a mapping entry E1 of the TT, wherein the TT update updates E1 of the TT to map a logical address LA1 of the metadata page to PA2. Recording can include querying a unified hash table (UHT) in accordance with LA1 to determine whether the UHT includes a UHT entry mapping LA1 to a corresponding physical address or location of where the MD page is stored on non-volatile storage. Responsive to determining that the UHT includes a UHT entry for LA1, processing can include: determining whether the UHT entry is a cache type. If the UHT entry is the cache type, processing can include converting the UHT entry to a delta type entry of the TT log.

Abstract: A method includes receiving, by a memory management unit (MMU) comprising a translation lookaside buffer (TLB) and a configuration register, a request from a processor core to directly modify an entry in the TLB. The method also includes, responsive to the configuration register having a first value, operating the MMU in a software-managed mode by modifying the entry in the TLB according to the request. The method further includes, responsive to the configuration register having a second value, operating the MMU in a hardware-managed mode by denying the request.

Abstract: The present application provides a sequential read prefetching method and apparatus based on an Inspur Cluster File System (ICFS) distributed block storage system, a device, and a non-volatile readable storage medium. The method includes: in response to an OSD receiving a read request issued by a client, determining whether the read request is a sequential read request; in response to the read request being the sequential read request, creating a prefetching sliding window according to a data object to be read in the read request; in response to completion of the creation of the prefetching sliding window, calculating, according to the data object to be read in the read request, anew volume object needing to be prefetched; and adding the calculated new volume object needing to be prefetched into a queue of objects to be prefetched of the prefetching sliding window and executing prefetching.

Abstract: An object storage system includes mass storage devices that implement general storage for objects stored in the object storage system and additionally includes other storage devices, such as solid-state drives, that provide higher performance storage access. The object storage system implements a common access interface for accessing both accelerated access objects (who are eligible to have cached copies stored on the higher performance storage devices) and non-accelerated access objects stored in the general storage. The cache is fully managed by the service and no changes are required for client applications to receive accelerated access to objects that are classified as accelerated access objects per a customer configurable acceleration policy for the object or for a bucket in which the object is stored.

Abstract: A memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. The memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. The physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the configuration data in response to the memory controller completing a save operation.

Abstract: In response to generating one or more speculative prefetch requests for a last-level cache, a processor determines prefetch analytics for the generated speculative prefetch requests and compares the determined prefetch analytics of the speculative prefetch requests to selection thresholds. In response to a speculative prefetch request meeting or exceeding a selection threshold, the processor selects the speculative prefetch request for issuance to a memory-side cache controller. When one or more system conditions meet one or more condition thresholds, the processor issues the selected speculative prefetch request to the memory-side cache controller. The memory-side cache controller then retrieves the data indicated in the selected speculative prefetch request from a memory and stores it in a memory-side cache in the data fabric coupled to the last-level cache.

Abstract: Deferred memory page allocation commands and non-deferred memory page allocation commands are identified within host I/O commands received by a data storage system. For each one of those received host I/O commands that are identified as a deferred memory page allocation command, QoS (Quality of Service) policy enforcement is performed before any memory pages are allocated by the data storage system to store host data indicated by the received command. Host I/O commands that are identified as deferred memory page allocation commands include read commands, and host I/O commands that are identified as non-deferred memory page allocation commands include in-capsule write commands. For commands identified as deferred memory page allocation commands, enforcing QoS policy before any memory pages are allocated to store host data indicated by the command avoids the possibility of enqueueing the allocated memory pages onto the QoS wait queue, thus conserving data storage system memory resources.

Abstract: A method for operating a computational storage device includes receiving by a storage controller and from a host device: (1) a compute namespace setting instruction instructing the setting of a compute namespace; (2) a latency threshold value related to the compute namespace; (3) a program; (4) a first execute command using the program; and (5) a second execute command using the program. Additionally, the method includes transmitting, by the storage controller and to the host device, a latency message in response to the second execute command.

Abstract: The present disclosure generally relates to memory management during SGL fetching. When a data storage device is required to fetch an SGL from a host device, the data storage device cannot determine how much memory will be required to be allocated. The disclosure herein reduces the impact of the problem of under or over allocating memory and over-fetching, thereby reducing performance of the device during transfers. The disclosure provides guidance on how to implement an adaptive learning process based upon statistic collection of SGL fetches. By maintaining a table of statistics, the data storage device controller may learn and more closely predict an amount of memory to allocate for SGL fetching.

Abstract: In one embodiment, a processing device includes a memory to store a plurality of memory pages having corresponding physical memory addresses in the memory, store an active multilevel page table (MPT) mapping virtual to physical memory addresses for corresponding allocated memory pages stored in the memory, and store a floating MPT at least partially mapping virtual to physical memory addresses for corresponding spare memory pages stored in the memory, the floating and active MPT using a common mapping scheme, and a processor to receive a request to add a virtual to physical address mapping for more memory pages of the plurality of memory pages to the active MPT, and in response to receiving the request, adjoin at least part of the floating MPT to the active MPT so that the active MPT provides the virtual to physical address mapping for at least some memory pages of the spare memory pages.

Abstract: A technique for signal deskew at the non-volatile memory side. The non-volatile memory includes a plurality of dies and a signal timing adjustment circuit. The dies are grouped into storage zones. A controller is coupled to the non-volatile memory through a plurality of data lines. Through the data lines, the controller issues a plurality of commands to provide zone delay parameters to the non-volatile memory to drive the signal timing adjustment circuit at the non-volatile memory side to separately adjust data-line timing of the different storage zones.

Abstract: System creates mapping of storage intent, defined for digital asset, to primary storage tier, of primary storage tiers in primary protection storage system, that matches storage intent. System receives request to store copy of digital asset, and stores the copy with storage intent in primary storage tier, based on mapping of storage intent to primary storage tier. System identifies expanded group of storage tiers comprising primary storage tiers combined with additional storage tier. If additional storage tier matches storage intent more than primary storage tier matches storage intent, which is mapped to primary storage tier, system changes mapping of storage intent to primary storage tier into mapping of storage intent, defined for digital asset, to additional storage tier. System relocates each copy of digital asset, based on mapping of storage intent to primary storage tier, to additional storage tier, based on mapping of storage intent to additional storage tier.