Patents Examined by Hua J Song
  • Patent number: 12147342
    Abstract: A storage system includes at least one solid-state drive (SSD) and a baseboard management controller (BMC). The at least one SSD communicates over a communication link information that the at least one SSD includes a predetermined number of super capacitors in which the predetermined number includes 0, and is capable of providing a mode of operation to flush data in a non-volatile memory to a non-volatile memory that spans a predetermined amount of time if a loss of power condition is detected. The BMC device receives the information from the SSD and in response sends a message to the at least on SSD to enter the mode of operation.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: November 19, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wentao Wu, Sompong Olarig, William Schwaderer, Ramdas Kachare
  • Patent number: 12147351
    Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: November 19, 2024
    Assignee: Rambus Inc.
    Inventors: Evan Lawrence Erickson, Christopher Haywood, Mark D. Kellam
  • Patent number: 12147670
    Abstract: A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table regions and associated apparatus are provided.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: November 19, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Chien-Cheng Lin, Chang-Chieh Huang
  • Patent number: 12141449
    Abstract: A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: November 12, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: John Martin Hayes, Robert Lee, John Colgrove, John D. Davis
  • Patent number: 12141444
    Abstract: An example computer-implemented method for mirroring memory in a disaggregated memory clustered environment is provided. The method includes assigning, by a hypervisor, a disaggregated memory to a virtual machine comprising a remote disaggregated memory, the virtual machine being one node of a cluster of the disaggregated memory clustered environment. The method further includes allocating, by a disaggregated memory manager, a mirrored memory for the remote disaggregated memory to mirror the remote disaggregated memory on an alternate node of the cluster of the disaggregated memory clustered environment. The method further includes responsive to a memory access occurring, maintaining, by the disaggregated memory manager, the mirrored memory. The method further includes, responsive to detecting a memory allocation adjustment, modifying, by the disaggregated memory manager, memory usage across the cluster.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: November 12, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adam Thomas Stallman, Suresh Guduru, Ryan K. Cradick
  • Patent number: 12135891
    Abstract: A storage service supports attachment of multiple clients to a distributed storage object and further supports persistent reservations that govern types of access the respective clients are granted with respect to the distributed storage object. In order to efficiently distribute reservation state changes to multiple partitions of the distributed storage object hosted by different data storage units/servers, existing connections are used between the data storage units/servers hosting the partitions of the distributed storage object and the connected clients to propagate reservation state changes.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: November 5, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Swapnil Vinay Dinkar, Pradeep Kunni Raman, David Matthew Buches, Hon Ping Shea, Norbert Paul Kusters
  • Patent number: 12131068
    Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for synchronously accessing data. The method may include sending metadata associated with data to be moved by a user to a programmable network device associated with a persistent memory containing the data, so as to enable the programmable network device to move the data based on the metadata, wherein the programmable network device is a smart network interface card having a remote direct memory access function. The method may also include entering a hibernation state. In addition, the method may include exiting from the hibernation state in response to receiving a confirmation of operation completion from the programmable network device, so as to notify the user that an operation of moving the data is complete.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: October 29, 2024
    Assignee: DELL PRODUCTS L.P.
    Inventors: Tao Chen, Ran Liu, Wei Lu
  • Patent number: 12124705
    Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: October 22, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Pitamber Shukla, Ching-Huang Lu, Devin Batutis
  • Patent number: 12124724
    Abstract: Embodiments of this application provide a memory migration method, an apparatus, and a computing device.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: October 22, 2024
    Assignee: Alibaba Group Holding Limited
    Inventor: Dianchen Tian
  • Patent number: 12124376
    Abstract: A method for providing elastic columnar cache includes receiving cache configuration information indicating a maximum size and an incremental size for a cache associated with a user. The cache is configured to store a portion of a table in a row-major format. The method includes caching, in a column-major format, a subset of the plurality of columns of the table in the cache and receiving a plurality of data requests requesting access to the table and associated with a corresponding access pattern requiring access to one or more of the columns. While executing one or more workloads, the method includes, for each column of the table, determining an access frequency indicating a number of times the corresponding column is accessed over a predetermined time period and dynamically adjusting the subset of columns based on the access patterns, the maximum size, and the incremental size.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: October 22, 2024
    Assignee: Google LLC
    Inventors: Anjan Kumar Amirishetty, Xun Cheng, Viral Shah
  • Patent number: 12124381
    Abstract: A processing system includes a hardware translation lookaside buffer (TLB) retry loop that retries virtual memory address to physical memory address translation requests from a software client independent of a command from the software client. In response to a retry response notification at the TLB, a controller of the TLB waits for a programmable delay period and then retries the request without involvement from the software client. After a retry results in a hit at the TLB, the controller notifies the software client of the hit. Alternatively, if a retry results in an error at the TLB, the controller notifies the software client of the error and the software client initiates error handling.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: October 22, 2024
    Assignee: ATI Technologies ULC
    Inventor: Edwin Pang
  • Patent number: 12118215
    Abstract: This application is directed to dynamic management of memory read request in a memory system of an electronic device. The electronic device identifies a queue of memory access requests to access the memory system. The queue of memory access requests including at least one host read request and a current system read request. The electronic device monitors a workload condition of the memory system based on the queue of memory access requests, and generates at least a first system read request and a second system read request from the current system read request based on the workload condition of the memory system. The queue of memory access requests is updated by inserting the at least one host read request after the first system read request and before the second system read request.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: October 15, 2024
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Sarvesh Varakabe Gangadhar, Mark Anthony Golez, Jacky Le
  • Patent number: 12118220
    Abstract: A system includes a memory and at least one processing device, operatively coupled to the memory, to perform operations including causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device. The PMR utilizes a power protection mechanism to prevent data loss in an event of power loss.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: October 15, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Joseph H. Steinmetz, Luca Bert, William Akin
  • Patent number: 12118227
    Abstract: Two storage arrays, a primary storage array and a remote storage array, are configured to implement a remote data replication facility, in which both the storage arrays are active, such that hosts can both read and write data to both the primary storage array and remote storage array. If the host would like to add storage, the host sends a command to one of the storage arrays to add a storage volume. The first storage array that receives the command locally creates the requested storage volume and coordinates with the second storage array to also locally create the requested storage volume. While the storage volumes are being created and formatted, the first and second storage arrays coordinate status responses to the host. Once the requested storage volumes is ready on both storage arrays, the storage volume is made accessible to the host on both storage arrays.
    Type: Grant
    Filed: April 15, 2023
    Date of Patent: October 15, 2024
    Assignee: Dell Products, L.P.
    Inventors: Jaeyoo Jung, Ben Yoder, Jeffrey Wilson
  • Patent number: 12117932
    Abstract: A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table update and associated apparatus are provided. The method may include: utilizing a memory controller to receive a plurality of host commands from a host device through a transmission interface circuit of the memory controller, receive a set of first data and a set of second data with first and second active blocks according to first and second commands among the host commands, respectively, and update first and second temporary physical-to-logical (P2L) address mapping tables; and in response to a table region of any temporary P2L address mapping table being full, updating a first P2L address mapping table according to the first temporary P2L address mapping table and selectively updating a second P2L address mapping table according to the second temporary P2L address mapping table, for performing subsequent processing.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: October 15, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Chien-Cheng Lin, Chang-Chieh Huang
  • Patent number: 12111766
    Abstract: Embodiments herein relates e.g., to a method performed by a first entity, for handling memory operations of an application in a computer environment, is provided. The first entity obtains position data associated with data of the application being fragmented into a number of positions in a physical memory. The position data indicates one or more positions of the number of positions in the physical memory. The first entity then provides, to a second entity, one or more indications of the one or more positions indicated by the position data for prefetching data from the second entity, using the one or more indications.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: October 8, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Amir Roozbeh, Dejan Kostic, Gerald Q. Maguire, Jr., Alireza Farshin
  • Patent number: 12112065
    Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: October 8, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Roberto Izzi, Luca Porzio, Marco Onorato
  • Patent number: 12105634
    Abstract: A processing system includes a translation lookaside buffer (TLB). The TLB includes a plurality of TLB entries that are configured to store requested page size indications. The TLB is configured to be indexed via the requested page size indications such that a plurality of TLB requests that each indicate a same virtual address, but different respective requested page sizes are allocated respective TLB entries. As a result, in response to a TLB request that indicates a requested page size and has a virtual address that corresponds to multiple TLB entries, only a single TLB entry is identified as a TLB hit.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: October 1, 2024
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Edwin Pang, Jimshed Mirza
  • Patent number: 12099444
    Abstract: In one embodiment, a method of selectively reserving portions of a last level cache (LLC) for a multi-core processor, the method comprising: allocating, by an executive system, plural classes of service to the portions of the LLC, wherein the portions comprise ways, and wherein each of the plural classes of service are allocated to one or more of the ways; assigning, by the executive system, one of the plural classes of service to an application as a default class of service, wherein the assignment controls which of the ways the application can allocate into; and overriding, by the application, the default class of service to enable allocation by the application to the one or more of the ways associated with a non-default class of service.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: September 24, 2024
    Assignee: CENTAUR TECHNOLOGY, INC.
    Inventor: Douglas Raye Reed
  • Patent number: 12093175
    Abstract: Described are examples for storing data on a storage device, including storing, in a live write stream cache, one or more logical blocks (LBs) corresponding to a data segment, writing, for each LB in the data segment, a cache element of a cache entry that points to the LB in the live write stream cache, where the cache entry includes multiple cache elements corresponding to the multiple LBs of the data segment, writing, for the cache entry, a table entry in a mapping table that points to the cache entry, and when a storage policy is triggered for the cache entry, writing the multiple LBs, pointed to by each cache element of the cache entry, to a stream for storing as contiguous LBs on the storage device, and updating the table entry to point to a physical address of a first LB of the contiguous LBs on the storage device.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: September 17, 2024
    Assignee: Lemon Inc.
    Inventors: Peng Xu, Ping Zhou, Chaohong Hu, Fei Liu, Changyou Xu, Kan Frankie Fan