Abstract: Devices and techniques are disclosed herein to control recovery of a memory device from a reduced power state. A memory controller can include a detection circuit configured to monitor the power supply voltage to an array of memory cells during the reduced power state. Control circuitry an initialization procedure for recovery of the memory device from the reduced power state, based on the state of the detection circuit.

Abstract: A computer-implemented method according to one embodiment includes identifying a request to migrate data associated with a volume from a first storage pool to a second storage pool; identifying entries in a first table corresponding to rank extents in the first storage pool containing the data; allocating and synchronizing a plurality of second tables for the identified entries of the first table that are located in the volume; transferring the data associated with the volume from the rank extents in the first storage pool containing the data to one or more rank extents in the one or more ranks of the second storage pool; and updating the second tables to correspond to the transferred data in the one or more rank extents in the one or more ranks of the second storage pool.

Abstract: Certain embodiments described herein relate to an improved block-level replication system. One or more components in an information management system may receive a request to perform a block-level replication between a source storage device and a destination storage device, and depending on the specific replication mode requested, (i) store block-level changes directly to the destination storage device or (ii) first to a recovery point store and then later to the destination storage device.

Abstract: Circuitry comprises a translation lookaside buffer to store memory address translations, each memory address translation being between an input memory address range defining a contiguous range of one or more input memory addresses in an input memory address space and a translated output memory address range defining a contiguous range of one or more output memory addresses in an output memory address space; in which the translation lookaside buffer is configured selectively to store the memory address translations as a cluster of memory address translations, a cluster defining memory address translations in respect of a contiguous set of input memory address ranges by encoding one or more memory address offsets relative to a respective base memory address; memory management circuitry to retrieve data representing memory address translations from a memory, for storage by the translation lookaside buffer, when a required memory address translation is not stored by the translation lookaside buffer; detector circ

Abstract: A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.

Abstract: A host is configured to communicate with a storage controller over a first storage area network. A request is transmitted from the host to the storage controller to provide read diagnostic parameters of a second storage area network that is used to mirror data controlled by the storage controller to another storage controller. The host receives the read diagnostic parameters of the second storage area network from the storage controller.

Abstract: Latency in a node-based compute-near-memory system can be problematic. A solution to the problem can include or use a dedicated software-based cache at each node. The cache can be configured to store information received from each of the other nodes in the system. In an example, the cache can be populated during a breadth first search algorithm to store frontier information from each of the other nodes.

Abstract: Systems and methods of tracking page state changes are provided. An input/output is communicatively coupled to a host having a memory. The I/O device receives a command from the host to monitor page state changes in a region of the memory allocated to a process. The I/O device, bypassing a CPU of the host, modifies data stored in the region based on a request, for example, received from a client device via a computer network. The I/O device records the modification to a bitmap by setting a bit in the bitmap that corresponds to a location of the data in the memory. The I/O device transfers contents of the bitmap to the CPU, wherein the CPU completes the live migration by copying sections of the first region indicated by the bitmap to a second region of memory. In some implementations, the process can be a virtual machine, a user space application, or a container.

Abstract: Data base performance is improved using write-behind optimization of covering cache. Non-volatile memory data cache includes a full copy of stored data file(s). Data cache and storage writes, checkpoints, and recovery may be decoupled (e.g., with separate writes, checkpoints and recoveries). A covering data cache supports improved performance by supporting database operation during storage delays or outages and/or by supporting reduced I/O operations using aggregate writes of contiguous data pages (e.g., clean and dirty pages) to stored data file(s). Aggregate writes reduce data file fragmentation and reduce the cost of snapshots. Performing write-behind operations in a background process with optimistic concurrency control may support improved database performance, for example, by not interfering with write operations to data cache. Data cache may store (e.g., in metadata) data cache checkpoint information and storage checkpoint information. A stored data file may store storage checkpoint information (e.g.

Abstract: An electronic device is disclosed. An electronic device comprises: a first memory in which an operating system and an application program executed on the operating system are stored; a second memory; a processor for loading at least some codes among codes corresponding to an application program from the first memory to the second memory, and when access information of the codes loaded in the second memory is received from a kernel of an operating system, accessing an area in which the loaded codes are stored, on the basis of the received information and executing the application program; and a snoop for monitoring access to an area in which a preset code, the access of which has been limited, from among codes loaded in the second memory is stored.

Abstract: An apparatus includes processing circuitry configured that performs data processing in response to instructions of one of a plurality of software execution environments. First stage partition identifier remapping circuitry remaps a partition identifier specified for a memory transaction by a first software execution environment to a internal partition identifier to be specified with the memory transaction issued to at least one memory system component. In response to a memory transaction to be handled, the at least one memory system component controls allocation of resources for handling the memory transaction or manage contention for the resources in dependence on a selected set of memory system component parameters selected in dependence on the internal partition identifier specified by the memory transaction.

Abstract: An operating method of a system-on-chip includes outputting a prefetch command in response to an update of mapping information on a first read target address, the update occurring in a first translation lookaside buffer storing first mapping information of a second address with respect to a first address, and storing, in response to the prefetch command, in a second translation lookaside buffer, second mapping information of a third address with respect to at least some second addresses of an address block including a second read target address.

Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.

Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. The storage devices may be assigned to one of a plurality of memory tiers, and the data in a storage device may be reassigned to another storage device in a different memory tier.

Abstract: A method and system for memory attack mitigation in a memory device includes receiving, at a memory controller, an allocation of a page in memory. One or more device controllers detects an aggressor-victim set within the memory. Based upon the detection, an address of the allocated page is identified for further action.

Abstract: A data storage device and method for host-initiated cached read to recover corrupted data within timeout constraints are provided. In one embodiment, a data storage device is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to receive a read look-ahead command from a host to perform a read look-ahead of a first logical address; receive a read command from the host to read a second logical address; and execute the read look-ahead command by performing the following as background operations while executing the read command: read data for a location in the non-volatile memory that corresponds to the first logical address; correct an error in the data; and cache the corrected data in the volatile memory. The cached corrected data can be sent back to the host in response to the host requesting a read of the same logical address. Other embodiments are provided.

Abstract: A computing platform comprising a first computer system including a first host and a first accelerator communicatively coupled to the first host, including a first memory, a first page table to perform a translation of virtual addresses to physical addresses in the first memory and a first trusted agent to validate the address translations.

Abstract: A storage device which is connected to a host using a virtual memory includes a solid state drive that receives a streaming access command including a logical block address (LBA) list and a chunk size, and prefetches stream data requested according to the LBA list and the chunk size from a nonvolatile memory device without an additional command. The prefetched stream data is sequentially loaded onto a buffer, and an in-storage computing block accesses a streaming region registered on the virtual memory to sequentially read the stream data loaded onto the buffer in units of the chunk size. The buffer is mapped onto a virtual memory address of the streaming region.

Abstract: A storage service supports attachment of multiple clients to a distributed storage object and further supports persistent reservations that govern types of access the respective clients are granted with respect to the distributed storage object. In order to efficiently distribute reservation state changes to multiple partitions of the distributed storage object hosted by different data storage units/servers, existing connections are used between the data storage units/servers hosting the partitions of the distributed storage object and the connected clients to propagate reservation state changes.

Abstract: In exemplary aspects of managing the ejection of entries of a coherence directory cache, the directory cache includes directory cache entries that can store copies of respective directory entries from a coherency directory. Each of the directory cache entries is configured to include state and ownership information of respective memory blocks. Information is stored, which indicates if memory blocks are in an active state within a memory region of a memory. A request is received and includes a memory address of a first memory block. Based on the memory address in the request, a cache hit in the directory cache is detected. The request is determined to be a request to change the state of the first memory block to an invalid state. The ejection of a directory cache entry corresponding to the first memory block is managed based on ejection policy rules.