Abstract: A technique is provided for controlling eviction from a storage structure. An apparatus has a storage structure with a plurality of entries to store data. The apparatus also has eviction control circuitry configured to maintain eviction control information in accordance with an eviction policy, the eviction policy specifying how the eviction control information is to be updated in response to accesses to the entries of the storage structure. The eviction control circuitry is responsive to a victim selection event to employ the eviction policy to select, with reference to the eviction control information, one of the entries to be a victim entry whose data is to be discarded from the storage structure. The eviction control circuitry is further configured to maintain, for each of one or more groups of entries in the storage structure, an indication of a most-recent entry. The most-recent entry is an entry in that group that was most recently subjected to at least a given type of access.

Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.

Abstract: An apparatus includes a plurality of processor cores; a shared cache connected to the plurality of processor cores; a cache control unit connected to the shared cache; and a way allocation circuitry connected to at least one of the plurality of processor cores. The way allocation circuitry is external to the plurality of processor cores. The cache control unit and the way allocation circuitry are cooperatively configured to process an intercepted memory request with respect to designated ways in the shared cache, the designated ways being based on a partition identifier and a partition table.

Abstract: Adding, by a memory management process executing in a computing device, a physical address of each of a plurality of available blocks of memory to a binary search tree based on the physical address. After the adding, receiving, by the memory management process, a request for a memory allocation, the memory allocation to be from the plurality of available blocks. Allocating, by the memory management process and in response to the request, blocks of memory in physical address order from the binary search tree.

Abstract: A fabric interface apparatus, including: a fabric interface logic to communicatively couple to a fabric; a data interface to communicatively couple to a compute platform including memory resources in at least two memory tiers; and a tier-aware read/write engine (TARWE) to: receive an incoming packet via the fabric; parse a header of the incoming packet to identify a hint for directing the incoming packet to a preferred memory tier; and write the incoming packet to the preferred memory tier.

Abstract: Preventing duplicate entries of identical data in a storage device, including: receiving a write request to write data to the storage device; calculating one or more signatures for the data associated with the write request; determining whether any of the calculated signatures match a calculated signature contained in a recently read signature buffer, each entry in the recently read signature buffer associating a calculated signature for data that has been read with an address of a storage location within the storage device where the data is stored; and responsive to determining that one of the calculated signatures matches a calculated signature contained in the recently read signature buffer, determining whether the data associated with the calculated signature is a duplicate of data stored at a particular address that is associated with the calculated signature contained in the recently read signature buffer.

Abstract: Provided are a method and apparatus for managing a page cache for multiple foreground applications. A method of managing a page cache includes identifying an application accessing to data stored in storage; allocating a page used by the application for the accessed data to a page cache; setting a page variable corresponding to a type of the identified application to the allocated page; and managing demoting of the allocated page based on the set page when the allocated page is a demoting target.

Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.

Abstract: A data storage system includes a memory device including a plurality of memory cells which are coupled to a plurality of row lines, and configured to communicate with a host device through at least one port; and a memory controller configured to select one of a first precharge policy and a second precharge policy according to a precharge control signal, and control the row lines based on access addresses for the row lines according to the selected precharge policy, wherein, under the first precharge policy, one of a first precharge scheme and a second precharge scheme is applied, and under the second precharge policy, both the first and second precharge schemes are applied at different times.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is arranged to configure a plurality of first memory blocks to receive data from a host device. The first memory blocks form at least a first superblock. When an amount of data stored in the first memory blocks reaches a specific value, the memory controller moves the data from the first memory blocks to a plurality of second memory blocks in a predetermined procedure. The second memory blocks form at least a second superblock. The second superblock includes the second memory blocks located in different memory chips. The data stored in two adjacent logical pages in the first superblock is written in two second memory blocks located in different memory chips.

Abstract: Techniques for consolidating shared state for translation lookaside buffer (TLB) shootdowns are provided. In one set of embodiments, an operating system (OS) kernel of a computer system can co-locate, in a system memory of the computer system, a plurality of shared data accessed by first and second processing cores of the computer system for performing a translation lookaside buffer (TLB) shootdown of the first processing core by the second processing core, where the co-locating allows the plurality of shared data to occupy a single cache line when brought from the system memory into a CPU (central processing unit) cache of the first or second processing core. This can include, e.g.

Abstract: A computer-implemented method, according to one embodiment, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a calibration read mode of the block, and using the calibration read mode to determine whether pages in the block should be read using full page read operations. In response to determining that the pages in the block should not be read using full page read operations, a current value of a partial page read indicator for the block is determined. The block is further calibrated by reading only a portion of each page in the block, where the current value of the partial page read indicator determines which portion of each respective page in the block is read. Moreover, the current value of the partial page read indicator is incremented.

Abstract: A method for providing elastic columnar cache includes receiving cache configuration information indicating a maximum size and an incremental size for a cache associated with a user. The cache is configured to store a portion of a table in a row-major format. The method includes caching, in a column-major format, a subset of the plurality of columns of the table in the cache and receiving a plurality of data requests requesting access to the table and associated with a corresponding access pattern requiring access to one or more of the columns. While executing one or more workloads, the method includes, for each column of the table, determining an access frequency indicating a number of times the corresponding column is accessed over a predetermined time period and dynamically adjusting the subset of columns based on the access patterns, the maximum size, and the incremental size.

Abstract: A memory system may include: a memory device including a plurality of memory dies suitable for storing data; and a controller operatively coupled to the memory dies of the memory device via a plurality of channels, the controller may be suitable for checking the plurality of the channels, selecting independently best transmission channels and best reception channels among the plurality of the channels according to states of the channels, requesting performing of command operations corresponding to the commands through the best transmission channels to the memory dies, and receiving performance results of the command operations through the best reception channels from the memory dies.

Abstract: A method is used in managing data reduction in storage systems using machine learning. A value representing a data reduction assessment for a first data block in a storage system is calculated using a hash of the data block. The value is used to train a machine learning system to assess data reduction associated with a second data block in the storage system without performing the data reduction on the second data block, where assessing data reduction associated with the second data block indicates a probability as to whether the second data block can be reduced.

Abstract: In a distributed storage system, a first storage node receives a first data read request for reading first data. The first data request includes a first address of the first data. The first storage node determines that the first data are stored in a first storage device included in the first storage node based on the first address. Based on the determination, the first storage node checks whether the first storage device is in a trusted access state. Further, the first storage node obtains the first data when the first storage device is in the trusted access state.

Abstract: A storage system and method for user-defined data archiving are provided. In one embodiment, the method comprises: receiving a write command from a host; determining whether the storage system received an indicator from the host indicating that data of the write command is archive data; in response to determining that the storage system received the indicator, storing the data in the multi-level memory cells; and in response to determining that the storage system did not receive the indicator, storing the data in the single-level memory cells. Other embodiments are provided.

Abstract: A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.

Abstract: A request associated with restoring a previous version of a linked clone virtual machine is received. One or more changes between a base image of a parent virtual machine and the previous version of the linked clone virtual machine are determined. One or more data blocks corresponding to the base image and one or more data blocks corresponding to the determined changes are provided to a remote system.

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a battery state associated with the memory system or sub-system may be used as an indicator or basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a battery state or condition satisfies a criterion. Based on determining that the criterion is satisfied the, the garbage collection operation may be postponed until the battery state changes to satisfy a different battery condition.