Abstract: To provide stable oscillation frequencies at small step intervals even with a high reference frequency, a PLL circuit of the present invention includes variable frequency oscillation means for outputting an oscillation frequency signal, pulse train generating means receiving the oscillation frequency signal as a clock signal, for converting a train of n clocks to m pulses where n and m are positive integers, generating sequential pulses produced by arranging part of the m pulses so that they have non-uniform numbers of clocks, and outputting m periodical, sequential pulse trains so that the pulses having the non-uniform numbers of clocks are arranged differently, phase comparing means for outputting a phase error signal by determining a phase error between the reference frequency signal and the oscillation frequency signal based on the reference frequency signal and the m sequential pulse trains, and filtering means for filtering the phase error signal to produce a frequency control signal, and supplying the

Abstract: In methods and apparatus for estimating carrier-to-interference ratios of signals transmitted between cellular radio base stations and mobile units, a SAT signal is transmitted from a base station to a mobile unit served by that base station. The mobile unit receives the SAT signal and retransmits the received SAT signal to the base station. A first order autoregressive parameter is calculated for the received SAT signal at the base station is correlated with a tabulated carrier-to-interference ratio estimate to estimate the carrier-to-interference ratio of the signals.

Abstract: An adaptive equalizing system equalizes an unequalized signal and performs carrier recovery for use in a digital communication receiver. An equalizing coefficient is initialized by a constant modulus algorithm (CMA) and the initialized equalizing coefficient is more finely updated by a stop-and-go algorithm (SGA). When the convergency by the CMA reaches a predetermined threshold value, carrier recovery is performed, while when an average value of the phase error during performing the carrier recovery is less than another predetermined threshold value, the equalizing algorithm is converted into the SGA. Thus, the adaptive equalizing apparatus can equalize the received signal more simply and reliably.

Abstract: A digital oscillator is synchronized to a master clock by comparing the master clock to an output of the digital oscillator by providing both to a first register which enables a counter. The counter increments while enabled until cleared. The output of the counter is then compared with a stored signal. Depending upon the match with the stored signal, the output of the digital oscillator is either slowed, advanced or maintained. The output from the digital oscillator is then fed back to an input of the digital phase locked loop.

Abstract: A method and apparatus are provided for smoothing jitter in a smoothed clock output by routing a portion of the incoming clock signal representing phase hit information through a digital high-pass filter (12), which produces complementary output digital signals. One of the output signals includes the higher order bits of the filtered phase hit signal, and the other output signal includes the lower order bits of the filtered phase hit signal. The filtered, complementary phase hit signals are summed with the stream of clock pulses to be smoothed. Each of these summed signals is supplied to a separate phase detector circuit (120, 121). The phase detector (120) receiving the higher order bit signal generates a coarse error signal, and the phase detector (121) receiving the lower order bit signal generates a fine error signal.

Abstract: A digital communications receiver provides joint MLSE equalization and diversity combining. A plurality of diversity branches are processed to produce complex receive data samples and synchronization information. Channel estimators then form channel estimates from the data samples and synchronization information. The data samples and channel estimates are then used by pre-processors to produce metric multipliers. Finally, the metric multipliers are combined with hypothesized data sequences to generate and accumulate metrics using a sequence estimation algorithm to produce a demodulated data stream.

Abstract: A phase locked loop system or other second order feedback system whose natural frequency scales with its output and whose damping factor remains constant includes a filter circuit having a scaling channel for scaling the error, an integrating channel for integrating the error, and a summing circuit for combining the scaled error and integrated error; an integrator circuit responsive to the summing circuit to produce an output signal, the gain of the integrator circuit being proportional to its output signal; and a control circuit for controlling the gain of the integrating channel proportional to the output signal and maintaining constant the ratio of and scaling the product of the unity gained frequency and the zero frequency of the feedback system to keep constant the damping factor and to scale the natural frequency of the feedback system with the output signal, respectively.

Abstract: A selective call receiver (10) comprising a receiver circuit (100) having at least one radio frequency amplifier (112) and at least one mixer (114), a baud rate detector (102), a signal grader (104), and a gain controller (106). Coupling to the baud rate detector (102) to determine the signal quality of a selective call signal, the signal grader (104) collates the results of at least one baud rate detection with a plurality of predetermined criteria and assigns a signal grade to the selective call signal. The signal grader (104) then indicates the signal grade to the gain controller (106) which then sets the at least one radio frequency amplifier (112) and the at least one mixer (114) to operate with one of a plurality of selectable predetermined parameters including a gain setting and a mixer injection setting corresponding to the signal grade assigned to the selective call signal.

Abstract: In a digital transmission system comprising a transmitter (2) connected to a receiver (6) through a channel (4), this receiver comprises an equalizer (8) which includes an equalization filter (12) with output signals from which a sum weighted with weight factors is determined. The output signal of the equalizer is applied to a detector. According to the inventive idea a correction signal for correcting the coefficients w of the equalizer is derived from w.sub.k =w.sub.k-1 +Ma.sub.k e.sub.k, where a.sub.k is the vector of a plurality of successive detected symbols, and e.sub.k is a difference between the current input signal of the detector and a reconstructed ideal input signal of the detector.

Abstract: An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.

Abstract: The present invention relates to a carrier recovery (CR) circuit for recovering carriers from offset quadrature phase shift keying (O-QPSK) modulated carriers, in which each of two orthogonal sequences of burst signals, to be modulated by the O-QPSK system, has a preamble field set in a prescribed bit pattern. In a Costas loop for recovering carriers by the QPSK system, a 1/2 symbol delay circuit makes the phases of burst signals inputted to two orthogonal channels identical to each other. A phase comparator for the bit timing recovery field adds with an adder 193 a detected carrier value detected by an arc tangent calculating circuit and a value resulting from the delaying of the detected carrier value with a one-symbol delay circuit, and supplies the added detected carrier value. A switching circuit switches and supplies the outputs of phase comparators, and enters the output into a loop filter.

Abstract: A PLL device includes a VCO (10) forming a phase-locked loop and an amplifier (18) for outputting a phase change signal having phase function with respect to frequencies, a synthesizer (20) having a first input receiving an error signal (phase comparison signal) from a phase comparator (2) through an LPF (4) and a second input for synthesizing signals at the first and second inputs to output a synthetic signal, and a phase and amplitude changer (15) for changing the phase and amplitude of the synthetic signal to provide a phase and amplitude change signal to the second input of the synthesizer in response to the error signal, the synthetic signal acting as an oscillation signal of the VCO (10), whereby the PLL device has a small variation in free-running frequency and a wide lock range.

Abstract: A lock detection circuit (112) includes a first sampler (113) which samples an input signal (102) at a rate of an output signal (109) to provide a sampled input signal. A second sampler (114) which samples a feedback signal (111) at the rate of the output signal (109) to provide a sampled feedback signal. The sampled input signal is subsequently sampled by a third sampler (115) at the rate of the feedback signal. The sampled feedback signal is subsequently sampled by a fourth sampler (116) at the rate of the input signal. The second sampled input signal and the second sampled feedback signal are subsequently compared (117) and when they substantially match, an indication (122) is set to indicate that phase and/or frequency lock has been obtained.

Abstract: A method is used in a receiver (100) for aligning the receiver (100). The method has a step of intercepting and demodulating the FM signal, which includes data symbols. The method has a step of determining error rates, in which the error rates of at least two subsets of the data symbols are determined. Each subset includes a plurality of the data symbols modulated at a unique one of a plurality of frequency deviations. The at least two subsets include data symbols of two opposite polarities. The method has a step of generating a frequency control signal, in which the frequency control signal is determined based on the error rates. The method has a step of aligning a receiver section (105), in which the receiver section (105) is aligned to the FM signal by controlling a local oscillator (320)which is responsive to the frequency control signal.

Abstract: Accurate phase switching of similar pulse trains having different phase position, in which a respectively selected pulse train determines a pulse train to be distributed by means of a phase locked loop, is achieved. Each pulse train is individually delayed so the phase position is roughly adjusted to zero with respect to the pulse train to be distributed. Each non-selected pulse train is continuously compared with the pulse train to be distributed. A phase error voltage is determined that corresponds to a phase difference still present as it would become effective as a control voltage in the phase locked loop. An oppositely equal correcting voltage is added to the phase error voltage to produce a sum, and the sum is made available as an output voltage. Switching to another pulse train is effected by maintaining the relevant correcting voltage at a momentary value and switching the associated output voltage into the phase locked loop as a control voltage in place of a previously used output voltage.

Abstract: A frequency control device comprises, in the form of a phase-locked loop, a phase comparator, a filter, an oscillator producing a local clock signal and two divide-by-M frequency dividers. The dividers receive the local clock signal whose frequency is slaved to N times the frequency of a master clock signal, with M<N, and are looped to the inputs of the comparator. A first of the dividers is reinitialized at the frequency of the master clock signal. A load circuit loads the most-significant-bit stages of a counter included in the first divider with a binary word added to binary elements stored in most-significant-bit stages of a counter included in the second divider, after a resetting of the second divider following a general initialization of the device.

Abstract: The present invention comprises an adaptive bilinear decision feedback equalizer to be implemented in a receiver to cancel the intersymbol interference. Basically, the decision feedback equalizer has a feed-forward filter, a feedback filter and a bilinear filter. The equalizer coefficients are determined recursively using an RLS or LMS algorithm.

Abstract: A digital phase locked loop arrangement is used in a desynchronizer demapping a plesiochronous stream from a synchronous bitstream is disclosed to remove jitter due to overhead gapping from the plesiochronous stream. To this end the part of the synchronous bitstream constituting the plesiochronous stream is written into a buffer memory (BUFF), the write address (WRADDR) of which is incremented at the rate of this plesiochronous part. The read address (RDADDR) for the buffer memory (BUFF) is derived from the write address (WRADDR) in the digital phase locked loop arrangement. Herein, a negative feedback for byte justifications in the synchronous bitstream and a positive feedback for bit justifications therein is provided so that byte justifications give rise to a lower change in the incrementing rate of the read address (RDADDR) but of longer duration, whereas bit justifications give rise to an increased change in this incrementing rate but of shorter duration.

Abstract: In a bit clock generation circuitry, a T/2 pulse generator includes a monostable multivibrator triggered by an edge of an input PCM data signal and controlled by a time constant adjusting signal so as to generate a pulse signal having its pulse width adjusted in accordance with the time constant adjusting signal. In response to a pulse signal generated by the monostable multivibrator, a D-type flipflop latches the input PCM data signal for generating a delayed data signal delayed from the input PCM data signal by T/2. An exclusive-OR means receives the input PCM data signal and the delayed data signal for generating a T/2 pulse signal.

Abstract: A digital phase lock loop for producing an output signal based on an input signal which is subject to jitter and frequency offset. The output signal follows the center of the jitter on the input signal to produce a jitter-filtered signal which compensates for the frequency offset. The digital phase lock loop includes a phase detector, a pulse scaler counter, a phase error counter and a first digitally controlled oscillator. The phase detector detects a phase difference between the input signal and the output signal and outputs up or down pulses depending on the phase difference. The pulse scaler counter increments an up/down counter when an up pulse is received from the phase detector, and decrements the up/down counter when a down pulses is received from the phase detector. When the up/down counter overflow or underflows, a correction pulse is output. The phase error counter resets during every cycle of the input and output signals.