Abstract: An intermediate frequency (IF) converter converts a received signal to an IF signal. A demodulator demodulates the IF signal to a demodulated signal and detects a phase error. A frequency error detector detects a frequency error based on the phase error. A modulated-carrier detector detects a modulated carrier component from the IF signal. When the modulated carrier component is detected, a controller achieves a frequency stabilizing operation based on the frequency error.

Abstract: There is disclosed a PLL circuit wherein a delay circuit (3') of a phase comparator (30') receives a supply current (IC) from a first variable current source (.PHI.IC) and changes a delay time (.DELTA.T) in negative correlation with the amount of the supply current (IC), and the first variable current source (.PHI.IC) changes the amount of the supply current (IC) to the delay circuit (3') in accordance with the indication of a control signal (C1) serving as a supply current control signal for a second variable current source (.PHI.IA) and a third variable current source (.PHI.IB) of a charge pump circuit (31). Changes in delay time of the delay device of the phase comparing device are adapted such that the delay time is constantly suitable as the amount of current of the phase comparison voltage signal of the charge pump circuit changes, permitting reduction in lock-up time.

Abstract: A synchronizing signal generating apparatus generates a synchronizing signal from digital data in which a synchronizing signal formed of a fixed data pattern having a predetermined bit number is inserted at a predetermined time interval L.

Abstract: A radio telephone of a configuration permitting the selective use of a waveform equalizer is so configured that the output signals of a waveform equalizer or the output signals of a receiving circuit are selectively stored in one memory or sequentially stored in plural memories, respectively, a plurality of memories, and stored signals can be selectively taken out of the one memory when the waveform equalizer is used, and stored signals can be sequentially taken out Of plural memories at respectively proper timings, to thereby to prevent omission and collision of signal at the time of switching between use and non-use of the waveform equalizer.

Abstract: A .pi./4-DQPSK differential phase state encoder/decoder (Codec) is presented which can be implemented using a small number of logic gates. The phase state Codec acts upon data in the transmitter and in the receiver of a .pi./4-DQPSK modulating system whereby the use of a look-up table technique or other off-line procedure to ensure proper phase transitions is not required. The phase state Codec is configured to ensure compliance with the IS-54 standard as well as other similar standards.

Abstract: An FSK receiver includes an amplifier, a local oscillation circuit, a mixer circuit, a limiter circuit, a demodulation circuit, a current detecting circuit, and a control circuit. The amplifier amplifies a received wave frequency-modulated with a binary digital signal. The local oscillation circuit outputs a local oscillation frequency signal. The mixer circuit mixes an amplified output from the amplifier with the local oscillation frequency signal. The limiter circuit receives a baseband signal component output from the mixer circuit to limit an amplitude. The demodulator samples the binary signal from the limiter circuit with a sampling signal generated by the received wave. The current detecting circuit detects a current flowing in the mixer circuit. The control circuit controls the gain of the amplifier in accordance with an output from the current detecting circuit.

Abstract: A composite signal recognizer separator, and PSK, AM, FM demodulator apparatus for processing received communication signals. The receiver utilizes N demodulators cascadely-coupled, where N is equal to or greater than the number of co-channel signals or perceived interference. Detailed in both dual and single stages cascaded fashion, the receiver first tracks to a predominant (stronger) signal, and regeneratively improves track on other (weaker) signals by subtracting predominant noise portion from the input of further demodulation stages. A unified approach to PSK carrier phase tracking, character data tracking, and recovery clock tracking is utilized.

Abstract: Adaptive equalizers and processing methods wherein data required to implement an adaptation algorithm is sampled at a rate that is significantly lower than the symbol rate. The adaptation algorithm is processed at this reduced rate, in that updated tap coefficients, sample timing errors and symbol clock error signals are computed at this reduced rate. An advantage of the adaptive equalizer and processing method of the present invention is that the adaptation algorithm may be implemented in equipment that operates at a clock rate that is much less then the symbol rate. In particular, the adaptation algorithm may be computed using software that is resident in inexpensive general purpose digital processor, such as a personal computer, for example.