Abstract: Massively parallel, block-based encoding and decoding technology that includes an encoded block format uses a plurality of processing cores to perform block-based encoding and decoding operations. The encoded block format includes a header and a payload. The encoded block format's headers represent unique single-Byte and multi-Byte event parameters that occur in the original data block from which each encoded block was generated. The encoded block format's payloads represent a sequence of single-Byte and multi-Byte events using tokens that associate each event with its corresponding parameter(s). Metadata can include an array of encoded block sizes that support random access.

Abstract: A computer-implemented optimization problem arithmetic method includes, receiving a combinatorial optimization problem, selecting a first arithmetic circuit from among a plurality of arithmetic circuits based on a scale or a requested accuracy of the combinatorial optimization problem and a partition mode that defines logically divided states of each of the plurality of arithmetic circuits, and causing the first arithmetic circuit to execute an arithmetic operation of the combinatorial optimization problem.

Abstract: The invention is notably directed at a device for high-dimensional computing comprising an associative memory module. The associative memory module comprises one or more planar crossbar arrays. The one or more planar crossbar arrays comprise a plurality of resistive memory elements. The device is configured to program profile vector elements of profile hypervectors as conductance states of the resistive memory elements and to apply query vector elements of query hypervectors as read voltages to the one or more crossbar arrays. The device is further configured to perform a distance computation between the profile hypervectors and the query hypervectors by measuring output current signals of the one or more crossbar arrays. The invention further concerns a related method and a related computer program product.

Abstract: According to one embodiment, a calculating device includes a processor. The processor acquires a data set {s} and repeats a processing procedure. The processing procedure includes first and second variable updates. The first variable update includes updating an ith entry of a first variable xi by adding a first function to the ith entry of the first variable xi. The ith entry of the first variable xi is one of a first variable set {x}. A variable of the first function includes at least a part of a second variable set {y}. The second variable update includes updating an ith entry of a second variable yi by adding a second function and a third function to the ith entry of the second variable yi. The ith entry of the second variable yi is one of the second variable set {y}. The processor outputs at least a fourth function.

Abstract: A device for providing a random number generator is provided. The device may include a true random number generator, at least one deterministic random number generator, and an exclusive OR logic function. The TRNG has an output and the at least one DRNG has an output. The exclusive OR logic function has a first input coupled to the output of the TRNG and a second input coupled to the output of the at least one DRNG, and an output for providing a random number. The TRNG and the at least one DRNG may include separate and independent entropy sources. A method for generating a random number is also provided.

Abstract: The present invention provides a calculator comprising number keys for digits one through nine, a NULL key, a first additional number key configured to represent 3.663, and a second additional fixed value number key configured to represent 6.336. The number keys are operatively coupled to processor configure to execute mathematical functions. The calculator can be a stand-alone device, or be executed within a cell phone, tablet, or other general purpose computer.

Abstract: Disclosed embodiments relate to performing floating-point (FP) arithmetic. In one example, a processor is to decode an instruction specifying locations of first, second, and third floating-point (FP) operands and an opcode calling for accumulating a FP product of the first and second FP operands with the third FP operand, and execution circuitry to, in a first cycle, generate the FP product having a Fuzzy-Jbit format comprising a sign bit, a 9-bit exponent, and a 25-bit mantissa having two possible positions for a JBit and, in a second cycle, to accumulate the FP product with the third FP operand, while concurrently, based on Jbit positions of the FP product and the third FP operand, determining an exponent adjustment and a mantissa shift control of a result of the accumulation, wherein performing the exponent adjustment concurrently enhances an ability to perform the accumulation in one cycle.

Abstract: Disclosed approaches for circuitry that implements a softmax function include difference calculation circuitry configured to calculate differences between combinations of elements, zk?zj, of a vector. First lookup circuitry is configured to lookup and output representations of exponential values, ezk?zj associated with the differences in response to input of the differences. Each adder circuit of N adder circuits sums a subset of the exponential values output from the first lookup circuitry and a value of 1. The sum output by each adder circuit denotes a denominator of a plurality of denominators of the softmax function. Second lookup circuitry is configured with quotients and looks-up and outputs quotients associated with the plurality of denominators as results of the softmax function.