Patents Examined by Hyun Nam
  • Patent number: 10379749
    Abstract: An operating method of a semiconductor device includes monitoring multiple request packets and multiple response packets that are being transmitted between a master device and a slave device. A target request packet that matches predefined identification (ID) information is detected from among the request packets. An operation of a latency counter is initiated. The operation is for measuring the latency of a communication exchange (transaction) that includes the target request packet and a target response packet that is one of the response packets that matches the predefined ID information. The target response packet is detected from among the response packets. The operation of the latency counter is terminated. A latency value of the communication exchange is acquired from the latency counter.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: August 13, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nak Hee Seong, Sang Youn Lee, Seong Min Jo, Yun Kyo Cho, Dong Soo Kang, Byeong Jin Kim, Jae Geun Yun
  • Patent number: 10380039
    Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Niranjan L. Cooray, Satyeshwar Singh, Sameer KP, Ankur N. Shah, Kun Tian, Abhishek R. Appu, Altug Koker, Joydeep Ray, Balaji Vembu, Pattabhiraman K, David Puffer, David J. Cowperthwaite, Rajesh M. Sankaran
  • Patent number: 10366038
    Abstract: This application relates to methods and apparatus for configuring a serial data interface, especially a data interface (300) for a transducer (324) such as a digital microphone or loudspeaker. The data interface is selectively operable in a first or second serial data mode of operation for input of data to or output data from the transducer device. The first and second serial data modes are different, e.g. correspond to different serial formats. The data interface has a controller (330) configured to determine a resistance value (331, 332) at a sense terminal (314) of the transducer device and to control the data interface in the first serial data mode if the resistance value is within a first resistance range and control the data interface in the second serial data mode if the resistance value is within a second, different, resistance range.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: July 30, 2019
    Assignee: Cirrus Logic, Inc.
    Inventor: Ian Johnson Smith
  • Patent number: 10360125
    Abstract: Methods and apparatus to communicatively coupled field devices to a remote terminal unit are disclosed. The example apparatus includes a base rack for a remote terminal unit in a process control system. The example apparatus further includes a first termination module to be inserted in a first termination slot of the base rack. Wires communicatively coupled to a field device are to be terminated on the first termination module. The example apparatus also includes a first control module separate from the first termination module to be inserted in a first control slot of the base rack. The first control module is to be communicatively coupled with the first termination module via a backplane of the base rack. The first control module is to control communications with the field device.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 23, 2019
    Assignee: Bristol, Inc.
    Inventors: Richard Joseph Vanderah, Robert John Findley
  • Patent number: 10353709
    Abstract: Techniques and mechanisms described herein include a signal processor implemented as an overlay on a field-programmable gate array (FPGA) device that utilizes special purpose, hardened intellectual property (IP) modules such as memory blocks and digital signal processing (DSP) cores. A Processing Element (PE) is built from one or more DSP cores connected to additional logic. Interconnected as an array, the PEs may operate in a computational model such as Single Instruction-Multiple Thread (SIMT). A software hierarchy is described that transforms the SIMT array into an effective signal processor.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 16, 2019
    Assignee: Nextera Video, Inc.
    Inventors: John E. Deame, Steven Kaufmann, Liviu Voicu
  • Patent number: 10346326
    Abstract: Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Yadong Li, Linden Cornett, Manasi Deval, Anil Vasudevan, Parthasarathy Sarangam
  • Patent number: 10346327
    Abstract: A system and computer program product are provided for optimized timer placement. A request to apply a new timer in a computer system is received and an interrupt time for the new timer is extracted from the new timer. A timer list is accessed for each processor in the system responsive to the received request. A range for placement of the new timer is established with respect to each of the accessed timer lists. A timer expiry delay is calculated between proximal processor interrupts and the extracted interrupt time based on the established range placement. Proximity of the extracted interrupt time within the existing processor interrupts is determined and one of the processors is selected based on the calculation and the determined proximity. The new timer is placed on the selected processor.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Juan M. Casas, Jr., Nikhil Hegde, Keerthi B. Kumar, Shailaja Mallya
  • Patent number: 10346331
    Abstract: One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern detected signals. Sequence detection logic receives the plurality of pattern detected signals and generates a plurality of sequence detected signals. Another embodiment relates to a method of data detection and event capture. Another embodiment relates to an integrated circuit having a first data detection and event capture circuit in a receiver circuit and a second data detection and event capture circuit in a transmitter circuit. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: July 9, 2019
    Assignee: Altera Corporation
    Inventors: Si Xing Saw, Seng Kuan Yeow, Kang Syn Ting
  • Patent number: 10346329
    Abstract: A method is provided for optimized timer placement. A request to apply a new timer in a computer system is received and an interrupt time for the new timer is extracted from the new timer. A timer list is accessed for each processor in the system responsive to the received request. A range for placement of the new timer is established with respect to each of the accessed timer lists. A timer expiry delay is calculated between proximal processor interrupts and the extracted interrupt time based on the established range placement. Proximity of the extracted interrupt time within the existing processor interrupts is determined and one of the processors is selected based on the calculation and the determined proximity. The new timer is placed on the selected processor.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Juan M. Casas, Jr., Nikhil Hegde, Keerthi B. Kumar, Shailaja Mallya
  • Patent number: 10349112
    Abstract: Methods and systems for multi-path video and network channels may comprise a communication device comprising a wideband tuner (WB) and a narrowband tuner (NB). A video channel and a network channel may be received in the WB when the device is operating in a first stage. A video channel and a network channel may be received in the WB and the network channel may also be received in the NB when the device is operating in a second stage. The network channel may be received in the NB when the device is operating in a third stage. The reception of the network channel from both the WB and NB may enable a continuous reception of the network channel in a transition between the first and third stages. The WB may be operable to receive a plurality of channels and the NB may be operable to receive a single channel.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: July 9, 2019
    Assignee: Maxlinear, Inc.
    Inventors: Anand Anandakumar, Sheng Ye, Curtis Ling
  • Patent number: 10331581
    Abstract: A high-performance computing system, method, and storage medium manage accesses to multiple memory modules of a computing node, the modules having different access latencies. The node allocates its resources into pools according to pre-determined memory access criteria. When another computing node requests a memory access, the node determines whether the request satisfies any of the criteria. If so, the associated pool of resources is selected for servicing the request; if not, a default pool is selected. The node then services the request if the pool of resources is sufficient. Otherwise, various error handling processes are performed. Each memory access criterion may relate to a memory address range assigned to a memory module, a type of request, a relationship between the nodes, a configuration of the requesting node, or a combination of these.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: June 25, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Frank R. Dropps, Michael E. Malewicki
  • Patent number: 10331598
    Abstract: A host computer connects to a data network via a host interface to a network interface controller A sideband interface connects the network interface controller to a baseboard management controller having a management network port for connection to a management network. A path is established in the network interface controller between the host interface the basement management controller via the sideband interface of the network interface controller to conduct data selectively between the management network and either the host central processing unit and the or internally in the network interface controller.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 25, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventor: Yuval Itkin
  • Patent number: 10324888
    Abstract: An apparatus, system, method, and program product for verifying a communication bus connection to a peripheral device are disclosed. The apparatus includes a data module that receives, over a communication bus, an identifier for a location where a peripheral device is installed. The peripheral device is communicatively coupled to an information handling device using the communication bus. The apparatus includes a verification module that compares the identifier received over the communication bus to a predefined identifier associated with the communication bus. The apparatus includes a notification module that sends a notification in response to the identifier received over the communication bus not matching the predefined identifier associated with the communication bus.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: June 18, 2019
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD
    Inventors: Luke Remis, Mark E. Andresen, Wilson Velez
  • Patent number: 10311002
    Abstract: A programmable apparatus for executing a function is disclosed. The programmable apparatus includes a physical interface configured to be connected with an external apparatus. The programmable apparatus also includes a function logic circuit configured to execute the function on the programmable apparatus. The programmable apparatus further includes a plurality of peripheral logic circuits, each of which is configured to connect the function logic circuit with the physical interface using a respective protocol. The programmable apparatus also includes a selector circuit configured to select one from among the plurality of the peripheral logic circuits to activate.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yutaka Kawai, Yohichi Miwa
  • Patent number: 10303635
    Abstract: A network adapter includes one or more network ports, multiple bus interfaces, and a processor. The one or more network ports are configured to communicate with a communication network. The multiple bus interfaces are configured to communicate with multiple respective Central Processing Units (CPUs) that support a management protocol and belong to a multi-CPU device, and with a Baseboard Management Controller (BMC). The processor is configured to, in response to a request to enumerate the bus interfaces that support the management protocol, report support of the management protocol over only a single bus interface, selected from among the multiple bus interfaces connecting the network adapter to the multi-CPU device, and exchange management packets over the communication network between the BMC and a remote management computer, wherein the management packets manage the entire multi-CPU device but traverse only the single selected bus interface.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: May 28, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventor: Yuval Itkin
  • Patent number: 10296481
    Abstract: A board adapter system includes a first adapter board. A secondary first processor coupling is located on the first adapter board, and the first adapter board passes signals between a primary first processor coupling on a first board and a first processor coupled to the secondary first processor coupling when the first adapter board engages the primary first processor coupling. A first/third processor communication bus extends between the secondary first processor coupling and the second board connector on the first adapter board, and passes signals between the first processor and a third processor that is coupled to the second board connector. A first/fourth processor communication bus extends between the secondary first processor coupling and the second board connector, and passes signals between the first processor and a fourth processor that is coupled to the second board connector on the first adapter board.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: May 21, 2019
    Assignee: Dell Products L.P.
    Inventors: Kevin Warren Mundt, Sandor Farkas, Bhyrav Mutnury
  • Patent number: 10289576
    Abstract: A storage system includes storage apparatuses and a second transmission path. The storage apparatuses each include a control device, and memory devices coupled in series with the control device through a first transmission path having the control device at a beginning. The memory devices are accessed by the control device. The second transmission path couples the storage apparatuses in a loop to allow communications between the control devices. The second transmission path includes the first transmission paths included in the respective storage apparatuses. The second transmission path is formed such that an ending of the first transmission path included in a first storage apparatus of the storage apparatuses is connected to the beginning of the first transmission path included in a second storage apparatus subsequent to the first storage apparatus on the second transmission path.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 14, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Satoshi Kubota
  • Patent number: 10282317
    Abstract: According to one embodiment, a semiconductor integrated circuit includes a bus master, a bus slave and a clock gating circuit. The bus master outputs an access request. The bus slave transmits a response to the access request to the bus master. The clock gating circuit shuts off clocks supplied to the bus slave. The bus slave includes a control circuit which outputs first and second signals in response to the access request; a first circuit which outputs a third signal in response to a clock supplied from the clock gating circuit, when the first signal is asserted; and a second circuit which receives the third signal output from the first circuit and the second signal, and outputs a fourth signal as the response to the bus master, when the second signal is asserted.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: May 7, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yuji Hisamatsu
  • Patent number: 10282332
    Abstract: A subscriber station for a bus system and a method for time-optimized data transmission in a bus system are provided. The subscriber station comprises a coding device for coding and/or decoding bits of a message to/from at least one further subscriber station of the bus system, in which at least temporarily an exclusive, collision-free access of a subscriber station to a bus line of the bus system is ensured, wherein the coding device is designed to allocate, during the coding of the message, to at least two bits as bit combination, a predetermined voltage level for a bit time and/or wherein the coding device is designed to allocate, during the decoding of the message, at least two bits as bit combination to a predetermined voltage level for a bit time.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: May 7, 2019
    Assignee: Robert Bosch GmbH
    Inventor: Stefan Thiele
  • Patent number: 10275008
    Abstract: Methods, apparatus, systems and articles of manufacture to reduce computing device power consumption are disclosed. Examples determine an idle period based on hardware residency of the computing device, and set a timer to wake up a central processing unit (CPU) from a low power idle state after the idle period, the CPU to exit the low power idle state in response to expiration of the idle period.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Derrick A. Jones, Jithendra S. Kancherlapalli, Michael C. Walz