Patents Examined by Hyun Nam
  • Patent number: 10996952
    Abstract: Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 4, 2021
    Assignee: SiFive, Inc.
    Inventors: Krste Asanovic, Andrew Waterman
  • Patent number: 10990557
    Abstract: A transmission interface communicating method used in a display device that includes the steps outlined below is provided. A first status update signal is received from a host device to turn a hot plug detect (HPD) status of the display device to a high status. A HPD signal having a low status is transmitted to the host device in response to the first status update signal. A configuration signal is received from the host device. A configuration acknowledgement signal is transmitted to the host device in response to the configuration signal. The HPD signal having the high status is actively transmitted to the host device.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: April 27, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chen Shen, Kai-Yuan Yin, Ti-Ti Chen, Yong-Fei Li
  • Patent number: 10983801
    Abstract: A processor includes a load/store unit that includes one or more load pipelines and one or more store pipelines. Load operations may be issued into the load pipelines out of order with respect to older store operations. If a load operation is executed out or order with an older store operation that writes one or more bytes read by the load operation, and if the store operation is issued shortly after the load operation, such that the load operation is still in the load pipeline when the store operation is issued, some cases of flushing may be converted to replays by detecting the ordering violation while the load operation is still in the load pipeline.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 20, 2021
    Assignee: Apple Inc.
    Inventors: Kulin N. Kothari, Mridul Agarwal
  • Patent number: 10983948
    Abstract: A reconfigurable computing appliance includes a number of computing tiles. Each computing tile includes a reconfigurable processing element and a network fabric interface device configured to communicate over a network fabric. The reconfigurable processing element operates on data received from an I/O input interface and/or data received via the network fabric interface device.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 20, 2021
    Assignee: Raytheon Company
    Inventor: Russell E. Dube
  • Patent number: 10980145
    Abstract: Provided is a patch panel, comprising: a circuit board; and an SFP, SFP+, or QSFP+ connector connected to a plurality of radio frequency coaxial (RF coaxial) connections via conductive traces of the circuit board, the RF coaxial connections configured to extend functionality of the SFP, SFP+, or QSFP+ socket of a computing device coupled to the patch panel from a rear end of the computing device to a front end of the computing device.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: April 13, 2021
    Assignee: Vapor IO, Inc.
    Inventor: Steven White
  • Patent number: 10977040
    Abstract: Methods, systems and computer program products for heuristically invalidating non-useful entries in an array are provided. Aspects include receiving an instruction that is associated with an operand store compare (OSC) prediction for at least one of a store function and a load function. The OSC prediction is stored in an entry of an OSC history table (OHT). Aspects also include executing the instruction. Responsive to determining, based on the execution of the instruction, that data forwarding did not occur, aspects include incrementing a useless OSC prediction counter. Responsive to determining that the useless OSC prediction counter is equal to a predetermined value, aspects also include invalidating the entry of the OHT associated with the instruction.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Raymond Cuffney, Adam Collura, James Bonanno, Jang-Soo Lee, Eyal Naor, Yair Fried, Brian Robert Prasky
  • Patent number: 10970075
    Abstract: An arithmetic processing apparatus includes a shift register configured to store a plurality of transactions each having one or more destinations; and a processor coupled to the shift register and configured to: select a first transaction among the transactions stored in the shift register based on a state of a destination of each of the transactions, determine whether or not the first transaction is issuable, select a second transaction based on destinations of the first transaction when it is determined that the first transaction is not issuable, issue the first transaction when it is determined that the first transaction is issuable, and issue the second transaction when it is determined that the first transaction is not issuable.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: April 6, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Ryo Takata, Tomohiro Nagano
  • Patent number: 10963256
    Abstract: Disclosed embodiments relate to systems and methods for performing instructions to transform matrices into a row-interleaved format. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction having fields to specify an opcode and locations of source and destination matrices, wherein the opcode indicates that the processor is to transform the specified source matrix into the specified destination matrix having the row-interleaved format; and execution circuitry to respond to the decoded instruction by transforming the specified source matrix into the specified RowInt-formatted destination matrix by interleaving J elements of each J-element sub-column of the specified source matrix in either row-major or column-major order into a K-wide submatrix of the specified destination matrix, the K-wide submatrix having K columns and enough rows to hold the J elements.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Raanan Sade, Robert Valentine, Bret Toll, Christopher J. Hughes, Alexander F. Heinecke, Elmoustapha Ould-Ahmed-Vall, Mark J. Charney
  • Patent number: 10956352
    Abstract: A method for detecting and identifying modules of a bus system is provided. The bus system includes a control unit, a bus starting from the control unit, and a plurality of modules connected to the bus. The method includes providing a current sink associated with each of the one or more modules. The current sink includes a transistor. The method includes providing a hall sensor associated with each of the one or more modules. The hall sensor detects a current on a low-side data line of the bus. For each one of the one or more modules: when the hall sensor detects a current on the low-side data line, the method includes maintaining a closed position of the transistor; and when the hall sensor fails to detect a current on the low-side data line, the method includes opening the transistor such that current does not flow to the module.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: March 23, 2021
    Assignee: Continental Automotive Systems, Inc.
    Inventor: Hesam Akbarian
  • Patent number: 10942742
    Abstract: A reconfigurable processing circuit and system are provided. The system allows a user to program machine-level instructions in order to reconfigure the way the circuit behaves, including by adding new operations. The system can include a profile access content-addressable memory (CAM) configured to receive an execution step value from a step counter. The execution step value can be incremented and/or reset by a step management logic. The profile access CAM can select an entry of a profile table based on an opcode and the execution step value, and the processing engine can execute microcode based on the selected entry of the profile table. The profile access CAM can translate the opcode to an internal short instruction identifier in order to select the entry of the profile table. The system can further include an instruction decoding module configured to merge multiple instruction fields into a single effective instruction field.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 9, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Sundeep Amirineni, Mohammad El-Shabani, Sagar Sonar, Kenneth Wayne Patton
  • Patent number: 10936320
    Abstract: A processor core and methods for managing the processor core. The processor core comprises of a plurality of lanes, each lane comprising a copy of a register file logically shared across the plurality lanes and a plurality of functional units, at least two of the functional units sharing a common cache and a common control unit, where the common control unit concurrently dispatches multiple consecutive instances of an instruction corresponding to multiple successive instances of an inner loop to the plurality of functional units of at least a proper subset of the plurality of lanes; and one or more registers of each copy of the register file, each register being configurable to write a data result from at least one of the functional units to a register in a lane-local mode, a lane-forward mode, and a normal mode.
    Type: Grant
    Filed: August 17, 2019
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kattamuri Ekanadham, Manoj Kumar, Jose E. Moreira, Pratap C. Pattnaik, Jessica Hui-Chun Tseng
  • Patent number: 10929137
    Abstract: An arithmetic processing device includes: a pipeline circuit including an instruction fetch circuit, an instruction decoder that performs a first branch misprediction determination for a branch instruction, and issues the instructions in-order, a branch instruction processing circuit which performs a second branch misprediction determination for the branch instruction; and a commit processing circuit that executes a commit processing of the processed instructions in-order.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: February 23, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Hisanari Fujita, Ryohei Okazaki, Takashi Suzuki
  • Patent number: 10922084
    Abstract: An apparatus has processing circuitry supporting vector load and store instructions. In response to a transaction start event, the processing circuitry executes one or more subsequent instructions speculatively. In response to a transaction end event, the processing circuitry commits speculative results of those instructions. Hazard detection circuitry detects whether an inter-element address hazard occurs between an address for data element J for an earlier vector load instruction and an address for data element K for a later vector store instruction, where K and J are not equal. In response to detecting the inter-element address hazard, the hazard detection circuitry triggers the processing circuitry to abort further processing of the instructions following the transaction start event and to prevent the speculative results being committed. This approach can provide faster performance for vectorised code.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: February 16, 2021
    Assignee: ARM Limited
    Inventors: Matthew James Horsnell, Mbou Eyole
  • Patent number: 10915317
    Abstract: The present disclosure relates to a computing device with a multiple pipeline architecture. The multiple pipeline architecture comprises a first and second pipeline for which are concurrently running, where the first pipeline runs at least one cycle ahead of the second pipeline. Special number detection is utilized on the first pipeline, where a special number is a numerical value which yields a predictable result. Upon the detection of a special number, a computation is optimized.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: February 9, 2021
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Liang Han, Xiaowei Jiang
  • Patent number: 10915470
    Abstract: A memory system is disclosed, which relates to technology for an accelerator of a high-capacity memory device. The memory system includes a plurality of memories configured to store data therein, and a pooled memory controller (PMC) configured to perform map computation by reading the data stored in the plurality of memories and storing resultant data produced by the map computation in the plurality of memories.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Sun Woong Kim, Eui Cheol Lim
  • Patent number: 10909054
    Abstract: A method for status monitoring of acceleration kernels in a storage device is provided. The method includes: receiving an asynchronous event reporting (AER) command by a controller of the storage device from a host, the AER command corresponding to a first operation assigned to a first acceleration kernel on an acceleration co-processor by the host; adding the received AER command to a look-up table in the controller; receiving a completion message from the first acceleration kernel corresponding to the first operation; comparing the received completion message to the AER commands in the look-up table; and when a match is found between the received completion message and one of the AER commands in the look-up table, sending a command completion entry to the host.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Divya Subbanna, Vinit Sadanand Apte, Ramdas P. Kachare
  • Patent number: 10901735
    Abstract: An apparatus includes a memory, a memory controller, arithmetic processors, and access circuits corresponding to the arithmetic processors. The memory controller controls a load instruction that reads, from the memory, data to be obtained by the arithmetic processors. The access circuit generates divided instructions by dividing a multicast load instruction, and selects, for each divided instruction, a first access circuit that issues, to the memory controller, a read request for causing the target access circuits to perform responses to the target access arithmetic processors. The first access circuit determines first identification information common to all the target access circuits, and issues, to the memory controller, a single read request to which the first identification information is added, and obtains, from the memory controller, responses to which the first identification information is added, and outputs first data based on the obtained responses to the target arithmetic processors.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: January 26, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Tomohiro Nagano
  • Patent number: 10896043
    Abstract: Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Bret Toll, Alexander F. Heinecke, Christopher J. Hughes, Ronen Zohar, Michael Espig, Dan Baum, Raanan Sade, Robert Valentine, Mark J. Charney, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 10877918
    Abstract: An information handling system includes an I/O device, a first processor die coupled to the I/O device, a second processor die coupled to the first processor die, and to no I/O device, and boot process logic. The boot process logic determines that the first processor die is coupled to the I/O device and that the second processor die is coupled to no I/O device, determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y, and enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z?X, on the second processor die, based upon the determination that the second processor die is coupled to no I/O device.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: December 29, 2020
    Assignee: Dell Products, L.P.
    Inventors: Mukund P. Khatri, Vijay Bharat Nijhawan
  • Patent number: 10872057
    Abstract: An example method of placing kernels of an application in a data processing engine array (DPE) of a system on chip (SOC) includes obtaining a graph of the application having nodes representing the kernels and edges representing communication between the kernels, sorting the kernels based on runtime ratio associated with each of the kernels, processing the sorted kernels sequentially to place into partitions, determining an execution order of kernels in each of the partitions; and generating implementation data for the SOC for implementing the application therein based on the determined partitions and execution order for each of the partitions.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 22, 2020
    Assignee: XILINX, INC.
    Inventors: Prashant S. Rawat, Shail Aditya Gupta