Patents Examined by Hyun Nam
  • Patent number: 11119771
    Abstract: Disclosed are various embodiments for computing 2-body statistics on graphics processing units (GPUs). Various types of two-body statistics (2-BS) are regarded as essential components of data analysis in many scientific and computing domains. However, the quadratic complexity of these computations hinders timely processing of data. According, various embodiments of the present disclosure involve parallel algorithms for 2-BS computation on Graphics Processing Units (GPUs). Although the typical 2-BS problems can be summarized into a straightforward parallel computing pattern, traditional wisdom from (general) parallel computing often falls short in delivering the best possible performance. Therefore, various embodiments of the present disclosure involve techniques to decompose 2-BS problems and methods for effective use of computing resources on GPUs. We also develop analytical models that guide users towards the appropriate parameters of a GPU program.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: September 14, 2021
    Assignee: UNIVERSITY OF SOUTH FLORIDA
    Inventors: Yicheng Tu, Napath Pitaksirianan
  • Patent number: 11113069
    Abstract: A method for implementing of a quick-release Variable Length Vector (VLV) memory access array in the technical field of software programs, which includes the following steps: Step 1: when a pipeline restarts to refresh an out-of-order queue each time, and the number of sending an entry recorded in a sending counter of the entry is equal to the number of returning the entry recorded in a returning counter of the entry, an ID of the entry is kept unchanged, and the ID is used for a next pushed request; Step 2: when the pipeline restarts to refresh the out-of-order queue each time, the number of sending the entry recorded in the sending counter is not equal to the number of returning the entry recorded in the returning counter and mirror resources are not exhausted, the existing entry is released, the ID, the sending counter and the returning counter of the entry are copied to another structure, and N IDs, each of which is in a non-busy status are selected from a free list, and a busy bit of each of the N IDs is
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: September 7, 2021
    Assignee: HUAXIA GENERAL PROCESSOR TECHNOLOGIES INC.
    Inventors: Xiaolong Fei, Lei Wang
  • Patent number: 11106494
    Abstract: Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Robert Pawlowski, Ankit More, Jason M. Howard, Joshua B. Fryman, Tina C. Zhong, Shaden Smith, Sowmya Pitchaimoorthy, Samkit Jain, Vincent Cave, Sriram Aananthakrishnan, Bharadwaj Krishnamurthy
  • Patent number: 11106608
    Abstract: A processing unit includes a processor core that executes a store-conditional instruction that generates a store-conditional request specifying a store target address. The processing unit further includes a reservation register that records shared memory addresses for which the processor core has obtained reservations and a cache that services the store-conditional request by conditionally updating the shared memory with the store data based on the reservation register indicating a reservation for the store target address. The cache includes a blocking state machine configured to protect the store target address against access by any conflicting memory access request snooped on a system interconnect during a protection window extension following servicing of the store-conditional request.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 31, 2021
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Guy L. Guthrie, Hugh Shen, Sanjeev Ghai
  • Patent number: 11099853
    Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 24, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cedric Lichtenau, Reid Copeland, Petra Leber, Silvia M. Mueller, Jonathan D. Bradbury, Xin Guo
  • Patent number: 11099847
    Abstract: A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state and transition to a second execution state responsive to executing a control transfer instruction. Responsive to executing a target instruction of the control transfer instruction, the processing logic further transitions to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and raises an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Ravi L. Sahita, Xiaoning Li
  • Patent number: 11086800
    Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 10, 2021
    Assignee: Apple Inc.
    Inventors: Jeremy C. Andrus, Joseph R. Auricchio, Russell A. Blaine, Daniel A. Chimene, Simon M. Douglas, Landon J. Fuller, Yevgen Goryachok, John K. Kim-Biggs, Arnold S. Liu, James M. Magee, Daniel A. Steffen, Roberto G. Yepez
  • Patent number: 11080053
    Abstract: Techniques and mechanisms described herein include a signal processor implemented as an overlay on a field-programmable gate array (FPGA) device that utilizes special purpose, hardened intellectual property (IP) modules such as memory blocks and digital signal processing (DSP) cores. A Processing Element (PE) is built from one or more DSP cores connected to additional logic. Interconnected as an array, the PEs may operate in a computational model such as Single Instruction-Multiple Thread (SIMT). A software hierarchy is described that transforms the SIMT array into an effective signal processor.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: August 3, 2021
    Assignee: Nextera Video, Inc.
    Inventors: John E. Deame, Steven Kaufmann, Liviu Voicu
  • Patent number: 11061843
    Abstract: A data storage device includes a case and a connector housed within the case. The connector includes a first connection interface having a plurality of connection fingers and a second connection interface having a plurality of springs. The case is positionable within a data storage device port such that the data storage device is completely disposed within the data storage device port when used.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: July 13, 2021
    Inventor: Martin Kuster
  • Patent number: 11030136
    Abstract: An aspect includes memory access optimization for an I/O adapter in a processor complex. A memory block distance is determined between the I/O adapter and a memory block location in the processor complex and determining one or more memory movement type criteria between the I/O adapter and the memory block location based on the memory block distance. A memory movement operation type is selected based on a memory movement process parameter and the one or more memory movement type criteria. A memory movement process is initiated between the I/O adapter and the memory block location using the memory movement operation type.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: June 8, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patricia G. Driever, Jerry W. Stevens
  • Patent number: 11016913
    Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g. coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: May 25, 2021
    Assignee: Apple Inc.
    Inventors: Harshavardhan Kaushikkar, Christopher D. Shuler, Srinivasa Rangan Sridharan, Yu Zhang, Kaushik Kannan, Deniz Balkan
  • Patent number: 11010326
    Abstract: A method and apparatus are provided to receive a voltage at a first value at a voltage reducing adaptor, ascertain a voltage supply requirement for the memory arrangement to obtain and ascertained voltage supply requirement, reduce the voltage from the first value to the ascertained voltage supply requirement within the adaptor and supply the voltage at the ascertained voltage supply requirement to the memory arrangement.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: May 18, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Charles Neumann, Robert P. Ryan
  • Patent number: 10996952
    Abstract: Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 4, 2021
    Assignee: SiFive, Inc.
    Inventors: Krste Asanovic, Andrew Waterman
  • Patent number: 10990557
    Abstract: A transmission interface communicating method used in a display device that includes the steps outlined below is provided. A first status update signal is received from a host device to turn a hot plug detect (HPD) status of the display device to a high status. A HPD signal having a low status is transmitted to the host device in response to the first status update signal. A configuration signal is received from the host device. A configuration acknowledgement signal is transmitted to the host device in response to the configuration signal. The HPD signal having the high status is actively transmitted to the host device.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: April 27, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chen Shen, Kai-Yuan Yin, Ti-Ti Chen, Yong-Fei Li
  • Patent number: 10983948
    Abstract: A reconfigurable computing appliance includes a number of computing tiles. Each computing tile includes a reconfigurable processing element and a network fabric interface device configured to communicate over a network fabric. The reconfigurable processing element operates on data received from an I/O input interface and/or data received via the network fabric interface device.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 20, 2021
    Assignee: Raytheon Company
    Inventor: Russell E. Dube
  • Patent number: 10983801
    Abstract: A processor includes a load/store unit that includes one or more load pipelines and one or more store pipelines. Load operations may be issued into the load pipelines out of order with respect to older store operations. If a load operation is executed out or order with an older store operation that writes one or more bytes read by the load operation, and if the store operation is issued shortly after the load operation, such that the load operation is still in the load pipeline when the store operation is issued, some cases of flushing may be converted to replays by detecting the ordering violation while the load operation is still in the load pipeline.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 20, 2021
    Assignee: Apple Inc.
    Inventors: Kulin N. Kothari, Mridul Agarwal
  • Patent number: 10977040
    Abstract: Methods, systems and computer program products for heuristically invalidating non-useful entries in an array are provided. Aspects include receiving an instruction that is associated with an operand store compare (OSC) prediction for at least one of a store function and a load function. The OSC prediction is stored in an entry of an OSC history table (OHT). Aspects also include executing the instruction. Responsive to determining, based on the execution of the instruction, that data forwarding did not occur, aspects include incrementing a useless OSC prediction counter. Responsive to determining that the useless OSC prediction counter is equal to a predetermined value, aspects also include invalidating the entry of the OHT associated with the instruction.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Raymond Cuffney, Adam Collura, James Bonanno, Jang-Soo Lee, Eyal Naor, Yair Fried, Brian Robert Prasky
  • Patent number: 10980145
    Abstract: Provided is a patch panel, comprising: a circuit board; and an SFP, SFP+, or QSFP+ connector connected to a plurality of radio frequency coaxial (RF coaxial) connections via conductive traces of the circuit board, the RF coaxial connections configured to extend functionality of the SFP, SFP+, or QSFP+ socket of a computing device coupled to the patch panel from a rear end of the computing device to a front end of the computing device.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: April 13, 2021
    Assignee: Vapor IO, Inc.
    Inventor: Steven White
  • Patent number: 10970075
    Abstract: An arithmetic processing apparatus includes a shift register configured to store a plurality of transactions each having one or more destinations; and a processor coupled to the shift register and configured to: select a first transaction among the transactions stored in the shift register based on a state of a destination of each of the transactions, determine whether or not the first transaction is issuable, select a second transaction based on destinations of the first transaction when it is determined that the first transaction is not issuable, issue the first transaction when it is determined that the first transaction is issuable, and issue the second transaction when it is determined that the first transaction is not issuable.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: April 6, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Ryo Takata, Tomohiro Nagano
  • Patent number: 10963256
    Abstract: Disclosed embodiments relate to systems and methods for performing instructions to transform matrices into a row-interleaved format. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction having fields to specify an opcode and locations of source and destination matrices, wherein the opcode indicates that the processor is to transform the specified source matrix into the specified destination matrix having the row-interleaved format; and execution circuitry to respond to the decoded instruction by transforming the specified source matrix into the specified RowInt-formatted destination matrix by interleaving J elements of each J-element sub-column of the specified source matrix in either row-major or column-major order into a K-wide submatrix of the specified destination matrix, the K-wide submatrix having K columns and enough rows to hold the J elements.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Raanan Sade, Robert Valentine, Bret Toll, Christopher J. Hughes, Alexander F. Heinecke, Elmoustapha Ould-Ahmed-Vall, Mark J. Charney