Abstract: A method for controlling a serial port information of a server host is provided. At first, a basic input/output system of the server host is activated. Then the BIOS reads a first port state value of a first input/output port of a MOS chip. Then an information output state of a serial port of a server host is determined according to the first port state value of the first input/output port, wherein the information output state is related to whether to output information of the serial port.

Abstract: A system and method for efficiently preventing visible side-effects in the memory hierarchy during speculative execution is disclosed. Hiding the side-effects of executed instructions in the whole memory hierarchy is both expensive, in terms of performance and energy, and complicated. A system and method is disclosed to hide the side-effects of speculative loads in the cache(s) until the earliest time these speculative loads become non-speculative. A refinement is disclosed where loads that hit in the L1 cache are allowed to proceed by keeping their side-effects on the L1 cache hidden until these loads become non-speculative, and all other speculative loads that miss in the cache(s) are prevented from executing until they become non-speculative. To limit the performance deterioration caused by these delayed loads, a system and method is disclosed that augments the cache(s) with a value predictor or a re-computation engine that supplies predicted or recomputed values to the loads that missed in the cache(s).

Abstract: Technology for fusing an add-immediate instruction with a load-immediate instruction (or store-immediate instruction) in a microprocessor. This can result in quicker address generation while performing a load and store operation.

Abstract: Aspects for vector combination in neural network are described herein. The aspects may include a direct memory access unit configured to receive aa first vector, a second vector, and a controller vector. The first vector, the second vector, and the controller vector may each include one or more elements indexed in accordance with a same one-dimensional data structure. The aspects may further include a computation module configured to select one of the one or more control values, determine that the selected control value satisfies a predetermined condition, and select one of the one or more first elements that corresponds to the selected control value in the one-dimensional data structure as an output element based on a determination that the selected control value satisfies the predetermined condition.

Abstract: Disclosed herein is a technique for managing I/O requests transmitted between a computing device and a storage device. According to some embodiments, the technique can be implemented by the computing device, and include providing at least one I/O request to a submission queue configured to store a plurality of I/O requests. In conjunction with providing the at least one I/O request, the computing device can identify that at least one condition associated with the submission queue—and/or a completion queue—is satisfied, where efficiency gains can be achieved. In turn, the computing device can (1) update an operating mode of the storage device to cause the storage device to cease interrupt issuances to the computing device when I/O requests are completed by the storage device, and (2) update an operating mode of the computing device to cause the computing device to periodically check the completion queue for completed I/O requests.

Abstract: An apparatus includes a memory and a processor, where the processor includes a performance counter that stores performance data for the processor. The apparatus store plural groups of calculation instructions in the memory. The apparatus calculates a first execution result by executing, based on the performance data obtained from the performance counter, each calculation instruction included in a first group of calculation instructions, and selects a second group of calculation instructions to be executed next, from among the plural groups of calculation instructions, based on the calculated first execution result.

Abstract: This data-processing device includes a unit for processing data, a storage memory and a buffer-memory device configured to contain a first group of data relative to a first context and exchange data between the processing unit and the first group of data. The buffer-memory device is further configured to contain a second group of data relative to a second context and, upon reception of a context-switching instruction, exchange data between the processing unit and the second group of data, in place of the first group of data. The data-processing device further includes a context-switching device configured to emit the context-switching instruction, select a group of data recorded in the storage memory, copy the first group of data to the storage memory and copy the selected group of data to the buffer-memory device.

Abstract: A Baseboard Management Controller (BMC) (125) that may configure itself is disclosed. The BMC (125) may include an access logic (415) to determine a configuration of a chassis (105) that includes the BMC (125). The BMC (125) may also include a built-in self-configuration logic (420) to configure the BMC (125) responsive to the configuration of the chassis (105). The BMC (125) may self-configure without using any BIOS, device drivers, or operating systems.

Abstract: An apparatus comprises execution circuitry to perform operations on source data values and to generate result data values; issue circuitry comprising one or more issue queues identifying pending operations awaiting performance by the execution circuitry, and selection circuitry to select pending operations to issue to the execution circuitry; data value cache storage comprising first and second cache regions; and cache control circuitry to control the storing to the first cache region of result data values generated by the execution circuitry and the eviction of stored result data values from the first cache region in response to newly generated result data values being stored in the first cache region; the cache control circuitry being configured to store to the second cache region result data values required as source data values for one or more oldest pending operations identified by the one or more issue queues and to inhibit eviction of a given result data value stored in the second cache region until in

Abstract: In order to be able to arrange a master module (M), slave modules (S), and conventional plug modules (K) in a freely configurable manner in a modular plug system, a modular frame (22) is provided with a circuit board (1) which includes at least one continuous conductor path and preferably more than one connection pad.

Abstract: Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.

Abstract: Disclosed are various embodiments for computing 2-body statistics on graphics processing units (GPUs). Various types of two-body statistics (2-BS) are regarded as essential components of data analysis in many scientific and computing domains. However, the quadratic complexity of these computations hinders timely processing of data. According, various embodiments of the present disclosure involve parallel algorithms for 2-BS computation on Graphics Processing Units (GPUs). Although the typical 2-BS problems can be summarized into a straightforward parallel computing pattern, traditional wisdom from (general) parallel computing often falls short in delivering the best possible performance. Therefore, various embodiments of the present disclosure involve techniques to decompose 2-BS problems and methods for effective use of computing resources on GPUs. We also develop analytical models that guide users towards the appropriate parameters of a GPU program.

Abstract: A method for implementing of a quick-release Variable Length Vector (VLV) memory access array in the technical field of software programs, which includes the following steps: Step 1: when a pipeline restarts to refresh an out-of-order queue each time, and the number of sending an entry recorded in a sending counter of the entry is equal to the number of returning the entry recorded in a returning counter of the entry, an ID of the entry is kept unchanged, and the ID is used for a next pushed request; Step 2: when the pipeline restarts to refresh the out-of-order queue each time, the number of sending the entry recorded in the sending counter is not equal to the number of returning the entry recorded in the returning counter and mirror resources are not exhausted, the existing entry is released, the ID, the sending counter and the returning counter of the entry are copied to another structure, and N IDs, each of which is in a non-busy status are selected from a free list, and a busy bit of each of the N IDs is

Abstract: A processing unit includes a processor core that executes a store-conditional instruction that generates a store-conditional request specifying a store target address. The processing unit further includes a reservation register that records shared memory addresses for which the processor core has obtained reservations and a cache that services the store-conditional request by conditionally updating the shared memory with the store data based on the reservation register indicating a reservation for the store target address. The cache includes a blocking state machine configured to protect the store target address against access by any conflicting memory access request snooped on a system interconnect during a protection window extension following servicing of the store-conditional request.

Abstract: Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.

Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.

Abstract: A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state and transition to a second execution state responsive to executing a control transfer instruction. Responsive to executing a target instruction of the control transfer instruction, the processing logic further transitions to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and raises an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction.

Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.

Abstract: Techniques and mechanisms described herein include a signal processor implemented as an overlay on a field-programmable gate array (FPGA) device that utilizes special purpose, hardened intellectual property (IP) modules such as memory blocks and digital signal processing (DSP) cores. A Processing Element (PE) is built from one or more DSP cores connected to additional logic. Interconnected as an array, the PEs may operate in a computational model such as Single Instruction-Multiple Thread (SIMT). A software hierarchy is described that transforms the SIMT array into an effective signal processor.

Abstract: A data storage device includes a case and a connector housed within the case. The connector includes a first connection interface having a plurality of connection fingers and a second connection interface having a plurality of springs. The case is positionable within a data storage device port such that the data storage device is completely disposed within the data storage device port when used.