Patents Examined by Idriss N Alrobaye
  • Patent number: 11914546
    Abstract: An information handling system includes a memory and a baseboard management controller. The memory stores one or more device update packages, and each of the first device update packages includes an inter-integrated circuit payload. The baseboard management controller receives a first device update package, and stores the first device update package in the memory. In response to the first device update package being stored in the memory, the baseboard management controller launches a handler. The baseboard management controller retrieves a bus number and an address for a target device identified in the first device update package. The baseboard management controller parses data in a body of the inter-integrated circuit payload of the first device update package, and executes inter-integrated circuit commands in the body to provide a firmware image update to the target device.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: February 27, 2024
    Assignee: Dell Products L.P.
    Inventors: Yogesh P. Kulkarni, Chandrasekhar Mugunda, Rui An, Akshata Sheshagiri Naik
  • Patent number: 11914902
    Abstract: Shared memory access in a distributed system, including: receiving a memory access request associated with a time value; determining, based on the time value, an entry in a translation lookaside buffer (TLB); and determining, based on the entry, whether to allow the memory access request.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: February 27, 2024
    Assignee: GHOST AUTONOMY INC.
    Inventors: John Hayes, Volkmar Uhlig, Richard A. Swetz, Daniel P. Potts, Aaron Carroll
  • Patent number: 11907144
    Abstract: Techniques to reduce the latency in notifying that space in a memory has been freed up are described. For example, when moving data from on-chip memory of a computing engine to system memory, the computing engine can be notified that its on-chip memory is free before an acknowledgment is provided by the system memory that the data being moved has been written into the system memory. The computing engine can be given access to the on-chip memory sooner by generating an early semaphore update based on a determination that the set of data being moved to system memory has been read out from the on-chip memory. The early semaphore update need not wait for the acknowledgement from the system memory, thus reducing the latency of notifying the computing engine that the on-chip memory is free.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: February 20, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Raymond S. Whiteside, Thomas A. Volpe
  • Patent number: 11907139
    Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: February 20, 2024
    Assignee: Rambus Inc.
    Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
  • Patent number: 11907155
    Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. In a first phase of a plurality of phases in each assignment period of an assignment stage after a synchronization stage, the first slave device is configured to control the alert handshake control line to a second voltage level via the alert handshake pin. In the phases of each of the assignment periods except for the first phase, a first slave device of the slave devices is configured to control the alert handshake control line to communicate with the slave devices via the alert handshake pin. The first phase corresponds to a first slave device.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: February 20, 2024
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Kang-Fu Chiu, Chih-Hung Huang, Hao-Yang Chang
  • Patent number: 11900130
    Abstract: Systems involving distributed control functions are described herein. Each member or device within the system has responsibility for controlling part of the system's behavior, and includes logic to determine what action, if any, will follow as a response to determining information or receiving information from other members or devices within the system. A change of status of one member of a system may provide a basis for action by another member of the system. Status may be the result of sensing a condition of the environment, sensing the condition of a component, receiving the output of a conventional sensor, and/or sensing the condition of a link between components. In some embodiments, action taken by a member of the system may include collecting data during law enforcement activities.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: February 13, 2024
    Assignee: Axon Enterprise, Inc.
    Inventors: Daniel J. Wagner, Mark A. Hanchett, Aaron J. Kloc, Tyler J. Conant
  • Patent number: 11899603
    Abstract: A connection hub includes a housing coupled to a universal serial bus (USB) cable that includes a plug for electronic devices. A housing of the connection hub includes a number (N) of ports and switches. The connection hub includes 1-to-N connections between the USB cable and the N ports, where each of the N ports includes a data line and/or a power line. The switches each include a mechanical component that is movable between a first position that activates a private mode and a second position that deactivates the private mode. A data line of a particular port is disabled when the private mode is activated, and a particular power line of the particular port is enabled when either the private mode is activated and when the private mode is deactivated.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: February 13, 2024
    Assignee: OSOM PRODUCTS, INC.
    Inventors: Jason Sean Gagne-Keats, David John Evans, V, James Kim, Evan Jackson, Nicholas Franco, Edith Silver Walker
  • Patent number: 11892964
    Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: February 6, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Oren Duer, Dror Goldenberg
  • Patent number: 11892957
    Abstract: A system is disclosed. An upstream interface enables communication with a processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for data, and a storage device acceleration module to assist the acceleration module in executing the acceleration instruction.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 6, 2024
    Inventors: Ramdas P. Kachare, Fred Worley, Harry Rogers, Wentao Wu, Nagarajan Subramaniyan
  • Patent number: 11892960
    Abstract: A display includes a keyboard, video mouse (KVM) switch that interfaces plural peripheral communication ports and plural information handling system ports. The KVM switch in a first configuration accepts video from one of the information handling system ports for presentation as visual images at a display panel and interfaces all of the plural peripheral communication ports with the one of the information handling system ports. When an end user commands a change to a different information handling system port and the KVM switch detects that a predetermined information transfer is taking place at the one of the information handling system ports, such as a bulk isochronous transfer or greater than a predetermined bandwidth utilization, the KVM switch changes the interface of peripheral devices and video to the second information handling system port while maintaining the transfer of the predetermined type of information with the first information handling system port.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: February 6, 2024
    Assignee: Dell Products L.P.
    Inventors: Vui Khen Thien, Tze Fung Chung
  • Patent number: 11886363
    Abstract: Disclosed are systems, computer-readable mediums, and methods for managing client performance in a storage system. In one example, the storage system receives a request from a client to write data to the storage system. The storage system estimates, based on a system metric associated with the storage system reflecting usage of the storage system, a requested write QoS parameter for storing the data by the storage system during a first time period. The storage system further determines a target write QoS parameter for the client based on the estimated requested write QoS parameter and an allocated write QoS parameter for the client. Then, the storage system independently regulates read performance and write performance of the client using a controller to adjust the write performance toward the determined target write QoS parameter within the first time period based on feedback regarding the estimated requested write QoS parameter.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: January 30, 2024
    Assignee: NetApp, Inc.
    Inventors: Austino Longo, Jared Cantwell
  • Patent number: 11886885
    Abstract: One embodiment of the present invention sets forth a data pipeline, which includes a first mousetrap element and a second mousetrap element in a first pipeline stage. Each mousetrap element includes a request latch that, when enabled, allows a request signal to pass from the first pipeline stage to a second pipeline stage following the first pipeline stage in the data pipeline. Each mousetrap element also includes a data latch that, when enabled, allows a data element to pass from the first pipeline stage to the second pipeline stage. Each mousetrap element further includes a latch controller that enables and disables the request and data latches based on a phase signal that alternates between a first value that configures the first mousetrap element to transmit data to the second pipeline stage and a second value that configures the second mousetrap element to transmit data to the second pipeline stage.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: January 30, 2024
    Assignee: NVIDIA Corporation
    Inventor: Benjamin Andrew Keller
  • Patent number: 11886373
    Abstract: An authentication and information system for use in a surgical stapling system includes a microprocessor configured to demultiplex data from a plurality of components in the surgical system. The authentication and information system can include one wire chips and a coupling assembly with a communication connection.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: January 30, 2024
    Assignee: Covidien LP
    Inventors: Ethan Collins, David Durant, John Hryb
  • Patent number: 11886366
    Abstract: An apparatus coupled to a single-wire serial bus through a line driver is configured to determine that a first sequence start condition (SSC) has been initiated when the single-wire serial bus transitions from first to second signaling states. The line driver drives the single-wire serial bus to the first signaling state after a first duration to complete the first SSC, and an arbitration window with plural timeslots is provided when the line driver presents a high impedance to the single-wire serial bus after the first SSC. The line driver drives the single-wire serial bus to the first signaling state in each timeslot of the plural timeslots in which the single-wire serial bus is driven to the second signaling state. After the arbitration window has expired, the apparatus transmits a second SSC and a Manchester encoded command addressed to at least one slave device.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: January 30, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Umesh Srikantiah, Richard Dominic Wietfeldt
  • Patent number: 11886357
    Abstract: A memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips include a first storage chip set and a second storage chip set, the storage chips in the first storage chip set are configured to perform information interaction with the control chip by adopting a first clock signal, the storage chips in the second storage chip set are configured to perform information interaction with the control chip by adopting a second clock signal, and phase of the first clock signal is different from phase of the second clock signal.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: January 30, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Shu-Liang Ning, Jun He, Zhan Ying, Jie Liu
  • Patent number: 11880328
    Abstract: The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system, and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: January 23, 2024
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Yao Zhang, Shaoli Liu, Jun Liang, Yu Chen
  • Patent number: 11880329
    Abstract: The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: January 23, 2024
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Shaoli Liu, Zhen Li, Yao Zhang
  • Patent number: 11880330
    Abstract: The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: January 23, 2024
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Shaoli Liu, Zhen Li, Yao Zhang
  • Patent number: 11880301
    Abstract: Techniques for enabling efficient guest OS access to PCIe configuration space are provided. In one set of embodiments, a hypervisor can reserve a single host physical memory page in the host physical memory of a host system and can populate the single host physical memory page with a value indicating non-presence of PCIe device functions. The hypervisor can then create, for each guest physical memory page in a guest physical memory of a virtual machine (VM) corresponding to a PCIe configuration space of an absent PCIe device function in the VM, a mapping in the hypervisor's second-level page tables that maps the guest physical memory page to the single host physical memory page.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: January 23, 2024
    Assignee: VMware LLC
    Inventors: Andrei Warkentin, Alexander Fainkichen, Ye Li, Regis Duchesne, Cyprien Laplace, Shruthi Hiriyuru, Sunil Kotian
  • Patent number: 11876702
    Abstract: A network interface controller (NIC) capable of facilitating efficient memory address translation is provided. The NIC can be equipped with a host interface, a cache, and an address translation unit (ATU). During operation, the ATU can determine an operating mode. The operating mode can indicate whether the ATU is to perform a memory address translation at the NIC. The ATU can then determine whether a memory address indicated in the memory access request is available in the cache. If the memory address is not available in the cache, the ATU can perform an operation on the memory address based on the operating mode.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: January 16, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Abdulla M. Bataineh, Thomas L. Court, Hess M. Hodge