Patents Examined by Idriss N Alrobaye
  • Patent number: 11513979
    Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Rajesh M. Sankaran, David J. Harriman, Sean O. Stalley, Rupin H. Vakharwala, Ishwar Agarwal, Pratik M. Marolia, Stephen R. Van Doren
  • Patent number: 11516936
    Abstract: A hybrid management cable includes a cable connector having a first cable sub-connector and a second cable sub-connector, The cable connector connects to a hybrid management switch connector on a hybrid management switch and, in response, engages the first cable sub-connector with a first hybrid management switch sub-connector on the hybrid management switch connector, and engages the second cable sub-connector with a second hybrid management switch sub-connector on the hybrid management switch connector. A cable conduit extends from the cable connector. A first management data transmission medium is connected to the first cable sub-connector, located in the cable conduit, and extends along the length of the cable conduit. A second management data transmission medium is connected to the second cable sub-connector, located in the cable conduit and isolated from the first management data transmission medium, and extends along the length of the cable conduit.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 29, 2022
    Assignee: Dell Products L.P.
    Inventors: Shree Rathinasamy, Victor Teeter
  • Patent number: 11513988
    Abstract: A method, computer program product, and computing system for receiving, at a local node, a request to buffer data on a remote persistent cache memory system of a remote node. A target memory address within the remote persistent cache memory system may be sent from the local node via a remote procedure call (RPC). The data may be sent from the local node to the target memory address within the remote persistent cache memory system via a remote direct memory access (RDMA) command.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: November 29, 2022
    Assignee: EMC IP Holding Company, LLC
    Inventors: Oran Baruch, Ronen Gazit, Jenny Derzhavetz, Yuri Chernyavsky
  • Patent number: 11507528
    Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 11507527
    Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 22, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler J. Saleh, Ruijin Wu
  • Patent number: 11500789
    Abstract: An apparatus includes a bi-phase mark coded (BMC) input port configured to receive BMC signals from a universal serial bus (USB) cable. The apparatus further includes a threshold adjustment circuit configured to generate a threshold, and a comparator configured to compare an input BMC signal from the BMC input port and the threshold and based on the comparison, generate an adjusted input BMC signal. The threshold adjustment circuit is further configured to adjust the threshold based upon the input BMC signal.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: November 15, 2022
    Assignee: Microchip Technology Incorporated
    Inventors: Atish Ghosh, Hari Kishore Rajendran, Sandhya Asokan
  • Patent number: 11500802
    Abstract: A direct memory access (DMA) engine can be used to multicast data from system memory to a target memory for loading into an array. The DMA engine may include a controller that is configured to receive a data transfer request, and generate a set of write operations for the output interface. The set of write operations can include, for each of multiple partitions of the target memory, a write operation to write usable data from the multicast data to an address offset in the corresponding partition, and an additional write operation to write filler data from the multicast data to a null device address.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: November 15, 2022
    Assignee: Amazon Technologies. Inc.
    Inventors: Kun Xu, Ron Diamant, Patricio Kaplan, Henry Wang
  • Patent number: 11500554
    Abstract: An access revocation system for removing user data from a service provider device includes a processing device and a memory storing instructions for performing an access revocation method. The method includes receiving user data from a user device via a data channel, storing the user data in a data storage module, and receiving an access revocation message via a request channel separate from the data channel. The method also includes decrypting the access revocation message and performing at least one action defined by the access revocation message, the at least one action including scrubbing of user data from the data storage module.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: November 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Doga Tav, Wayne F. Tackabury
  • Patent number: 11494316
    Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: James R. Magro, Kedarnath Balakrishnan, Brendan T. Mangan
  • Patent number: 11494329
    Abstract: A method for conducting bus arbitration in a hardware tester system comprising a single master controller and a multi-master controller comprises configuring the single master controller with arbitration logic operable to communicate on a bus in the hardware tester system using a same arbitration scheme as the multi-master controller, wherein the single master controller and the multi-master controller are connected to the bus. Further, responsive to a determination by the arbitration logic that the multi-master controller controls the bus, the method comprises withdrawing the single master controller from attempting to control the bus.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: November 8, 2022
    Assignee: Advantest Corporation
    Inventors: Yogen Krishnapillai, Linden Hsu, Mike Bautista
  • Patent number: 11487458
    Abstract: Embodiments of the present invention provide a computer system, a computer program product, and a method that comprises collecting data capable of being replicated from a computing device; detecting risks of the computing device, wherein detecting risks comprises detecting the computing device's surroundings, location, speed, and condition; initiating data replication on the computing device once the risks are determined to reach a predetermined threshold; and storing the replicated data within a cloud storage system using a 5G network.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Craig M. Trim, Rashida A. Hodge, Gandhi Sivakumar, Kushal Patel, Sarvesh S. Patel
  • Patent number: 11487554
    Abstract: The present invention relates to a data processing method, including the steps of intercepting a signal within a communications channel between a predefined peripheral device for a computing system and an application executing on the computing system and processing the signal and performing one or more actions in response to the processing. At least one action affects onward transmission of one or more signals within the communications channel. A data processing system is also described.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: November 1, 2022
    Assignee: SPARKLE CS LTD
    Inventors: Judd Ferrer, Mark Brighton
  • Patent number: 11487435
    Abstract: A system and method for efficiently storing and accessing large volumes of metadata persistent on Non-Volatile Memory (NVM) storage systems is provided. The system applies log-structured, Copy-on-Write (CoW) B+ tree methods, and supports a core-affine data and resource partitioning approaches on the system's architecture and platform with a high-degree of parallelism within the CPU, NVMe storage, and networking devices. The subject system and method efficiently indexes both in-core (DRAM resident) and out-of-core (NVM resident) metadata, supports a variety of data access patterns, supports CoW features and provides verifiable data safety and integrity capabilities. The present system minimizes latencies over all aspects of the metadata management and access path by leveraging core-affine resource partitioning with runtime environment providing lightweight user-level threads with low-latency context switching that execute within the exclusive context of a dedicated CPU core, and partitioned resources.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: November 1, 2022
    Assignee: DATADIRECT NETWORKS INC.
    Inventors: Zhiwei Sun, Yuhua Guo, Jason Micah Cope, Eric Barton
  • Patent number: 11481349
    Abstract: A dynamic switching method is applied to an electronic switching device. Judge whether insertion and withdrawal times between the electronic switching device and a USB cable reach a preset threshold value. Start a UART function of the electronic switching device temporarily. Judge whether an instruction of starting the UART function sent by the USB cable is received. If a recognition program unit receives the instruction of starting the UART function, the recognition program unit starts the UART function. Execute the UART function. Judge whether the electronic switching device receives an instruction of stopping the UART function. Switch to an initial status. Change a start value of a UART circuit unit into an initial value of the UART circuit unit. Charge the electronic switching device through the USB cable.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: October 25, 2022
    Assignee: Cheng Uei Precision Industry Co., Ltd.
    Inventor: Chin Huang Tseng
  • Patent number: 11483511
    Abstract: An information processing device includes a processor, a plurality of connectors that output video signals to a plurality of connected external displays, a plurality of detectors that detect connection states of the plurality of connectors to the plurality of external displays, a plurality of switches that switch paths between a plurality of output ports and the plurality of connectors, and a controller that controls a switching operation of the plurality of switches. The controller has setting information that defines a relationship between the connection states of the plurality of connectors and at least one connector that outputs at least one of video signals among the plurality of connectors, and controls a switching operation of the plurality of switches based on the connection states detected by the plurality of detectors and the setting information. The setting information is set by the user.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: October 25, 2022
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hironori Ueda, Shinya Sato
  • Patent number: 11474788
    Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: October 18, 2022
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Nitin Chawla, Tanmoy Roy, Anuj Grover, Giuseppe Desoli
  • Patent number: 11474964
    Abstract: A configurable input/output device includes a plurality of input/output terminals, a routing module, and a first universal input/output channel. The input/output terminals are connected a plurality of field devices. The input/output terminals receive a plurality of input signals from the field devices, and output a plurality of output signals to the field devices. At least two of the input signals are different, at least two of the output signals are different, and at least two the field devices are different. The routing module is connected to the input/output terminals. The first universal input/output channel is connected to the routing module. The routing module controls connections between the first universal input/output channel and the input/output terminals. The routing module also controls the transceiving sequence for the input signals and the output signals.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: October 18, 2022
    Assignee: MOXA INC.
    Inventor: Kun-Nan Wu
  • Patent number: 11474735
    Abstract: An operation method of a storage device configured to communicate with an external device through an interface channel includes receiving an indicator of a first throttling level of a plurality of throttling levels from the external device, setting a first operation parameter based on a throttling predefined table (PDT) including a relationship between the plurality of throttling levels and a plurality of throttling performances, such that the interface channel has a first throttling performance from among the plurality of throttling performances, the first throttling performance corresponding to the first throttling level, receiving a first input/output (I/O) request from the external device through the interface channel having the first throttling performance caused by the setting of the first operation parameter, and processing a first operation corresponding to the first I/O request through the interface channel having the first throttling performance.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: October 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangwon Jung, Jinsoo Yoo, Hyeongyu Cho
  • Patent number: 11467742
    Abstract: An integrated circuit (IC) includes a memory manager having a plurality of memory ports, each configured to communicate with a corresponding floating memory block. The IC includes a first interconnect for a first domain, wherein the first interconnect has a first set of fixed ports configured to communicate with memory blocks dedicated to the first domain and a first set of floating ports configured to communicate with the memory manager, and a second interconnect for a second domain, wherein the second interconnect has a second set of fixed ports configured to communicate with memory blocks dedicated to the second domain and a second set of floating ports configured to communicate with the memory manager. The memory manager is configured to allocate a first portion of the memory ports to the first set of floating ports and a second portion of the memory ports to the second set of floating ports.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: October 11, 2022
    Assignee: NXP USA, Inc.
    Inventors: Ankur Behl, Rakesh Pandey
  • Patent number: 11461617
    Abstract: According to an embodiment, a neural network device includes a plurality of cores, and a plurality of routers. Each of the plurality of routers includes an input circuit and an output circuit. Each of the plurality of cores transmits at least one of forward direction data propagating in the neural network in a forward direction and reverse direction data propagating in the neural network in a reverse direction. The input circuit receives the forward direction data and the reverse direction data from any one of the plurality of cores and the plurality of routers. The output circuit or the input circuit selectively deletes the reverse direction data stored based on a request signal for requesting reception of data.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 4, 2022
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kumiko Nomura, Takao Marukame