Patents Examined by Idriss N Alrobaye
  • Patent number: 10810476
    Abstract: The invention relates to an electronic circuit for interconnecting a smartcard chip with a peripheral device, comprising: —a dedicated communication interface adapted to communicate with a smartcard chip; —a configurable communication interface adapted to communicate with a peripheral device; —a configuration module adapted to receive on said dedicated communication interface a request for configuring the configurable communication interface, adapted to configure the communication protocol of the configurable communication interface with the peripheral device based on the received request; —a bridging module adapted for converting data exchanged between the peripheral device and the smartcard chip through the dedicated communication interface and the configurable communication interface.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: October 20, 2020
    Assignee: THALES DIS FRANCE SA
    Inventors: Michel Thill, Alain Pomet
  • Patent number: 10809768
    Abstract: An intelligent platform integrates with an intelligent portable device or intelligent core to provide a dynamic computer that may serve as any of: a pad, a tablet computing device, a netbook computer, and a notebook computer. The operations of the integrated device are determined by the connected intelligent core's CPU architecture and its installed operating system. The intelligent platform includes a housing and a core slot located behind a display for accommodating the intelligent core. A core connector is provided on an inner wall of the core slot for interconnecting with a compatible connector of the inserted intelligent core. A control unit continually communicates with the intelligent core through signals carried by the connector, refreshes image received from the intelligent core on its touch-sensitive display, and sends touch-input commands from the touchable panel of the touch-sensitive display to the intelligent core.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 20, 2020
    Assignee: ICE COMPUTER, INC.
    Inventors: Shang-Che Cheng, Wei-Han Wu, Chia-Ming Lin
  • Patent number: 10795838
    Abstract: An embodiment of a semiconductor apparatus may include technology to detect a collision for a read request of an electronic storage device, and read data for the read request directly from a transfer buffer if the collision is detected. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Peng Li, David J. Pelster, William Harper
  • Patent number: 10789192
    Abstract: A method and system for programming a microcontroller (MCU) to implement a data transfer, the MCU having a flash memory, a central processing unit (CPU) and a direct memory access controller (DMAC). In one embodiment, the method includes calling a function stored in the flash memory, wherein a first parameter is passed to the function when it is called, wherein the first parameter identifies a first data structure that is stored in flash memory, and wherein the first data structure includes first DMAC control values. The CPU reads the first DMAC control values in response to the CPU executing instructions of the function. The CPU then writes the first DMAC control values to respective control registers of the DMAC in response to the CPU executing instructions of the function.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 29, 2020
    Assignee: RENESAS ELECTRONICS AMERICA INC.
    Inventor: Dale Sparling
  • Patent number: 10789004
    Abstract: Implementations of the present disclosure relate to a method, system and computer program product for managing a storage system. Specifically, in one implementation of the present disclosure there is provided a method for managing a storage system. The method comprises: determining an access level of a target extent comprised in a stripe of a storage system, the access level indicating the possibility that the target extent will be accessed; obtaining a usage state of a target storage device where the target extent resides, the target storage device residing in a storage device pool associated with the storage system; and processing a mapping relationship between the target extent and the target storage device on the basis of the access level and the usage state. In other implementations of the present disclosure, there is provided a corresponding system and computer program product.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: September 29, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Wayne Weihua Li, Geng Han, Jamin Kang, Jibing Dong
  • Patent number: 10776297
    Abstract: A trigger operation method of an electronic device is provided. The trigger operation method includes when a trigger jack device is connected to a jack interface, configuring trigger execution information on the basis of at least one of sharing configuration information related to a task in progress, configuration change information, and communication connection configuration information, and recording the trigger execution information in the trigger jack device connected to the jack interface.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: September 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Younghak Oh, Soji Kang, Jihun Lee, Yusin Jung, Seungpyo Hong
  • Patent number: 10776296
    Abstract: A control method for a host device includes assigning a first detection command and a first identification number to a first slave device; receiving first response information generated by the first slave device to determine the first function number of the first slave device; and determining whether the first slave device is cascaded to a second slave device. When the first slave device is not cascaded to the second slave device, the host device performs a first specific action according to the first function number, or it directs the first slave device to perform a first specific action. When the first slave device is cascaded to the second slave device, the host device assigns a second detection command and a second identification number to the second slave device and receives second response information generated by the second slave device.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: September 15, 2020
    Assignee: Nuvoton Technology Corporation
    Inventor: Sheng-Tsai Chang
  • Patent number: 10769089
    Abstract: A write blocking system may include a host computer. The host computer may include a host processor configured as a blocking driver. A separate connection interface device may be is configured to be operatively coupled to the host computer, and include a switch and a connection interface control device, such as a processor assembly. The switch may be connected by the drive socket to a storage drive. The connection interface control device may communicate with the blocking driver while the connection interface control device is operatively coupled to the host computer. The connection interface control device may selectively establish communication between the storage drive and the host computer by operating the switch after communication between the connection interface control device and the blocking driver. The blocking driver may prevent the host computer from altering data stored on the connected storage drive.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 8, 2020
    Assignee: CRU Acquisition Group, LLC
    Inventors: James P. Wiebe, Dean L. Mehler, Randal Barber
  • Patent number: 10761776
    Abstract: A method for handling a command ID conflict in an NVMe-based solid-state drive (SSD) device includes fetching, from a host submission queue (HSQ), one or more commands submitted by a host device. The fetched commands are checked to determine if there is a command ID conflict. A command ID (CID) error interrupt is communicated to firmware of the SSD device if the command ID conflict is detected. A command validation is performed for the one or more commands on receiving the CID error interrupts. A command response is communicated with additional special information from the device FW to the host device for a command having a command ID conflict. One or more resources associated with the one or more commands are released based on the command response.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chandrashekar Tandavapura Jagadish, Abhinav Kumar Singh, Vikram Singh Shekhawat
  • Patent number: 10762004
    Abstract: A hardware independent peripheral control system and method are disclosed. The system comprises: a virtualised controller (20) executable by a processor (35) of a host system (30). The virtualised controller (20), when executed by the host system (30), has an input interface (21), an output interface (22), a processor (23) and a memory (24). The memory (24) encodes data on one or more peripheral specific instructions to control a peripheral (40) attached or connected to the host system (30). The input interface (21) is configured to receive peripheral agnostic instructions from the host system (30).
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 1, 2020
    Assignee: DENSITRON TECHNOLOGIES LIMITED
    Inventor: Matej Gutman
  • Patent number: 10761986
    Abstract: A data processing system includes a host processor, a local memory coupled to the host processor, a plurality of remote memory media, and a scalable data fabric coupled to the host processor and to the plurality of remote memory media. The scalable data fabric includes a filter for storing information indicating a location of data that is stored by the data processing system. The host processor includes a hardware sequencer coupled to the filter for selectively moving data stored by the filter to the local memory.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 1, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Blagodurov, Timothy E. Landreth, Stanley Ames Lackey, Jr., Patrick Conway
  • Patent number: 10762015
    Abstract: A peripheral module of a programmable controller and method for operating the peripheral module, wherein in a calibration mode a base voltage value is supplied by the peripheral module to a terminal via a switching device, the supply potential is changed at a start time by the peripheral module to the modified value and a response time at which the expected change occurs is acquired, and the valid time interval is ascertained by the peripheral module utilizing the start time and the response time.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 1, 2020
    Assignee: Siemens Aktiengesellschaft
    Inventor: Sevan Haritounian
  • Patent number: 10761816
    Abstract: A method and system for determining interface compatibility between components are provided. In the system for determining interface compatibility in component model-based software design, the system includes a compatibility rule manager managing interface compatibility rules, and an interface compatibility validator verifying interface compatibility between components based on the interface compatibility rules.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Ho Son, Ja-Gun Kwon
  • Patent number: 10754578
    Abstract: Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
  • Patent number: 10754797
    Abstract: A network device stores information associated with a packet in a queue. The network device sends an interrupt to a host to notify the host of completion of processing the packet. A Memory-Mapped Input/Output (MMIO) write transaction is received that includes a pointer update associated with the queue and an interrupt unmasking value. The pointer is updated and the interrupt is unmasked based on receiving the single MMIO write transaction.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: August 25, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Georgy Machulsky, Netanel Israel Belgazal, Said Bshara, Nafea Bshara, Adi Habusha
  • Patent number: 10747617
    Abstract: Techniques manage a storage system and involve: determining priorities of a first set of to-be-executed operations of a first stripe of a plurality of stripes of the storage system and priorities of a second set of to-be-executed operations of a second stripe, the plurality of stripes at least including the first stripe and the second stripe different from the first stripe, and each of the plurality of stripes including a plurality of extents distributed on different storage devices; determining a first to-be-executed operation with the highest priority among the priorities of the first set of to-be-executed operations; determining a second to-be-executed operation with the highest priority among the priorities of the second set of to-be-executed operations; and determining operation execution priorities of the first and second stripes based on the priorities of the first and second to-be-executed operations. Accordingly, the processing performance of the storage system is increased.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: August 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Hongpo Gao, Jian Gao, Geng Han, Yousheng Liu, Shaoqin Gong
  • Patent number: 10740258
    Abstract: An I/O processing system includes reception of a request to perform an I/O operation at a storage driver, and, in response to receiving the request, providing of the request to a storage device, and scheduling a timer associated with a callback routine to determine whether the storage device has completed the I/O operation, and, in response to expiration of the scheduled timer, determination of whether the storage device has completed the I/O operation.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 11, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Robin Andrew Alexander, HoYuen Chau, Xiaozhong Xing, Danyu Zhu, Liang Yang, Vishal Jose Mannanal
  • Patent number: 10725957
    Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 28, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Thomas A. Volpe, Nafea Bshara, Yaniv Shapira, Adi Habusha
  • Patent number: 10725943
    Abstract: Apparatuses and methods for transferring data from memory on a data path are described. An example apparatus includes: one or more data terminals; a plurality of memory banks, one of the plurality of memory banks being selected responsive, at least in part, to a bank address; and a data path including a plurality of data path routes and a plurality of switching buffers on the plurality of data path routes. The plurality of switching buffers are arranged such that one or more of the plurality of switching buffers are selected responsive, at least in part, to the bank address and activates one of the plurality of data path routes.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hiromasa Noda
  • Patent number: 10725950
    Abstract: A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Atmel Corporation
    Inventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot