Patents Examined by Idriss N Alrobaye
  • Patent number: 11182321
    Abstract: Techniques are provided for characterizing and quantifying a sequentiality of workloads using sequentiality profiles and signatures. One exemplary method comprises obtaining telemetry data for an input/output workload; evaluating a distribution over time of sequence lengths for input/output requests in the telemetry data by the input/output workload; and generating a sequentiality profile for the input/output workload to characterize the input/output workload based at least in part on the distribution over time of the sequence lengths. Multiple sequentiality profiles for one or more input/output workloads may be clustered into a plurality of clusters. A sequentiality signature may be generated to represent one or more sequentiality profiles within a given cluster. A performance of data movement policies may be evaluated with respect to the sequentiality signature of the given cluster.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: November 23, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Rômulo Teixeira de Abreu Pinho, Hugo de Oliveira Barbalho, Vinícius Michel Gottin, Roberto Nery Stelling Neto, Alex Laier Bordignon, Daniel Sadoc Menasché
  • Patent number: 11176075
    Abstract: A hybrid bus hub circuit and related apparatus are provided. The bus hub circuit can be configured to bridge a radio frequency front-end (RFFE) bus with a number of auxiliary buses of different types. Each of the auxiliary buses may support a fixed number of slaves identified respectively by a unique slave identification (USID). The hybrid bus hub circuit can be configured to selectively activate an auxiliary bus(es) for communication with the RFFE bus, thus making it possible to reuse a same set of USIDs among the auxiliary buses without causing potential identification conflict. As such, it may be possible to support more slaves in an apparatus with a single RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible heterogeneous bus deployment in the apparatus.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: November 16, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Christopher Truong Ngo, Alexander Wayne Hietala
  • Patent number: 11175928
    Abstract: The present invention relates to the technical field of electronic communication, and specifically disclosed thereby are a master-slave configuration communication protocol, a method for improving compatibility and an electronic device. The master-slave configuration communication protocol comprises: electrically connecting one GPIO pin of a master configuration to at least one kind of slave configuration; the master configuration sending a mock address to the slave configuration through the GPIO pin; and the slave configuration receiving the mock address and comparing the mock address with its native address, if the mock address matches the native address, the slave configuration sends its parameter information to the master configuration.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 16, 2021
    Inventor: Jun Deng
  • Patent number: 11169942
    Abstract: A double data rate (DDR) RF digitization module for a software defined radio (SDR) is disclosed. In embodiments, the DDR RF digitization module includes a printed circuit board (PCB) terminating in a DDR memory bus interface comprising a plurality of input/output (I/O) connectors insertable into a DDR slot of an SDR motherboard. The RF digitization module is connectable to an RF front end of the SDR via receiver-side (Rx) and transmitter-side (Tx) RF connectors. The RF digitization module includes DDR analog-digital converters (ADC) and digital-analog converters (DAC) mounted to the PCB and in communication with the RF front end and the DDR memory bus. The DDR ADCs provide high speed digital sampling of inbound RF signals for the signal processors via the DDR memory bus, and the DDR DACs provide high speed generation of transmittable analog RF signals based on digital spectrum data generated by the signal processors.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 9, 2021
    Assignee: Rockwell Collins, Inc.
    Inventor: Matthew J. Poduska
  • Patent number: 11169927
    Abstract: A distributed cache is managed. In some embodiments, only a subset of a plurality of processing nodes may be designated as cache managers that manage the cache access history of a logical area, including having an exclusive right to control the eviction of data from cache objects of the logical area. In such embodiments, all of the processing nodes may collect cache access information, and communicate the cache access information to the cache managers. Some of the processing nodes that are not cache managers may collect cache access information from a plurality of the other non-cache managers. Each such processing node may combine this communicated cache access information with the cache access information of the processing node itself, sort the combined information per cache manager, and send the resulting sorted cache access information to the respective cache managers. The processing nodes may be arranged in a cache management hierarchy.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 9, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Gabriel Benhanokh, Arieh Don
  • Patent number: 11163712
    Abstract: An electronic switching device includes a USB interface, a multifunctional module, a microprogrammed control module, a recognition program unit and a transient memory. The USB interface is connected with a computer through a USB cable. The multifunctional module includes a UART circuit unit and a power supply. The UART circuit unit and the power supply are disposed in the electronic switching device. The UART circuit unit is connected between the USB interface and the microprogrammed control module. The recognition program unit is disposed in the microprogrammed control module. The transient memory is disposed in the microprogrammed control module. The microprogrammed control module stores an initial value of the UART circuit unit or a start value of the UART circuit unit in the transient memory to dynamically switch UART function statuses of the UART circuit unit.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: November 2, 2021
    Assignee: Cheng Uei Precision Industry Co., Ltd.
    Inventor: Chin Huang Tseng
  • Patent number: 11157462
    Abstract: Transportable storage devices are communicatively coupled behind one or more dedicated “edge” data servers to take advantage of the benefits of the data servers and transportable storage devices while limiting their disadvantages. Each edge data server ingests data from one or more client devices and copies the data to one or more of the transportable storage devices for eventual transport to a cloud data center for upload to a cloud storage system. Object identifiers of objects stored on the transportable storage devices are maintained in a namespace of the data servers after decoupling of the transportable storage devices from the data servers so that the object identifiers remain visible to client devices.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 26, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Richard Paul Testardi, Andrea D'Amato, Devidas Joshi, Mohit Kumar Garg, Sebastien Charles, Gautam Gopinadhan, Stephen Wade Wolfe, John Renaud, Ernie Pistor
  • Patent number: 11150819
    Abstract: A memory system includes a memory device including a plurality of memory blocks, and a controller in communication with the memory device to control an operation of the memory device, the controller allocating, among the plurality of memory blocks, a normal region and a redundancy region. The controller divides the normal region into a user region for storing user data, a user overprovisioning region for user data management, a map region for storing map data, and a map overprovisioning region for map data management, and divides the redundancy region into a reserved region and an additional map overprovisioning region, and wherein the reserved region, upon determination that a block in the normal region is a bad block, replaces the bad block.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 19, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11151063
    Abstract: A host system is connected to the internal fabric of a storage system without an intervening external network or director or other component of the storage system controlling the host system's access to the internal fabric. The host system may exchange I/O communications with physical storage devices and/or global memory over an I/O path that does not include any directors, for example, over the internal fabric to which the host system is directly attached. In embodiments in which at least a portion of the global memory is considered part of a director, the host system may be configured to communicate with such global memory over the internal fabric and without use of director compute resources.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: October 19, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Ian Wigmore, Alesia A. Tringale, Jason J. Duquette
  • Patent number: 11144339
    Abstract: Various systems, methods, and processes for optimizing access to production data in application development and testing environments are disclosed. If an input/output (I/O) operation is a read operation, a storage location on a virtual storage unit at which the read operation is to be performed is determined. Also determined is whether an earlier write operation was performed at the storage location. If an earlier write operation was performed at the storage location, the read operation is performed on one or more virtual data files. However, if the earlier write operation was not performed at the storage location, the read operation is performed on allocated storage space.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 12, 2021
    Assignee: Veritas Technologies LLC
    Inventors: Chirag Dalal, Vaijayanti Rakshit Bharadwaj
  • Patent number: 11144454
    Abstract: Metadata in volatile memory is selectively compressed and destaged to non-volatile storage in the event of an emergency shutdown due to loss of like power. Compression offload hardware that is normally used for data compression is used to compress the metadata, e.g. at line speed. The compressed metadata and any uncompressed metadata that was not selected for compression may be destaged to vault drives along with compressed and uncompressed data that is in the volatile memory. Compression during vaulting may decrease power consumption when operating under standby battery power.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 12, 2021
    Assignee: Dell Products L.P.
    Inventors: James Guyer, Jason Duquette
  • Patent number: 11144448
    Abstract: Method for managing flash translation layers (FTL) table updates in response to unmap commands starts with an unmap controller receiving unmap command that comprises a listing of regions in at least one memory component to be unmapped. Unmap controller updates an unmap regions list based on the unmap command. Unmap controller receives a write command to non-volatile memory component. Unmap controller determines, using the unmap regions list, if a write command occurs in a portion of an unmapped region of the non-volatile memory component. In response to determining that write command occurs in the portion of the unmapped region of the non-volatile memory component, unmap controller loads logical-to-physical (L2P) row to volatile memory. L2P row comprises a set of L2P entries mapping the portion of the unmapped region of the non-volatile memory component. Unmap controller then causes the set of L2P entries to be unmapped.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Christian M Gyllenskog
  • Patent number: 11144235
    Abstract: Disclosed approaches for measuring memory performance include inputting respective sets of parameter values for master circuits. Each set specifies control over a transaction issuance rate, a transaction size, or an address pattern. Configuration data is generated for implementing master circuits in programmable logic circuitry based on the sets of parameter values. Each master circuit is configured to issue memory transactions according to the respective set of parameter values. The programmable logic circuitry is configured with the configuration data, and the master circuits are activated. Each master circuit issues memory transactions based on the respective set of parameter values. Each master circuit measures performance metrics of memory circuitry in processing the memory transactions and stores data indicative of the performance metrics.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: October 12, 2021
    Assignee: XLNX, INC.
    Inventors: Rowan Lyons, Noel Brady
  • Patent number: 11144486
    Abstract: An information handling system includes a processor with an Improved Inter-Integrated Circuit (I3C) master interface, a first device with a first I3C slave interface, and a second device with a second I3C slave interface. The first I3C slave interface provides first In-Band Interrupts (IBIs) to the I3C master interface and has a first I3C address. The second I3C interface provides second IBIs to the I3C master interface and has a second I3C address. The second I3C address is higher than the first I3C address. The processor receives the first IBI, determines that the second IBIs are masked by the first Mb due to the second I3C address being higher than the first I3C address, and assigns a third I3C address to one of the first I3C slave interface and the second I3C slave interface in response to determining that the second IBIs are masked by the first IBIs.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: October 12, 2021
    Assignee: Dell Products L.P.
    Inventors: Nihit S. Bhavsar, Timothy M. Lambert
  • Patent number: 11144495
    Abstract: An authentication and information system for use in a surgical stapling system includes a microprocessor configured to demultiplex data from a plurality of components in the surgical system. The authentication and information system can include one wire chips and a coupling assembly with a communication connection.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: October 12, 2021
    Assignee: Covidien LP
    Inventors: Ethan Collins, David Durant, John Hryb
  • Patent number: 11140001
    Abstract: The invention relates to a method for providing data packets (5) from a CAN bus (2), in particular a charging station for a motor vehicle. In order to permit a resource-saving and nevertheless secure possible way of providing data packets (5), steps are provided: detection of the data packets (5) from at least one component (3) of the CAN bus (2) by a detection unit (10) which is part of the CAN bus (3), creation of at least one web resource (6) which contains the data packets (5) in accordance with a predetermined specification by a computing unit (11), wherein only data packets (5) which are related in accordance with the predetermined specification are combined in the at least one web resource (6), transmission of a content of the at least one web resource (6) from the computing unit (11) to a receiving device (4) by means of a communication unit (12) via a data link (7) having a transmission protocol that differs from the CAN bus (2).
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 5, 2021
    Inventors: Sebastian Bode, Matthias Kovatsch
  • Patent number: 11138134
    Abstract: A software only debug approach is provided that does not require special hardware in a target embedded system undergoing debug. Instead, already present DMA capabilities of the target system are utilized to transfer I/O operation parameters into a memory area accessible to both the target processor and a debugger executing on a host system. The debugger can thereby access and execute the I/O operations without program execution stopping on the target. A semihosting library is provided as a replacement for the standard C I/O library on the target. The semihosting library provides a range of equivalent functions to the standard C I/O API that program a DMA transfer to copy the I/O function parameters to an external memory area that is not otherwise being used by the target core processor. The external memory area is then accessed by a debug tool on the host computer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 5, 2021
    Assignee: NXP USA, Inc.
    Inventors: Alexandra Dracea, Catalina D. Mitulescu
  • Patent number: 11132310
    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 28, 2021
    Inventors: Ramdas P. Kachare, Fred Worley, Harry Rogers, Wentao Wu, Nagarajan Subramaniyan
  • Patent number: 11126585
    Abstract: The present disclosure generally relates to an interface transmitting training method and algorithm. The receiving device can train the transmitting device to choose the correct tap for transmitting from the transmitting device. During the training, the receiving device will send a request for a directional change tap. The transmitting device will note the request, but not act on the request. The receiving device will then send another request for a direction change tap. If the new request is for the same directional change tap as the previous request, and the number of consecutive identical directional change tap requests exceeds a predetermined threshold, the request is executed. By so doing, the effect of randomness for choosing the correct tap is minimized and the link is not degraded by transmitter training. As such, there is an overall improvement in the bit error rate and reliability of the serial interface.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: September 21, 2021
    Inventors: Brian Joyce, Mackenzie Roeser
  • Patent number: 11119673
    Abstract: A method for dynamically adjusting utilization of I/O processing techniques includes providing functionality to execute a plurality of I/O processing techniques. The I/O processing techniques include a first I/O processing technique that uses a higher performance communication path for transmitting I/O and a second I/O processing technique that uses a lower performance communication path for transmitting I/O. The method automatically increases use of the first I/O processing technique and reduces use of the second I/O processing technique when the set of conditions is satisfied. Similarly, the method automatically increases use of the second I/O processing technique and reduces use of the first I/O processing technique when the set of conditions is not satisfied. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: August 12, 2018
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Matthew G. Borlick, Kyler A. Anderson