Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Abstract: A recovery storage system asynchronously protecting a synchronously replicated dataset, where the asynchronous protection of the synchronously replicated dataset includes: receiving, by a recovery storage system, an identifier of a synchronously replicated dataset, wherein the synchronously replicated dataset is a dataset synchronously replicated across the plurality of storage systems; asynchronously replicating, on the recovery storage system, the synchronously replicated dataset from the plurality of storage systems; detecting that each dataset in the synchronously replicated dataset on the plurality of storage systems has become unavailable; and restoring the dataset on the recovery storage system.

Abstract: A sensing device includes a sensed information transmitting circuit, a control information slave circuit and a mode switching circuit. The sensed information transmitting circuit converts sensed information into a transmission signal compliant with a signal format of a first transmission protocol. The control information slave circuit converts a received signal received from a signal transmission interface into control information according to a second transmission protocol, thereby to configure the sensing device. The mode switching circuit to activates one of the sensed information transmitting circuit and the control information slave circuit based on a signal on a clock channel of the signal transmission interface, a signal on a data channel of the signal transmission interface or a signal on a power rail of the sensing device, thereby to transmit or receive signals through the signal transmission interface.

Abstract: Methods and systems for managing operation of data processing systems are disclosed. The data processing systems may include a limited number of hardware components. To increase the usable number or types of hardware components, an add-in card or other device may be attached to the data processing system. To facilitate connection of a variety of types of devices having varying form factors, an interposer may be used. The data processing system may modify a communication topology based on whether a device or the interposer is connected to it to establish communication channels.

Abstract: According to some example embodiments, a system includes: at least one motherboard; at least one baseboard management controller (BMC); a mid-plane; and at least one storage device, wherein the at least one storage device is configured to operate in a first mode or a second mode based on a first input received from the at least one motherboard or the at least one BMC via a plurality of device ports over the mid-plane; and when operating in the second mode, the at least one storage device is configured to operate in a first speed from a plurality of operating speeds based on a second input received from the mid-plane via the plurality of device ports.

Abstract: A PCI-E bus standard compliant multifunctional interface board includes a substrate, a PCI-E connector, a storage device, a non-storage device and a signal dispatch device. The PCI-E connector is provided on the substrate and is configured to be electrically connected to a host. The storage device and the non-storage device are provided on the substrate. The signal dispatch device is provided on the substrate and includes: an upstream port, a downstream port and an I/O controller. The upstream port is electrically connected to the PCI-E connector. The downstream port is electrically connected to the storage device and/or the non-storage device. The I/O controller is electrically connected to the upstream port and the downstream port to control an electrical connection relationship between the host and the storage device and/or the non-storage device.

Abstract: A transmission device communicates with a reception device via a control data bus in a communication standard of I3C. The transmission device includes a transfer mode switching section and a data transmission section. The transfer mode switching section switches a transfer mode of the control data bus from a first transfer mode having a first transfer rate to a second transfer mode having a second transfer rate faster than the first transfer rate by transmitting a switching command instructing to switch to the second transfer mode after issuance of an IBI request using a function of the I3C in the first transfer mode. The data transmission section transmits data to the reception device via the control data bus in the second transfer mode.

Abstract: A method begins by a computing device of a storage network receiving a storage network access request and determining whether the storage network access request requires multiple access steps to a plurality of storage units, where a data segment of the plurality of data segments is dispersed error encoded in accordance with dispersed storage error encoding parameters to produce a set of encoded data slices that are distributedly stored among a plurality of storage units, and where a decode threshold number of encoded data slices are needed to recover the data segment. When the storage network access request requires multiple access steps to a plurality of storage units, the method continues with the computing device determining to delegate at least as portion of the multiple access steps to a delegation agent issuing a multi-step object access partial task to the delegation agent; and receiving a multistep object access result.

Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

Abstract: Eyewear including a frame having a first side and a second side, a first temple extending from the first side of the frame, a second temple extending from the second side of the frame, electronic components, a first system on a chip (SoC) adjacent the first side of the frame coupled to a first set of the electronic components, and a second system on a chip adjacent the second side, the second SoC coupled to the first SoC and to a second set of the plurality of electronic components. Processing workloads are balanced between the first SoC and the second SoC by performing a first set of operations with the first SoC and performing a second set of operations with the second SoC.

Abstract: The present disclosure provides a data transmission apparatus and a data transmission system. The data transmission apparatus comprises a first transmission unit and a second transmission unit. The first transmission unit comprises a plurality of sensor interfaces and is configured to receive sensor data from a plurality of sensors through the plurality of sensor interfaces, and the second transmission unit comprises a computing system interface and is configured to receive the sensor data from the first transmission unit and to send the sensor data to a computing system through the computing system interface.

Abstract: A circuit for coupling a field bus and a local bus. A field bus controller is equipped to send and receive process data over the field bus. A local bus controller is equipped to send and receive the process data over the local bus. A data management unit is connected to the field bus controller and the local bus controller. The data management unit is equipped to transfer the process data between field bus controller and local bus controller. A memory area connected to the data management unit for copying and storing the process data. A processor connected to the data management unit and connected to the memory area. The processor is equipped to set up the data management unit to copy the process data into the memory area and the processor is equipped to read out the process data copied in the memory area.

Abstract: Methods and systems are disclosed to aggregate traffic from multiple server devices through a peripheral component interconnect (PCI) hosting device. In one embodiment, the PCI hosting device comprises a network interface to couple the PCI hosting device to a network, a plurality of PCI interfaces, a processing circuit to forward packets, and a power supply to supply power to the PCI interfaces independently from the plurality of server devices. Each of the PCI interfaces is designed to be coupled to one server device to the PCI hosting device, which is registered as a first PCI board of a first server device through a first PCI interface and as a second PCI board of a second server device through a second PCI interface, and the PCI hosting device is designed to forward packets between the network interface and the first server device, and the network interface and the second server device.

Abstract: An automatic addressing process for devices on a serial bus is disclosed. In one aspect, a controller is communicatively coupled to multiple power supply units (PSUs) over a serial bus. At installation (and may be at start up or reset), the controller sends a signal through the serial bus to a first PSU, which adopts a first address based on a voltage level of the signal and increases the voltage level before passing the signal to a second PSU. The second PSU adopts an address based on the increased voltage level, increments the voltage level of the signal and passes the signal down the bus. Adopted addresses are written to memory and stored in such a manner that power loss will not erase the address. This stepped voltage signal allows multiple identical PSUs to be addressed without reliance on manually-changed dip switches, separate address negotiation software, or the like.

Abstract: Systems and methods are disclosed for providing an indication of the data transfer protocol that is operative during a data transfer operation between a data storage device capable of supporting a plurality of data transfer protocols and a host computer. A protocol controller of the data storage device is configured to determine a data transfer protocol based on a data cable used and to generate a selector signal used to provide the indication.

Abstract: A method for efficient journal truncation is provided. A method for journal truncation includes maintaining a journal in a memory of a computing system including a plurality of records. Each record indicates a transaction in an ordered data structure. The method includes maintaining a truncation queue in the memory including one or more entries. Each entry in the truncation queue includes a physical on-disk offset associated with a different record of the plurality of records. The method includes determining to truncate the journal and truncating records, of the plurality of records, from the journal starting from a beginning record in the journal up to the record with the physical on-disk offset associated a least recent entry of the one or more entries in the truncation queue, where the truncating includes removing the records from the memory.

Abstract: The present invention relates to methods for enabling use of a pluggable module in a host system, regardless of the type of pluggable module used in view of the module ports of the host system, which is realized using an adaptation device. The disclosure also relates to corresponding devices; adaptation devices and host systems. The methods comprise inserting a pluggable module in a module port of a host system, obtaining information indicating an electrical interface of pluggable module and setting a mode of operation of the adaptation device for re-routing and adapting signals to/from the pluggable module towards one or more controlling entities of the host system based on the electrical interface of the pluggable module.

Abstract: For dialogue from a first on-board bus in a vehicle, with a first computer connected to a second on-board bus, connected to the first bus by a second computer, with a main command being processed for the first computer: a third computer generates a command to write a description of the main command in a first dedicated zone of the second computer, then transmits the write command to the second computer; the second computer transmits, to the first computer, auxiliary command(s) to respond to the main command after receiving the write command; the third computer transmits a command to read the second dedicated zone, to the second computer such that the second computer transmits a response to the received read command; the third computer responds to the main command upon receipt of a response to the command to read a second zone of the second computer.