Abstract: Each storage controller comprises a first storage unit, an interface unit, and a processing unit which sends, to the interface unit, a parameter which instructs n-fold write of writing data in each of n-number of (n is a natural number of 2 or more) other storage controllers. When the interface unit receives the parameter, the interface unit executes each processing of acquiring the data from the first storage unit and storing the data in the second storage unit, generating n-number of requests of writing the data in each of n-number of the other storage controllers, storing each of the generated requests in n-number of the queues corresponding to each of n-number of the other storage controllers, and processing each request stored in each queue and transferring the data stored in the second storage unit to each of n-number of the other storage controllers.

Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

Abstract: Systems, methods and computer software are disclosed for fronthaul. In one embodiment a method is disclosed, comprising: providing a virtual Radio Access Network (vRAN) having a centralized unit (CU) and a distributed unit (DU); and interconnecting the CU and DU over an Input/Output (I/O) bus using Peripheral Component Interconnect-Express (PCIe); wherein the CU and the DU include a PCI to optical converter and an optical to PCI converter.

Abstract: A hybrid storage device includes an interface configured to electrically couple the hybrid storage device to an external device, and exchange data with the external device, a plurality of storage channels electrically coupled to the interface and configured to exchange the data with the interface, a plurality of chip select lines, where each of the chip select lines is electrically coupled to one storage channel in the storage channels and configured to exchange the data with the one storage channel, and a plurality of storage medium particles, where each of the storage medium particles is electrically coupled to one chip select line and configured to exchange the data with the one chip select line. The storage medium particles include a non-volatile random-access memory (NVRAM) and a flash memory.

Abstract: Examples described herein relate to a device indicating a number of available interrupt messages that is more than physical resources available to store the available interrupt messages and allocating one or more physical resources to provide one or more interrupt messages based on allocation of the one or more interrupt messages to a destination entity. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level and allocate the requested maximum permitted allocation of interrupt messages for use in a configuration region of a device. However, based on unavailability of a physical resource to store a first interrupt message, allocation of the first interrupt message to a destination entity may not be permitted.

Abstract: A method includes populating a physical storage volume associated with a second PVC from a data source identified by a first PVC and in response to populating the physical storage volume, associating the physical storage volume with the first PVC.

Abstract: A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.

Abstract: Aspects of the disclosure are directed to high performance connection cache eviction for reliable transport protocols in data center networking. Connection priorities for connection entries are determined to store the connection entries in a cache based on their connection priority. During cache eviction, the connection entries with a lowest connection priority are evicted from the cache. Cache eviction can be achieved with low latency at a high rate.

Abstract: The disclosure describes techniques for the isochronous transfer of data between a central device and one or more peripheral devices. For example, the central device may comprise any type of electronic device that is able to distribute data to peripheral devices using a wireless protocol. The isochronous transfer of data from the central device may provide an efficient method for wirelessly delivering data to multiple peripheral devices in an alternating pattern. In some examples, the isochronous transfer of data may help ensure that the peripheral devices receive timely and successful data transfers, improving the overall performance of the network of devices.

Abstract: Methods, systems, and devices for separate cores for media management of a memory sub-system are described. A controller of a memory sub-system can include a first processing core and a second processing core for a garbage collection procedure. The first processing core can perform a first set of one or more operations associated with a read process of a first stage of a garbage collection procedure for a plurality of transfer units of the memory sub-system. The second processing core can perform a second set of one or more operations associated with a write process of the first stage of the garbage collection procedure, where the second set of one or more operations are concurrent with the first set of one or more operations.

Abstract: In providing USB communication functionality over a non-USB-compliant extension medium, increased latency and processing delays may be introduced, including during configuration of endpoints. In some embodiments of the present disclosure, an upstream facing port device (UFP device) and a downstream facing port device (DFP device) are used to extend USB communication across an extension medium. In some embodiments, the UFP device extracts information from packets sent between a host device and a USB device during configuration of an endpoint. In some embodiments, the UFP device sends a synthetic NRDY packet to the host device in response to a STATUS Transaction Packet to provide the UFP device and DFP device additional time to complete configuration for servicing the endpoint.

Abstract: A method for evaluating a signal that is, for example, transferred and/or receivable via a bus system. The method includes: ascertaining a first variable that characterizes a length of a bit sequence associated with the signal, for example, the bit sequence including n bits, where n is greater than or equal to one, and optionally ascertaining a second variable that characterizes a deviation of the length of the bit sequence from a reference bit sequence that includes n bits.

Abstract: This disclosure relates to the technical field of automobiles and software and discloses an interface circuit and a method and apparatus for interface communication thereof. In the interface circuit, a micro-control unit has an output interface connected to a first conversion unit connected to a USB HOST interface and a USB SLAVE interface and a second conversion unit connected to an HDMI interface, and is configured to control the first conversion unit to be set in a HOST mode to communicate with the USB HOST interface when receiving a trigger signal from the USB HOST interface, the first conversion unit to be set in an SLAVE mode to communicate with the USB SLAVE interface when receiving a trigger signal from the USB SLAVE interface, and the second conversion unit to output the TMDS signal to communicate with the HDMI interface when receiving a trigger signal from the HDMI interface.

Abstract: In one embodiment, an apparatus includes: a first queue to store requests that are guaranteed to be delivered to a persistent memory; a second queue to store requests that are not guaranteed to be delivered to the persistent memory; a control circuit to receive the requests and to direct the requests to the first queue or the second queue; and an egress circuit coupled to the first queue to deliver the requests stored in the first queue to the persistent memory even when a power failure occurs. Other embodiments are described and claimed.

Abstract: A method for a slave bus and a master bus includes receiving a first frame via a first data channel, wherein the first frame includes at least first header data, first payload data and first checksum. The method further includes implementing a function depending on the header data contained in the received first frame, and generating a second frame including second header data, second payload data, which are determined by the implemented function, and a second checksum. The second checksum is ascertained at least on the basis of the second payload data and the first header data contained in the received first frame. The method also includes transmitting the second frame via a second data channel simultaneously with receiving the first frame via the first data channel.

Abstract: A processor interface assembly includes: a first interface circuit including a plurality of sub-interface circuits and configured to couple with a plurality of peripheral devices, wherein the plurality of peripheral devices is configured to occupy a pre-determined address space, and the pre-determined address space includes multiple sub-address spaces; and a controller including a register and configured to set a sub-address space occupied by at least one type of peripheral devices among the plurality of peripheral devices based on at least a portion of data stored in the register.

Abstract: A modular keyboard video and mouse (KVM) switching system comprises a core KVM switch module, one or more console peripheral interface modules (CPIM) and one or more host computer interface modules (HIM). The CPIM interfaces console peripheral devices to the core KVM switch module and the HIM interfaces host computer to the core KVM switch module Changing of console peripheral devices or host computer involves adapting a corresponding CPIM or HIM without changing the core KVM switch module.

Abstract: A semiconductor memory device comprises: first storage logic configured to store, as first addresses, ‘K’ addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.

Abstract: A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer. Training data is generated for transmission to the first memory address. The data is transmitted to the first memory address. Information relating to the training data is read from the first memory address and the stored data is read from the buffer and written to the memory area where the training data was transmitted.

Abstract: Described systems, apparatuses, and methods relate to volatile memories that are refreshed to maintain data integrity, such as dynamic random-access memory (DRAM) and synchronous DRAM (SDRAM). A memory device includes multiple dies, with each die having a memory array to be refreshed. The multiple dies may be interconnected via at least one inter-die bus of the memory device. A memory controller sends a command to the memory device to enter a self-refresh mode. In response, a die of the multiple dies can enter the self-refresh mode and initiate or otherwise coordinate refresh operations of the other dies. To do so, the die may transmit at least one refresh-related command to at least one other die using the inter-die bus. Multiple different signaling schemes and timing approaches are disclosed. The described inter-die refresh control principles may be implemented in energy-efficient applications, such as in low-power double data rate (LPDDR) SDRAM.