Abstract: A system includes a storage device; a storage device controller; a first interface configured to connect the storage device controller to the storage device; and a second interface configured to connect the storage device controller to a host device, wherein the storage device is configured to operate in a first mode or a second mode based on a status of a signal at the second interface based on instructions received from the host device.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: When a communication protocol is changed, the I/O function can be appropriately provided. In a computer system, a storage node includes a CPU and a storage control program that performs communication relating to data I/O. The storage control program has a first storage control program that is capable of using a first communication protocol, and a second storage control program that is capable of using the first communication protocol and a second communication protocol. The control node the control node causes, when any storage node of the plurality of storage nodes is capable of executing the first storage control program alone, all storage nodes to perform communication using the first communication protocol. The control node causes, after all storage nodes of the plurality of storage nodes are enabled to execute the second storage control program, the all storage nodes to perform communication using the second communication protocol.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: An address translation buffer or ATB is provided for emulating or implementing the PCIe (Peripheral Component Interface Express) ATS (Address Translation Services) protocol within a PCIe-compliant device. The ATB operates in place of (or in addition to) an address translation cache (ATC), but is implemented in firmware or hardware without requiring the robust set of resources associated with a permanent hardware cache (e.g., circuitry for cache control and lookup). A component of the device (e.g., a DMA engine) requests translation of an untranslated address, via a host input/output memory management unit for example, and the response (including a translated address) is stored in the ATB for use for a single DMA operation (which may involve multiple transactions across the PCIe bus).

Abstract: Methods and systems are disclosed to aggregate traffic from multiple server devices through a peripheral component interconnect (PCI) hosting device. In one embodiment, the PCI hosting device comprises a network interface to couple the PCI hosting device to a network, a plurality of PCI interfaces, a processing circuit to forward packets, and a power supply to supply power to the PCI interfaces independently from the plurality of server devices. Each of the PCI interfaces is designed to be coupled to one server device to the PCI hosting device, which is registered as a first PCI board of a first server device through a first PCI interface and as a second PCI board of a second server device through a second PCI interface, and the PCI hosting device is designed to forward packets between the network interface and the first server device, and the network interface and the second server device.

Abstract: According to one embodiment, a storage controller is configured to control a storage device capable of, upon issuance of a predetermined command, causing a storage including a temperature sensor to perform a temperature measurement to update a temperature measurement value. The storage controller includes a timer configured to notify a timeout when an elapsed time from a last issuance of the predetermined command reaches a predetermined time, and a controller configured to, when the timeout is notified, issue to the storage a command for updating the temperature measurement value.

Abstract: In one embodiment, a method for tensor data distribution using a direct-memory access agent includes generating, by a first controller, source addresses indicating locations in a source memory where portions of a source tensor are stored. A second controller may generate destination addresses indicating locations in a destination memory where portions of a destination tensor are to be stored. The direct-memory access agent receives a source address generated by the first controller and a destination address generated by the second controller and determines a burst size. The direct-memory access agent may issue a read request comprising the source address and the burst size to read tensor data from the source memory and may store the tensor data into an alignment buffer. The direct-memory access agent then issues a write request comprising the destination address and the burst size to write data from the alignment buffer into the destination memory.

Abstract: A docking station includes a network interface controller (NIC), a dock-side controller and a dock-side connector interface. The NIC is configured to transmit one or more management component transport protocol (MCTP) packets via a system management bus (SMbus). The dock-side controller is electrically coupled to the SMbus, and configured to encode the one or more MCTP packets to one or more vendor specific protocol (VSP) packets. The dock-side connector interface is electrically coupled to the dock-side controller, and configured to transmit the one or more VSP packets to an electrical device to control a basic input output system (BIOS) of the electrical device on the condition that the electrical device is connected to the docking station via the dock-side connector interface.

Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.

Abstract: A first solid state drive (SSD) includes a built-in network interface device configured to communicate via a network fabric, and a second SSD includes a built-in network interface device configured to communicate via the network fabric. A connection is opened between the first SSD and the second SSD over the network fabric, where the first SSD is further communicatively coupled to the second SSD further over an interconnect associated with a host computer. The first SSD encapsulates a non-volatile memory over fabric (NVMe-oF) command to transfer data between the first SSD and the second SSD in a capsule and sends the capsule to the second SSD over the connection. The second SSD executes the NVMe command to transfer the data between the first SSD and the second SSD over the connection according to an NVMe-oF communication protocol and without transferring any of the data to the host computer.

Abstract: Servicing I/O operations in a cloud-based storage system, including: receiving, by the cloud-based storage system, a request to write data to the cloud-based storage system; storing, in solid-state storage of the cloud-based storage system, the data; storing, in object storage of the cloud-based storage system, the data; detecting that at least some portion of the solid-state storage of the cloud-based storage system has become unavailable; identifying data that was stored in the portion of the solid-state storage of the cloud-based storage system that has become unavailable; retrieving, from object storage of the cloud-based storage system, the data that was stored in the portion of the solid-state storage of the cloud-based storage system that has become unavailable; and storing, in solid-state storage of the cloud-based storage system, the retrieved data.

Abstract: An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.

Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for data compression. The method includes: comparing the size of a first data packet to be compressed with a first threshold size; if the size of the first data packet is greater than the first threshold size, determining at least two second data packets from the first data packet, wherein the size of each second data packet is less than a second threshold size; and respectively compressing the at least two second data packets. In this way, the delay of data compression can be shortened.

Abstract: Command execution data is received. The command execution data comprises a block address corresponding to an functional component, a register identifier corresponding to a design for testability (DFT) register of the functional component, and command data. The command execution data is converted to a serial command. The serial command is committed to the DFT register of the functional component. A response to the serial command is received. The response is generated by the functional component based on the serial command. The response is converted to command response data and is provided to a testing sub-system.

Abstract: A method, computer program product, and computing system for coupling a multi-host remote direct memory access (RDMA) card to at least a pair of central processing units (CPUs). One or more signals may be routed, via the multi-host RDMA card, between the at least a pair of CPUs.

Abstract: Methods and apparatus for implementing a low-pin count architecture with priority message arbitration and delivery. The architecture includes a hardware-based message arbitration unit (MAU) including a plurality of priority queues, each having a respective priority level, implemented on a first component, such as a processor and/or System on a Chip (SoC). The first component is communicatively coupled to a second component via a low-pin count link such as an I2C bus. The MAU receives prioritized messages from clients and enqueues the messages in priority queues based on their priority levels. An arbiter selects messages to transmit over the low-pin count link from the priority queues. The MAU further may abort transmission of a message in favor of transmission of a higher-priority message to guarantee a transmit latency.

Abstract: A device includes a microcontroller, memory including secure memory to store a private key, a set of registers, and an authentication engine. The set of registers includes a write mailbox register and a read mailbox register, and message data is to be written to the write mailbox register by a host system. The message data includes at least a portion of a challenge request, and the challenge request includes a challenge by the host system to authenticity of the device. The authentication engine generates a response to the challenge, where the response includes data to identify attributes of the device and a signature generated using the private key. The authentication engine causes at least a portion of the response to be written to the read mailbox register to be read by the host system.

Abstract: Methods and Systems are described for control at/of a network node. The network node can include a control module and first and second modules coupled to the control module. The first module can be configured to select first input/output (I/O) types of a field device coupled at an I/O interface of the network node. The second module can be configured to select a second I/O types of the field device. The first and second modules can be coupled to the I/O interface through a field device coupler.

Abstract: A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport.