Patents Examined by Igwe U. Anya
  • Patent number: 10983404
    Abstract: A display device according to an exemplary embodiment includes: a first substrate; first data pads that are disposed in a first row extending along a first direction on the first substrate, second data pads that are disposed in a second row extending along the first direction on the first substrate, gate pads that are disposed in the first row and are not disposed in the second row on the first substrate, data lines that are connected with the first data pads and the second data pads on the first substrate, and control signal lines that are connected the gate pads, wherein the control signal lines extend in a side area of the second data pads from the gate pads.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 20, 2021
    Inventors: Dong Hee Shin, Yoo Mi Ra
  • Patent number: 10978538
    Abstract: A display apparatus includes: a first thin-film transistor (TFT) including a first semiconductor layer including a silicon semiconductor; a second TFT including a second semiconductor layer including an oxide semiconductor; a first shielding layer configured to overlap the first TFT and positioned between a substrate and the first TFT; and a second shielding layer configured to overlap the second TFT and positioned between the substrate and the second TFT.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 13, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seongmin Wang, Youngin Hwang, Yongho Yang
  • Patent number: 10978588
    Abstract: A semiconductor device includes a semiconductor part between first and second electrodes, first and second control electrodes between the semiconductor part and the second electrode. The semiconductor part includes a first region and a second region around the first region. The semiconductor part includes first and third layers of a first conductivity type and second layers of a second conductivity type. The second layers are provided between the first layer and the second electrode. A second layer faces the first control electrode in the second region. Another second layer faces the second control electrode in the second region. A third layer is provided between the second layer and the second electrode. Another third layer is provided between another second layer and the second electrode. The second layer includes a second conductivity type impurity with a concentration lower than that of a second conductivity type impurity in another second layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 13, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shunsuke Nitta, Takeru Matsuoka, Hiroshi Ohta
  • Patent number: 10978672
    Abstract: A display panel includes a substrate having an opening area, and a display area at least partially surrounding the opening area. Display elements are arranged in the display area. The display elements includes a pixel electrode, an opposite electrode, and an intermediate layer interposed therebetween. A multilayer film includes a first insulating layer between the substrate and the pixel electrode and a second insulating layer, of a different material, on the first insulating layer. A thin film encapsulation layer covers the display elements and includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. The multilayer film includes a first groove disposed between the opening area and the display area. The first groove has an undercut structure in which a lower width of the first groove is greater than an upper width of the first groove.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joongeol Lee, Kyeongsu Ko, Sanggab Kim, Shinil Choi
  • Patent number: 10971633
    Abstract: In accordance with an embodiment of the present invention, a method of making a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, where the semiconductor layer has a first conductivity type. The method further includes etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions including conductive material of the conductive layer over the semiconductor layer. The method further includes using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer. The diodes vertically extend from an upper surface of the semiconductor layer to the insulating layer.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 6, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 10964711
    Abstract: A semiconductor memory device includes a first insulating layer over a semiconductor substrate, a metal layer, an adhesive layer on a first region of the metal layer, a conductive layer on a second region of the metal layer and on the adhesive layer, a second insulating layer on the conductive layer, a plurality of wiring layers that are separated from each other and are stacked above the second insulating layer, a semiconductor layer that extends in a first direction perpendicular to the semiconductor substrate and includes a bottom surface connected to the conductive layer, a storage portion disposed between at least one of the plurality of wiring layers and the semiconductor layer, and a slit that extends in the first direction, includes aside surface in contact with the plurality of wiring layers and a bottom surface reaching the conductive layer, and is filled with an insulating material.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Murata, Yoshinori Nakakubo, Hiroaki Hayasaka, Naoki Yamamoto
  • Patent number: 10950654
    Abstract: A stacked quantum computing device including: a first chip including a superconducting qubit, where the superconducting qubit includes a superconducting quantum interference device (SQUID) region, a control region, and a readout region, and a second chip bonded to the first chip, where the second chip includes a first control element overlapping with the SQUID region, a second control element displaced laterally from the control region and without overlapping the control region, and a readout device overlapping the readout region.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: March 16, 2021
    Assignee: Google LLC
    Inventors: Julian Shaw Kelly, Joshua Yousouf Mutus
  • Patent number: 10947326
    Abstract: An adhesive composition comprising (a) a (meth)acrylic polymer, (b) a compound having at least two (meth)acryloyl groups, (c) a polymerization initiator and (d) a filler.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: March 16, 2021
    Assignee: SHOWA DENKO MATERIALS CO., LTD.
    Inventors: Sadaaki Katou, Takuya Komine, Shinjiro Fujii
  • Patent number: 10950788
    Abstract: A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode, and a first barrier layer, including a first oxide material and a second oxide material, where the first oxide material is different from the second oxide material, and where the first barrier layer is between one of A) the memory layer and the bottom contact, and B) the top electrode and the top contact, where the first barrier layer is configured to substantially prevent the conduction of ions or vacancies therethrough.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 16, 2021
    Assignee: 4DS MEMORY, LIMITED
    Inventor: Seshubabu Desu
  • Patent number: 10943976
    Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: March 9, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Sundar Chetlur, Maxim Klebanov, Washington Lamar
  • Patent number: 10932517
    Abstract: A monitoring system includes a shoe and a sole integrated into the shoe. The monitoring system also includes a connection mechanism attached to an underside of the sole and is shaped to connect the sole to a pedal. A pressure sensor is incorporated into the shoe that senses a force exerted on the pedal when the shoe is connected to the pedal through the connection mechanism.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: March 2, 2021
    Assignee: ICON Health & Fitness, Inc.
    Inventors: Darren C. Ashby, Scott R. Watterson
  • Patent number: 10937878
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
  • Patent number: 10930738
    Abstract: A replacement fin in a heterogeneous FinFET transistor in which source and drain regions are grown in corresponding trenches that extend into a sub-fin region. This depth of the epitaxial source/drain regions, in combination with the selected materials, can reduce off-state leakage while also keeping high defect density portions out of the active portions of the source and drain. In one embodiment, materials are selected for the source and drain regions that have an energy band offset from the material selected for the substrate. This band offset between the source/drain material can further reduce sub-fin leakage.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Dipanjan Basu, Seung Hoon Sung, Glenn A. Glass, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10930729
    Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Neville L. Dias, Rahul Ramaswamy, Hsu-Yu Chang, Roman W. Olac-Vaw, Chen-Guan Lee
  • Patent number: 10923563
    Abstract: A power device is disclosed. The power device comprises: a semiconductor substrate; a first doped region on the semiconductor substrate; a plurality of second doped regions located in a first region of the first doped region; a plurality of third doped regions located in a second region of the first doped region. The plurality of second doped regions are separated with each other at a first predetermined spacing. A first charge compensation structure is formed by the plurality of second doped regions and the first doped region, and the first charge compensation structure and the semiconductor substrate are located on a current channel. The plurality of third doped regions are separated with each other at a second predetermined spacing. A second charge compensation structure is formed by the plurality of third doped regions and the first doped region. The second charge compensation structure is configured to disperse continuous surface electric field of the power device.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: February 16, 2021
    Assignee: HANGZHOU SILAN MICROELECTRONICS CO., LTD.
    Inventor: Shaohua Zhang
  • Patent number: 10916480
    Abstract: A magnetic wall utilization type analog memory device includes a magnetization fixed layer having a magnetization oriented in a first direction, a non-magnetic layer provided on one side of the magnetization fixed layer, a magnetic wall driving layer provided on the magnetization fixed layer with the non-magnetic layer interposed therebetween, a first magnetization supplying part which is configured to supply magnetization oriented in the first direction to the magnetic wall driving layer and a second magnetization supplying part which is configured to supply magnetization oriented in a second direction reversed with respect to the first direction, wherein at least one of the first magnetization supplying part and the second magnetization supplying part is a spin-orbit torque wiring which comes into contact with the magnetic wall driving layer and extends in a direction intersecting the magnetic wall driving layer.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 9, 2021
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Tatsuo Shibata
  • Patent number: 10913874
    Abstract: The present application relates to an encapsulating composition, an organic electronic device, a method for evaluating reliability of the organic electronic device and a method for preparing the organic electronic device, and provides an encapsulating composition which can improve flatness and adhesion of an organic layer sealing an organic electronic element to effectively block moisture or oxygen introduced into an organic electronic device from the outside, thereby securing the lifetime of the organic electronic device.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 9, 2021
    Assignee: LG Chem, Ltd.
    Inventors: Kook Hyun Choi, Joon Hyung Kim, Yu Jin Woo, Mi Lim Yu
  • Patent number: 10910531
    Abstract: An optoelectronic component and a method for producing an optoelectronic component are disclosed. In an embodiment an optoelectronic component includes an optical element including silicone as a polymer material, the silicone having repeating units of cyclic siloxane and of linear siloxane which are arranged in alternation, wherein the optoelectronic component is configured to emit radiation.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: February 2, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Patrick Wenderoth, Ulf Betke, Guido Kickelbick
  • Patent number: 10910535
    Abstract: A method for making light emitting device LED arrays includes the steps of providing a plurality of LEDs having a desired configuration (e.g., VLED, FCLED, PLED); attaching the LEDs to a carrier substrate and to a temporary substrate; forming one or more metal layers and one or more insulator layers configured to electrically connect the LEDs to form a desired circuitry; and separating the LEDs along with the layered metal layers and insulator layers that form the desired circuitry from the carrier substrate and the temporary substrate.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: February 2, 2021
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventors: David Trung Doan, Trung Tri Doan
  • Patent number: 10903195
    Abstract: A manufacturing method of a micro-LED display device comprises forming a plurality of thin-film transistor array areas that includes a plurality of thin-film transistor arrays on a first substrate; forming a plurality of micro-LED array areas that includes a plurality of micro-LED arrays on a second substrate; transferring the plurality of micro-LED array areas that correspond to the plurality of thin-film transistor array areas onto the first substrate; forming a bank film on a third substrate over the first substrate; patterning the bank film to form a first bank layer that corresponds to a boundary area between the plurality of micro-LED arrays and a second bank layer that corresponds to an edge area of the plurality of micro-LED array areas, to form a pixel area and a pixel array area, and to remove the bank film in a boundary area between the second bank layers adjacent to each other; cutting the third substrate and the first substrate along a scribe zone that is set in a boundary area between the second
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: January 26, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Wonjin Choi, Geesung Chae