Patents Examined by Igwe U. Anya
  • Patent number: 10522556
    Abstract: An antifuse structure includes an active area and a gate electrode over the active area. The active area includes a first body portion and a first extending portion extending in a first direction. The gate electrode includes a second body portion and a second extending portion extending in a second direction perpendicular to the first direction. The first body portion includes a first surface facing a portion of the second body portion, and the second body portion includes a second surface facing a portion of the first extending portion. The first extending portion and the second extending portion are partially overlapped in a third direction perpendicular to both the first direction and the second direction, with a dielectric layer sandwiched between the first and second extending portions, forming an intersection area.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 31, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chin-Ling Huang, Chiang-Lin Shih, Zi-Yin Chen
  • Patent number: 10510835
    Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Yu Chou, Seiji Takahashi, Shang-Fu Yeh, Chih-Lin Lee, Chin Yin, Calvin Yi-Ping Chao
  • Patent number: 10510848
    Abstract: Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Ying Pang, Anand S. Murthy, Tahir Ghani, Karthik Jambunathan
  • Patent number: 10497571
    Abstract: A method is provided. The method includes the following operations. A dielectric layer is deposited over a substrate. Then, a first work function metal layer is deposited over the dielectric layer. Next, a dummy layer is deposited over the first work function metal layer. Afterwards, an impurity is introduced into the first work function metal layer. Then, the dummy layer is etched. Next, a second work function metal layer is deposited over the first work function metal layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • Patent number: 10497780
    Abstract: In an aspect, a circuit can include a first transistor, wherein an emitter is coupled to an emitter terminal, and a base is coupled to a base terminal; a second transistor, wherein the collector is coupled to a substrate terminal, and a base is coupled to the collector of the first transistor; and a component having a rectifying junction, wherein a first terminal is coupled to the collector of the first transistor, and a second terminal is coupled to the collector terminal of the circuit. In another aspect, an electronic device can include a substrate having a first semiconductor region; a second semiconductor region; and a third semiconductor region; a first trench isolation structure extending from a major surface through the third semiconductor region and terminating within the second semiconductor region; and an emitter region coupled to an emitter terminal of the electronic device.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Moshe Agam, Agajan Suwhanov, Johan Camiel Julia Janssens
  • Patent number: 10497694
    Abstract: A power semiconductor device includes a power transistor arranged in a power device region of a semiconductor substrate. The power semiconductor device further includes a first circuit arranged in a first circuit region of the semiconductor substrate. The power semiconductor device further includes a second circuit arranged in a second circuit region of the semiconductor substrate. The first circuit region is arranged at a first edge of the semiconductor substrate. The second circuit region is arranged at a second edge of the semiconductor substrate. The power device region is arranged between the first circuit region and the second circuit region.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Guenther Kolmeder
  • Patent number: 10497584
    Abstract: The present invention provides a method and a device for repairing semiconductor chips. The method includes providing an LED module including a circuit substrate and a plurality of light-emitting units; driving the light-emitting units by a signal generator; measuring at least one light-emitting unit by a feature detector module so as to obtain an abnormal feature and define the at least one light-emitting unit as a bad light-emitting unit having the abnormal feature; projecting a laser light source generated by a laser generating module onto the bad light-emitting unit; removing the bad light-emitting unit from the circuit substrate by a chip pick-and-place module to form a vacancy; placing a good light-emitting unit inside the vacancy by the chip pick-and-place module; and electrically connecting the good light-emitting unit to the circuit substrate. Therefore, the bad light-emitting unit is replaced by the good light-emitting unit for repairing the LED module.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 3, 2019
    Assignee: ASTI GLOBAL INC., TAIWAN
    Inventor: Chien-Shou Liao
  • Patent number: 10483164
    Abstract: A method for manufacturing a semiconductor includes following steps. An epitaxial structure including a first semiconductor material and a second semiconductor material is provided. A lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material. A metal-containing layer is deposited on the epitaxial structure. The metal containing layer includes a first metal material and a second metal material. An atomic size of the second metal material is greater than an atomic size of the first metal material. The metal-containing layer and the epitaxial structure are annealed to form a metal silicide layer on the epitaxial structure. The metal silicide layer includes the first semiconductor material, the second semiconductor material, the first metal material, and the second metal material.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yan-Ming Tsai, Wei-Yip Loh, Yu-Ming Huang, Hung-Hsu Chen, Chih-Wei Chang
  • Patent number: 10476543
    Abstract: A lighting device is disclosed having a plurality of LED chips mounted on a single planar flexible substrate, wherein the single planar flexible substrate is disposed in an arcuate orientation. A heat sink having an arcuate surface shaped to approximate the arcuate orientation of the flexible substrate is coupled to the flexible substrate between complementary arcuate surfaces. A luminescent coating is disposed about a top surface of the arcuate single planar flexible substrate.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: November 12, 2019
    Assignee: Alliance Sports Group, L.P.
    Inventor: Steven Cramer
  • Patent number: 10468313
    Abstract: Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Naohisa Nishioka
  • Patent number: 10468570
    Abstract: A circuit board includes a base plate, a first circuit layer, a first dielectric layer, and a light emitting element. The first circuit layer is disposed on the base plate. The first dielectric layer is disposed on the base plate and has plural openings. The first circuit layer is embedded in the first dielectric layer and exposes the openings. A Young's modulus of the first dielectric layer is greater than a Young's modulus of the base plate. The light emitting element is electrically connected to the first circuit layer through the openings.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 5, 2019
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Po-Hsuan Liao, Zong-Hua Li
  • Patent number: 10468485
    Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 5, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventors: Sundar Chetlur, Maxim Klebanov, Washington Lamar
  • Patent number: 10466413
    Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: November 5, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Gyungock Kim, Hyundai Park, In Gyoo Kim, Sang Hoon Kim, Ki Seok Jang, Sang Gi Kim, Jiho Joo, Yongseok Choi, Hyuk Je Kwon, Jaegyu Park, Sun Ae Kim, Jin Hyuk Oh, Myung joon Kwack
  • Patent number: 10468449
    Abstract: Disclosed is an image sensor, which includes a first PD isolation region for determining first to fourth PD regions, an FD isolation region formed between the first to fourth PD regions, and a floating diffusion formed in the FD isolation region. Horizontal distances from a perimeter of the floating diffusion to interfaces between the FD isolation region and the first to fourth PD regions are equal to each other.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 5, 2019
    Assignee: SK hynix Inc.
    Inventor: Cha-Young Lee
  • Patent number: 10461196
    Abstract: Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Steven Bentley, Ruilong Xie, Min Gyu Sung
  • Patent number: 10461202
    Abstract: Resonant-cavity infrared photodetector (RCID) devices that include a thin absorber layer contained entirely within the resonant cavity. In some embodiments, the absorber is a single type-II InAs—GaSb interface situated between an AlSb/InAs superlattice n-type region and a p-type AlSb/GaSb region. In other embodiments, the absorber region comprises quantum wells formed on an upper surface of the n-type region. In other embodiments, the absorber region comprises a “W”-structured quantum well situated between two barrier layers, the “W”-structured quantum well comprising a hole quantum well sandwiched between two electron quantum wells. In other embodiments, the RCID includes a thin absorber region and an nBn or pBp active core within a resonant cavity. In some embodiments, the RCID is configured to absorb incident light propagating in the direction of the epitaxial growth of the RCID structure, while in other embodiments, it absorbs light propagating in the epitaxial plane of the structure.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: October 29, 2019
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Jerry R. Meyer, Igor Vurgaftman, Chadwick Lawrence Canedy, William W. Bewley, Chul Soo Kim, Charles D. Merritt, Michael V. Warren, Mijin Kim
  • Patent number: 10461171
    Abstract: A method for forming a semiconductor device structure includes forming a first dummy gate stack and a second dummy gate stack over a semiconductor substrate and forming a dielectric layer over the semiconductor substrate to surround the first dummy gate stack and the second dummy gate stack. The method includes removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer and removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer. The method includes partially removing the first metal gate stack, the second metal gate stack, and the dielectric layer to form a recess. The method includes forming an insulating structure to partially or completely fill the recess.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsuan Hsiao, Shu-Yuan Ku, Chih-Chang Hung, I-Wei Yang, Chih-Ming Sun
  • Patent number: 10451762
    Abstract: Methods, systems, and computer-readable media for determining a chance of success for a prospect including two or more segments. The method may include receiving seismic data indicative of a plurality of anomalies in a prospect. The prospect may include a plurality of segments. Prior probabilities of success and failure scenarios may be computed for at least one of the segments of the prospect. Likelihoods of the anomalies may be determined given the success and failure scenarios for the at least one of the segments. At least two of the segments may be classified into a direct fluid indicator dependency group. A degree of correlation may be determined between the anomalies for the direct fluid indicator dependency group. A posterior chance of success may be determined for the prospect based at least in part on the degree of correlation between the anomalies.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 22, 2019
    Assignee: Schlumberger Technology Corporation
    Inventors: Gabriele Martinelli, Charles Stabell, Espen Langlie
  • Patent number: 10453977
    Abstract: Resonant-cavity infrared photodetector (RCID) devices that include a thin absorber layer contained entirely within the resonant cavity. In some embodiments, the absorber is a single type-II InAs—GaSb interface situated between an AlSb/InAs superlattice n-type region and a p-type AlSb/GaSb region. In other embodiments, the absorber region comprises quantum wells formed on an upper surface of the n-type region. In other embodiments, the absorber region comprises a “W”-structured quantum well situated between two barrier layers, the “W”-structured quantum well comprising a hole quantum well sandwiched between two electron quantum wells. In other embodiments, the RCID includes a thin absorber region and an nBn or pBp active core within a resonant cavity. In some embodiments, the RCID is configured to absorb incident light propagating in the direction of the epitaxial growth of the RCID structure, while in other embodiments, it absorbs light propagating in the epitaxial plane of the structure.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: October 22, 2019
    Assignee: The Governement of the United States of America, as represented by the Secretary of the Navy
    Inventors: Jerry R. Meyer, Igor Vurgaftman, Chadwick Lawrence Canedy, William W. Bewley, Chul Soo Kim, Charles D. Merritt, Michael V. Warren, Mijin Kim
  • Patent number: 10446701
    Abstract: Resonant-cavity infrared photodetector (RCID) devices that include a thin absorber layer contained entirely within the resonant cavity. In some embodiments, the absorber is a single type-II InAs—GaSb interface situated between an AlSb/InAs superlattice n-type region and a p-type AlSb/GaSb region. In other embodiments, the absorber region comprises quantum wells formed on an upper surface of the n-type region. In other embodiments, the absorber region comprises a “W”-structured quantum well situated between two barrier layers, the “W”-structured quantum well comprising a hole quantum well sandwiched between two electron quantum wells. In other embodiments, the RCID includes a thin absorber region and an nBn or pBp active core within a resonant cavity. In some embodiments, the RCID is configured to absorb incident light propagating in the direction of the epitaxial growth of the RCID structure, while in other embodiments, it absorbs light propagating in the epitaxial plane of the structure.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: October 15, 2019
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Jerry R. Meyer, Igor Vurgaftman, Chadwick Lawrence Canedy, William W. Bewley, Chul Soo Kim, Charles D. Merritt, Michael V. Warren, Mijin Kim