Patents Examined by Igwe U. Anya
  • Patent number: 12010887
    Abstract: There are provided a semiconductor unit that prevents connection failure caused by a wiring substrate to improve reliability, a method of manufacturing the semiconductor unit, and an electronic apparatus including the semiconductor unit. The semiconductor unit includes: a device substrate including a functional device and an electrode; a first wiring substrate electrically connected to the functional device through the electrode; and a second wiring substrate electrically connected to the functional device through the first wiring substrate.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: June 11, 2024
    Assignee: SONY GROUP CORPORATION
    Inventor: Hironobu Abe
  • Patent number: 12002873
    Abstract: The method for adjusting a groove depth includes: preparing masks having different thicknesses on respective top surfaces of a plurality of substrates made of silicon carbide; forming a first opening having a predetermined width and a second opening having a width wider than the first opening in each of the masks; simultaneously forming a first groove and a second groove in each of the substrates by selectively etching via the first opening and the second opening; measuring a depth ratio of the first groove to the second groove in each of the substrates; and acquiring a thickness of a mask such that the depth ratio is an intended value, from a relationship between each thickness of the masks and each depth ratio in the substrate.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: June 4, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Setsuko Wakimoto
  • Patent number: 11996457
    Abstract: A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: May 28, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuncheol Kim, Yongseok Kim, Ilgweon Kim, Seokhan Park, Kyunghwan Lee, Jaeho Hong
  • Patent number: 11996476
    Abstract: A semiconductor device includes a region of semiconductor material comprising a shielded-gate trench structure. The shielded-gate trench structure includes an active trench, an insulated shield electrode in the lower portion of the active trench, an insulated gate electrode adjacent to the gate dielectric in an upper portion of the active trench, and an inter-pad dielectric (IPD) interposed between the gate electrode and the shield electrode. A conductive region is within the active trench and extends through the gate electrode and the IPD and is electrically connected to the shield electrode. The conductive region is electrically isolated from the gate electrode. The gate electrode comprises a shape that is uninterrupted on at least one side the conductive region in a top view so that the gate electrode.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: May 28, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Peter A. Burke
  • Patent number: 11984486
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
  • Patent number: 11984496
    Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DEG.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: May 14, 2024
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Anbang Zhang, King Yuen Wong, Hao Li, Haoning Zheng, Jian Wang
  • Patent number: 11984500
    Abstract: The invention provides a multi-Vt vertical power device and a method of making the same. Through patterning a contact mask, a contact structure array having a shared trench gate structure may be formed, and different traversal gaps between an edge of a contact portion of a second conductivity type and an edge of a trench may be formed in the contact structure array. As such, multi-Vt vertical states may be implemented for storing information. The present invention allows making a multi-Vt vertical power device having different Vt's to be capable to store information without additional process steps. Therefore, with respect to the present invention, the process is simple, cost is low, and application field is wide; number of Vt varies to store multi-bit digital information or analog information in the power device; the built-in multi-Vt power MOSFET and IGBT are adapted not only for the high power applications but also for information storage.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: May 14, 2024
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa Chi, Dongyang Zhou, Jinpeng Qiu, Peng Li, Conghui Liu
  • Patent number: 11973170
    Abstract: A semiconductor package includes a photonic die, an encapsulated electronic die, a substrate, and a lens structure. The photonic die includes an optical coupler. The encapsulated electronic die is disposed over and bonded to the photonic die. The encapsulated electronic die includes an electronic die and an encapsulating material at least laterally encapsulating the electronic die. The substrate is disposed over and bonded to the encapsulated electronic die. The lens structure is disposed over the photonic die and is overlapped with the optical coupler from a top view. The optical coupler is configured to be optically coupled to an optical signal source through the lens structure.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen
  • Patent number: 11967595
    Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 23, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Jung Kim, Young Suk Chai, Sang Yong Kim, Hoon Joo Na, Sang Jin Hyun
  • Patent number: 11967631
    Abstract: The present disclosure provides a power semiconductor device and a manufacturing method thereof. In order to provide a power semiconductor device with improved latch-up immunity but without increasing device power loss and costs, a hole current path in a fourth semiconductor region of a first conductivity type between a gate trench and a dummy gate trench is shortened by providing a first contact trench between two adjacent gate trenches, and providing a second contact trench between the gate trench and a dummy gate trench such that the width and depth of the second contact trench are respectively greater than those of the first contact trench. The effect of the hole current on the potential rise of the fourth semiconductor region of the first conductivity type is suppressed, thereby suppressing the latch-up effect, and enhancing the switching reliability.
    Type: Grant
    Filed: October 30, 2023
    Date of Patent: April 23, 2024
    Assignee: JSAB TECHNOLOGIES (SHENZHEN) LTD.
    Inventors: Hao Feng, Yong Liu, Jing Deng, Johnny Kin On Sin
  • Patent number: 11961904
    Abstract: In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 16, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Ralf Siemieniec, Wolfgang Jantscher, David Kammerlander
  • Patent number: 11963443
    Abstract: The present disclosure relates to an OLED that includes a first electrode; a second electrode facing the first electrode; a first emitting material layer including a first host, a second host and a blue dopant and positioned between the first and second electrodes; a first electron blocking layer including an electron blocking material of a spirofluorene-substituted amine derivative and positioned between the first electrode and the first emitting material layer; and a first hole blocking layer including a first hole blocking material of an azine derivative and positioned between the second electrode and the first emitting material layer, wherein the first host is an anthracene derivative, and the second host is a deuterated anthracene derivative.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: April 16, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: In Bum Song, Seung Hee Yoon, Gwi Jeong Cho, So Yeon Ahn, Yoo Yi Son, Tae Shick Kim
  • Patent number: 11961906
    Abstract: A semiconductor device according to an embodiment includes first to third semiconductor regions, a structure body, a gate electrode, and a high resistance part. The structure body includes an insulating part and a conductive part. The insulating part is arranged with the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region. The conductive part is located in the insulating part. The conductive part includes a portion facing the first semiconductor region. The high resistance part is located in the first semiconductor region and has a higher electrical resistance than the first semiconductor region. A plurality of the structure bodies includes first to third structure bodies. The second and third structure bodies are next to the first structure body. The high resistance part overlaps a circle center of an imaginary circle passing through centers of the first to third structure bodies.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: April 16, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Takuo Kikuchi, Kazuyuki Ito, Satoshi Akutsu
  • Patent number: 11961903
    Abstract: A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: April 16, 2024
    Assignee: HYUNDAI MOBIS CO., LTD.
    Inventors: Jeong Mok Ha, Hyuk Woo, Sin A Kim, Tae Youp Kim, Ju Hwan Lee, Min Gi Kang, Tae Yang Kim
  • Patent number: 11955540
    Abstract: Provided is a semiconductor device, comprising a semiconductor substrate; and an emitter electrode provided above an upper surface of the semiconductor substrate; wherein the semiconductor substrate has: a first conductive type drift region; a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate; a second conductive type contact region with a higher doping concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate; a trench contact of a conductive material provided to connect to the emitter electrode and penetrate the contact region; and a second conductive type high-concentration plug region with a higher doping concentration than the contact region, which is provided in contact with a bottom portion of the trench contact.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: April 9, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Soichi Yoshida
  • Patent number: 11955588
    Abstract: In one embodiment, the optoelectronic semiconductor device comprises a semiconductor layer sequence and an electrical via. The semiconductor layer sequence includes an active zone for generating radiation and a contact layer for electrical contacting. The active zone lies in a plane perpendicular to a main growth direction of the semiconductor layer sequence and is located between a first semiconductor region and a second semiconductor region. The contact layer is located within the second semiconductor region. The via extends through the contact layer and preferably ends within the second semiconductor region. A contact surface between the via and the contact layer encloses a contact angle of at least 20° and at most 60° with respect to the plane.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: April 9, 2024
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Korbinian Perzlmaier, Kerstin Neveling, Heribert Zull
  • Patent number: 11950414
    Abstract: According to one embodiment, a memory device includes a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure and including a semiconductor layer that extends in a direction perpendicular to a surface of the substrate. The semiconductor layer includes a first portion on a side of an upper portion of the structure, and a second portion between the first portion and the substrate. The first portion has a thickness larger than a thickness of the second portion.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 2, 2024
    Assignee: Kioxia Corporation
    Inventors: Yasuhiro Uchimura, Tatsufumi Hamada, Shinichi Sotome, Tomohiro Kuki, Yasunori Oshima, Osamu Arisumi
  • Patent number: 11948800
    Abstract: A device includes a pair of gate spacers on a substrate, and a gate structure on the substrate and between the gate spacers. The gate structure includes an interfacial layer, a metal oxide layer, a nitride-containing layer, a tungsten-containing layer, and a metal compound layer. The interfacial layer is over the substrate. The metal oxide layer is over the interfacial layer. The nitride-containing layer is over the metal oxide layer. The tungsten-containing layer is over the nitride-containing layer. The metal compound layer is over the tungsten-containing layer. The metal compound layer has a different material than a material of the tungsten-containing layer.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • Patent number: 11950433
    Abstract: A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first portion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jheng-Hong Jiang, Cheung Cheng, Chia-Wei Liu
  • Patent number: 11950486
    Abstract: A display device, an electronic apparatus and a method for manufacturing the display device are disclosed. The display device includes an array substrate and a first thin film encapsulation layer disposed on the array substrate. The array substrate is a silicon based organic light-emitting diode array substrate, and the array substrate includes a silicon substrate and a light-emitting device disposed on the silicon substrate; a second thin film encapsulation layer disposed between the light-emitting device and the first thin film encapsulation layer; and a color filter layer disposed between the first thin film encapsulation layer and the second thin film encapsulation layer, at each edge of the first thin film encapsulation layer, an orthographic projection of the array substrate on a plane parallel to the array substrate extends beyond an orthographic projection of the first thin film encapsulation layer on the plane.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: April 2, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Chao Pu, Shengji Yang, Kuanta Huang, Pengcheng Lu, Xiaochuan Chen