Abstract: A display device includes a substrate including a plurality of pixel areas; and a pixel provided in each of the pixel areas. The pixel may include a first electrode and a second electrode extending in a first direction on the substrate and spaced from each other in a second direction different from the first direction; a bank pattern between the substrate and the first electrode and between the substrate and the second electrode, and including at least two sub-bank patterns in a same column and spaced from each other; and a plurality of light emitting elements between the first and second electrodes. Here, each of the first and second electrodes may have at least two or more widths in the second direction along the first direction.

Abstract: A semiconductor device includes a semiconductor part, first to fourth electrodes, and insulating films. The semiconductor part is provided between the first and second electrodes. The third and fourth electrodes extend into the semiconductor part from a frond side thereof. The third electrodes are surrounded by the fourth electrode. The insulating films are provided between the semiconductor part and the third electrodes, respectively. The fourth electrode includes first to third portions. The first to third portions extend in first to third directions, respectively, along a back surface of the semiconductor part. The third portion links the first and second portions. The second direction is orthogonal to the first direction. The third direction crosses the first and second directions. The third electrodes are arranged to have a minimum spacing of two adjacent insulating films between two third electrodes adjacent to each other respectively in the first and third directions.

Abstract: A semiconductor device includes a semiconductor body having first and second opposing surfaces in a vertical direction, and transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes first and second source regions, first and second body regions, a drift region separated from the respective source region by the corresponding body region, a first gate electrode, and a control electrode. The drift region is arranged between the first and the second body region in a horizontal direction that is perpendicular to the vertical direction and extends from the first surface into the semiconductor body in the vertical direction. The first gate electrode is configured to provide a control signal for switching the transistor cell. The control electrode is configured to provide a control signal for controlling a JFET formed by the first body region, the drift region, and the second body region.

Abstract: A device having reduced Rds(on) is described. The device comprises a unit cell. The unit cell comprises: a first region, a second region, a third region, and a fourth region. The fourth region is residing on the first region, the second region, and the third region. The second region connects the first region and the third region. The first region, the second region and the third region are of same conductivity type (e.g., second conductivity type). In an embodiment, the fourth region comprises a fifth region and a sixth region. The fourth region, the fifth region, and the sixth region are of same conductivity type (e.g., first conductivity type). The fourth region is on the first region. The fifth region is on the second region. The sixth region is on the third region. In an embodiment, the device achieves reduced Rds(on) by relaxing the JFET constraint.

Abstract: A method for making light emitting device LED arrays includes the steps of providing a plurality of LEDs having a desired configuration (e.g., VLED, FCLED, PLED); attaching the LEDs to a carrier substrate and to a temporary substrate; forming one or more metal layers and one or more insulator layers configured to electrically connect the LEDs to form a desired circuitry; and mounting additional devices on the desired circuitry to form a second circuitry level; performing the mounting step multiple times to form a plurality of electronic products that include the additional devices and the second circuitry level; and separating the LEDs from the carrier substrate and the temporary substrate.

Abstract: A semiconductor device with densified dielectric structures and a method of fabricating the same are disclosed. The method includes forming a fin structure, forming an isolation structure adjacent to the fin structure, forming a source/drain (S/D) region on the fin structure, depositing a flowable dielectric layer on the isolation structure, converting the flowable dielectric layer into a non-flowable dielectric layer, performing a densification process on the non-flowable dielectric layer, and repeating the depositing, converting, and performing to form a stack of densified dielectric layers surrounding the S/D region.

Abstract: A display panel includes a substrate having an opening area, and a display area at least partially surrounding the opening area. Display elements are arranged in the display area. The display elements includes a pixel electrode, an opposite electrode, and an intermediate layer interposed therebetween. A multilayer film includes a first insulating layer between the substrate and the pixel electrode and a second insulating layer, of a different material, on the first insulating layer. A thin film encapsulation layer covers the display elements and includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. The multilayer film includes a first groove disposed between the opening area and the display area. The first groove has an undercut structure in which a lower width of the first groove is greater than an upper width of the first groove.

Abstract: A trench gate power MOSFET, including: a substrate provided with a hexagonal wide bandgap semiconductor of a first conductivity type; an epitaxial layer grown on the substrate and of the first conductivity type; a body region formed on the epitaxial layer and of a second conductivity type; a trench formed in the body region by etching, where a length direction of the trench is parallel to a projection, on the surface of a wafer, of the C axis; a second conductivity-type pillar formed by implanting first ions into a bottom region of the trench along the C axis of the hexagonal wide bandgap semiconductor material, where the bottom region of the trench is located below the trench, and is connected to the bottom of the trench, and the longitudinal depth of the second conductivity-type pillar is at least not less than 50% of the thickness of the epitaxial layer located in the bottom region of the trench; and a trench gate formed by filling the trench with a filler.

Abstract: Provided is a semiconductor device including a semiconductor substrate having an upper surface, a lower surface, and a center position equidistant from the upper surface and the lower surface in a depth direction of the semiconductor substrate. One or more N-type regions with an N-type conductivity are provided in the semiconductor substrate such that at least one N-type region among the one or more N-type regions includes the center position of the semiconductor substrate. An entire portion of the semiconductor substrate includes a bulk-acceptor having a bulk-acceptor concentration. A carrier concentration in all of the one or more N-type regions is higher than the bulk-acceptor concentration.

Abstract: A display device includes a side surface which is exposed to outside the display device, a circuit element layer including a gate line layer spaced apart from the side surface of the display device, a data line layer which is exposed to outside the display device at the side surface of the display device, and an insulating layer between the gate line layer and the data line layer, and a pad which faces the side surface of the display device and is connected to the circuit element layer at the data line layer.

Abstract: A solid-state imaging element of a pixel sharing type with improved driving of transistors is disclosed. A first electric charge accumulating section and a second electric charge accumulating section are arranged in a predetermined direction. A first transfer section transfers electric charge from first photoelectric conversion elements to the first electric charge accumulating section, causing it to accumulate the electric charge. A second transfer section transfers electric charge from second photoelectric conversion elements to the second electric charge accumulating section, causing it to accumulate the electric charge. A first transistor is configured to output a signal corresponding to an amount of the electric charge accumulated in each of the first electric charge accumulating section and the second electric charge accumulating section. A second transistor is arranged with the first transistor in the predetermined direction and connected in parallel to the first transistor.

Abstract: A display panel has a display region and a bezel region located on a periphery of the display region, and the display region includes a first region and a second region. The display panel includes a plurality of pixel driving circuits located in the first region and a plurality of pixel driving circuits located in the second region. A density of the pixel driving circuits in the first region is less than a density of the pixel driving circuits in the second region.

Abstract: The present disclosure relates to a structure comprising, in a trench of a substrate, a first conductive region separated from the substrate by a first distance shorter than approximately 10 nm; and a second conductive region extending deeper than the first region.

Abstract: A split gate carrier stored trench bipolar transistor (CSTBT) with current clamping PMOS include a P-type buried layer and a split gate electrode with equal potential to an emitter metal on the basis of the traditional CSTBT, which effectively eliminates the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation effect, and helps to improve the trade-off relationship between the on-state voltage drop and the turn-off loss. Moreover, the introduction of a parasitic PMOS structure can reduce the saturation current and improve short-circuit safe operating area of the device, reduce the Miller capacitance, and improve the switching speed of the device and reduce the switching loss of the device. In addition, the split gate CSTBT integrating the split gate electrode and gate electrode in the same trench can shorten the distance between PMOS and NMOS channels.

Abstract: A semiconductor device of an embodiment includes a transistor region and a diode region. The transistor region includes an n-type first silicon carbide region having a first portion in contact with a first plane, a p-type second silicon carbide region, an n-type third silicon carbide region, a first electrode in contact with the first portion, the second silicon carbide region, and the third silicon carbide region, a second electrode in contact with a second plane, and a gate electrode. The diode region includes an n-type first silicon carbide region having a second portion in contact with the first plane, a p-type fourth silicon carbide region, a first electrode in contact with the second portion and the fourth silicon carbide region, and a second electrode. An occupied area per unit area of the fourth silicon carbide region is larger than an occupied area per unit area of the second silicon carbide region. The first diode region is provided between a first transistor region and a second transistor region.

Abstract: A three-dimensional carrier stored trench IGBT and a manufacturing method thereof are provided. A P-type buried layer and a split gate electrode with equal potential to an emitter metal is introduced on the basis of the traditional carrier stored trench IGBT, which can effectively eliminate the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation, and at the same time can reduce the on-state voltage drop and improve the trade-off relationship between the on-state voltage drop Vceon and the turn-off loss Eoff. The split gate electrodes is introduced in the Z-axis direction, so that the gate electrodes are distributed at intervals. Therefore, the channel density is reduced. The turning on of the parasitic PMOS has a potential-clamping effect on the NMOS channel, so that the saturation current can be reduced and a wider short-circuit safe operating area (SCSOA) can be obtained.

Abstract: The present disclosure relates to a trench metal-oxide-semiconductor field-effect transistor, trench MOSFET, and to a method for manufacturing such transistors. In particular, the present disclosure relates to trench MOSFETs having deep trenches adjacent to the more shallow gate defining trench for obtaining a RESURF effect. According to the present disclosure, an ion implantation region of a charge type similar to that of the drift region is formed in the drift region. The ion implantation region extends below the deep trenches of the trench MOSFET and is vertically aligned with a base of the deep trenches.

Abstract: Provided are semiconductor devices having a three-dimensional stacked structure and methods of manufacturing the same. A semiconductor device includes a plurality of channel structures on a substrate and arranged in a three-dimensional array; a plurality of gate electrodes extending in a direction parallel to the substrate; and a plurality of source and drain electrodes extending in a direction perpendicular to the substrate. The gate electrodes are connected to the channel structures arranged in the direction parallel to the substrate, and the source and drain electrodes are connected to the channel structures arranged in the direction perpendicular to the substrate. The channel structures include a channel layer and a ferroelectric layer on the channel layer.

Abstract: A device includes gate spacers over a substrate, and a gate structure between the gate spacers. The gate structure includes an interfacial layer over the substrate, a metal oxide layer over the interfacial layer, a metal oxide layer over the interfacial layer, a first metal nitride layer over the metal oxide layer, a second metal nitride over the first metal nitride layer, and a tungsten-containing material interposing the first metal nitride layer and the second metal nitride layer.

Abstract: An array substrate, a display panel, and a display terminal are provided. The array substrate includes: a substrate; a first active layer disposed on the substrate; a first metal layer including a source electrode electrically connected to one end of the first active layer and a first gate electrode disposed opposite to the first active layer; a second active layer disposed on the first metal layer and electrically connected to the first active layer, wherein, the first gate electrode is disposed opposite to the second active layer; and a second metal layer including a drain electrode electrically connected to the second active layer.