Abstract: A display apparatus including a first thin-film transistor (TFT) including a first semiconductor layer including a silicon semiconductor; a second TFT including a second semiconductor layer including an oxide semiconductor; a first shielding layer configured to overlap the first TFT and positioned between a substrate and the first TFT; and a second shielding layer configured to overlap the second TFT and positioned between the substrate and the second TFT.

Abstract: A display panel includes a substrate having an opening area, and a display area at least partially surrounding the opening area. Display elements are arranged in the display area. The display elements includes a pixel electrode, an opposite electrode, and an intermediate layer interposed therebetween. A multilayer film includes a first insulating layer between the substrate and the pixel electrode and a second insulating layer, of a different material, on the first insulating layer. A thin film encapsulation layer covers the display elements and includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. The multilayer film includes a first groove disposed between the opening area and the display area. The first groove has an undercut structure in which a lower width of the first groove is greater than an upper width of the first groove.

Abstract: A method for reconfiguration of a vortex density in a rare earth manganate, to a non-volatile impedance switch having reconfigurable impedance, and to the use thereof as micro-inductance is disclosed. A unique voltage-time profile is applied between a first and a second electrically conductive contact attached to the rare earth manganate, such that the rare earth manganate passes through an ordering temperature in a region of an electric field forming between the two electrically conductive contacts during a cooling process during and after application of the voltage pulse or the voltage ramp, and the vortex density is thus influenced and adjusted locally in the region of the electric field forming between the two electrically conductive contacts.

Abstract: A display panel includes a base substrate, a bonding pattern, and a planarization layer pattern. The bonding pattern includes one or more conductive blocks. A bonding region is disposed on a surface, distal from the base substrate, of the conductive block. The planarization layer pattern is provided with an opening region and an occlusion region. An orthographic projection of the bonding region onto the base substrate is within an orthographic projection of the opening region onto the base substrate. The planarization layer pattern covers at least part of a side surface of the conductive block.

Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, and a switch component and a light-sensing component adjacent to each other and disposed on the substrate. The switch component includes a first semiconductor disposed on the substrate. The light-sensing component includes a second semiconductor disposed on a same layer as the first semiconductor and a light-sensing electrode disposed on a side of the second semiconductor away from the substrate and connected to the second semiconductor. The light-sensing electrode and the second semiconductor constitute a Schottky knot.

Abstract: A semiconductor device includes: a first electrode; a first semiconductor layer located on the first electrode in a diode region; a second semiconductor layer located on the first electrode in an IGBT region; a third semiconductor layer located in the diode region, the boundary region, and the IGBT region and positioned on the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer located on the third semiconductor layer in the boundary region and the IGBT region; a fifth semiconductor layer located on the third semiconductor layer and the fourth semiconductor layer; a second electrode located in the diode region; a third electrode located in the IGBT region; and a fourth electrode extending from an upper surface of the fifth semiconductor layer toward the third semiconductor layer in the boundary region and electrically insulated from the third electrode.

Abstract: A light-emitting element according to an embodiment of the present disclosure includes: a semiconductor layer having a first surface and a second surface, and including a first conductive-type layer, an active layer, and a second conductive-type layer that are stacked in order from the first surface side; a first dielectric layer provided on the second surface side of the semiconductor layer and having an opening; a first electrode electrically coupled to the first conductive-type layer on the first surface side of the semiconductor layer; and a second electrode provided on the first dielectric layer and electrically coupled to the second conductive-type layer via the opening.

Abstract: The disclosure provides a light emitting device and a manufacturing method thereof. The light emitting device includes a substrate, an LED chip, a quantum dot composite layer and a first protective layer; the LED chip is disposed on a surface of the substrate; the quantum dot composite layer is arranged on a surface of the LED chip away from the substrate; the first protective layer is arranged on a surface of the quantum dot composite layer away from the LED chip; wherein the quantum dot composite layer includes a water-soluble polymer matrix and quantum dots dispersed in the water-soluble polymer matrix; the material of the first protective layer is one of a first inorganic oxide and a first water-blocking polymer; and the material of the water-soluble polymer matrix is an oxygen-blocking polymer.

Abstract: There are provided a semiconductor unit that prevents connection failure caused by a wiring substrate to improve reliability, a method of manufacturing the semiconductor unit, and an electronic apparatus including the semiconductor unit. The semiconductor unit includes: a device substrate including a functional device and an electrode; a first wiring substrate electrically connected to the functional device through the electrode; and a second wiring substrate electrically connected to the functional device through the first wiring substrate.

Abstract: The method for adjusting a groove depth includes: preparing masks having different thicknesses on respective top surfaces of a plurality of substrates made of silicon carbide; forming a first opening having a predetermined width and a second opening having a width wider than the first opening in each of the masks; simultaneously forming a first groove and a second groove in each of the substrates by selectively etching via the first opening and the second opening; measuring a depth ratio of the first groove to the second groove in each of the substrates; and acquiring a thickness of a mask such that the depth ratio is an intended value, from a relationship between each thickness of the masks and each depth ratio in the substrate.

Abstract: A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities.

Abstract: A semiconductor device includes a region of semiconductor material comprising a shielded-gate trench structure. The shielded-gate trench structure includes an active trench, an insulated shield electrode in the lower portion of the active trench, an insulated gate electrode adjacent to the gate dielectric in an upper portion of the active trench, and an inter-pad dielectric (IPD) interposed between the gate electrode and the shield electrode. A conductive region is within the active trench and extends through the gate electrode and the IPD and is electrically connected to the shield electrode. The conductive region is electrically isolated from the gate electrode. The gate electrode comprises a shape that is uninterrupted on at least one side the conductive region in a top view so that the gate electrode.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: The invention provides a multi-Vt vertical power device and a method of making the same. Through patterning a contact mask, a contact structure array having a shared trench gate structure may be formed, and different traversal gaps between an edge of a contact portion of a second conductivity type and an edge of a trench may be formed in the contact structure array. As such, multi-Vt vertical states may be implemented for storing information. The present invention allows making a multi-Vt vertical power device having different Vt's to be capable to store information without additional process steps. Therefore, with respect to the present invention, the process is simple, cost is low, and application field is wide; number of Vt varies to store multi-bit digital information or analog information in the power device; the built-in multi-Vt power MOSFET and IGBT are adapted not only for the high power applications but also for information storage.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DEG.

Abstract: A semiconductor package includes a photonic die, an encapsulated electronic die, a substrate, and a lens structure. The photonic die includes an optical coupler. The encapsulated electronic die is disposed over and bonded to the photonic die. The encapsulated electronic die includes an electronic die and an encapsulating material at least laterally encapsulating the electronic die. The substrate is disposed over and bonded to the encapsulated electronic die. The lens structure is disposed over the photonic die and is overlapped with the optical coupler from a top view. The optical coupler is configured to be optically coupled to an optical signal source through the lens structure.

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

Abstract: The present disclosure provides a power semiconductor device and a manufacturing method thereof. In order to provide a power semiconductor device with improved latch-up immunity but without increasing device power loss and costs, a hole current path in a fourth semiconductor region of a first conductivity type between a gate trench and a dummy gate trench is shortened by providing a first contact trench between two adjacent gate trenches, and providing a second contact trench between the gate trench and a dummy gate trench such that the width and depth of the second contact trench are respectively greater than those of the first contact trench. The effect of the hole current on the potential rise of the fourth semiconductor region of the first conductivity type is suppressed, thereby suppressing the latch-up effect, and enhancing the switching reliability.

Abstract: A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.

Abstract: The present disclosure relates to an OLED that includes a first electrode; a second electrode facing the first electrode; a first emitting material layer including a first host, a second host and a blue dopant and positioned between the first and second electrodes; a first electron blocking layer including an electron blocking material of a spirofluorene-substituted amine derivative and positioned between the first electrode and the first emitting material layer; and a first hole blocking layer including a first hole blocking material of an azine derivative and positioned between the second electrode and the first emitting material layer, wherein the first host is an anthracene derivative, and the second host is a deuterated anthracene derivative.