Patents Examined by Igwe U. Anya
  • Patent number: 11322585
    Abstract: A semiconductor device includes a semiconductor layer. The semiconductor layer has bottom and upper surfaces opposite to each other in a first direction. The semiconductor layer includes a first region of a first conductivity type at the bottom surface, a second region of the first conductivity type at the bottom surface surrounding the first region, a third region of the first conductivity type above the first and second regions, and a fourth region of a second conductivity type extending from the upper surface into the third region. In a first cross sectional plane along the first direction, an outer edge of the first region is within an outer edge of the fourth region by a first distance. In a second cross sectional plane along the first direction, an outer edge of the first region is within an outer edge of the fourth region by a second distance.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Shoko Hanagata
  • Patent number: 11322581
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first and fourth semiconductor regions of a first conductivity type, and second and third semiconductor regions of a second conductivity type. The third semiconductor region is provided around the second semiconductor region along a first plane crossing a first direction from the first electrode toward the first semiconductor region and is separated from the second semiconductor region. The fourth semiconductor region is provided around the third semiconductor region along the first plane, and has a greater impurity concentration of the first conductivity type than the first semiconductor region. The second electrode is provided on the second semiconductor region and is electrically connected to the second semiconductor region.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi Matsushita
  • Patent number: 11322593
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor layer of the first conductivity type, a second silicon carbide semiconductor layer of a second conductivity type, a first silicon carbide semiconductor region of the first conductivity type, a trench, and a gate electrode on a gate insulating film. Between the gate insulating film and any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region is an interface section where a concentration of oxygen varies, the interface section having closer to the gate insulating film than to the any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region, a region where a rate of increase of the oxygen included in the interface section is greatest.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: May 3, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Tsuyoshi Araoka
  • Patent number: 11316084
    Abstract: A radiation-emitting semiconductor device (1) is specified, comprising a semiconductor body (2) having an active region (20) provided for generating radiation, a carrier (3) on which the semiconductor body is arranged and an optical element (4), wherein the optical element is attached to the semiconductor body by a direct bonding connection. Furthermore, a method for producing of radiation-emitting semiconductor devices is specified.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: April 26, 2022
    Assignee: OSRAM OLED GMBH
    Inventors: Roland Heinrich Enzmann, Hubert Halbritter, Martin Rudolf Behringer
  • Patent number: 11309420
    Abstract: The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate having fins and forming an initial gate structure across the fins, which covers a portion of a top surface and sidewall surfaces of the fins, and includes an initial first region and an initial second region on the initial first region. A bottom boundary of the initial second region is higher than the top surface of the fins, and a size of the initial first region is larger than a size of the initial second region. A first etching process is performed on sidewalls of the initial gate structure to form a gate structure, which includes a first region formed by etching the initial first region, and a second region formed by etching the initial second region. A size of the first region is smaller than a size of the second region.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Haiyang Zhang, Bo Su
  • Patent number: 11302766
    Abstract: There are provided a semiconductor unit that prevents connection failure caused by a wiring substrate to improve reliability, a method of manufacturing the semiconductor unit, and an electronic apparatus including the semiconductor unit. The semiconductor unit includes: a device substrate including a functional device and an electrode; a first wiring substrate electrically connected to the functional device through the electrode; and a second wiring substrate electrically connected to the functional device through the first wiring substrate.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 12, 2022
    Assignee: SONY CORPORATION
    Inventor: Hironobu Abe
  • Patent number: 11296270
    Abstract: Optoelectronic modules exhibiting relatively small thickness and methods for their manufacture are disclosed. The optoelectronic modules include substrates and transparent covers. Each optoelectronic module includes a transparent substrate on which an optoelectronic component is mounted. The optoelectronic component can be sensitive to and/or operable to generate a particular wavelength of electromagnetic radiation. The transparent substrate is transmissive to the particular wavelength of electromagnetic radiation. In some instances, the transparent substrate is composed, at least partially of glass.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: April 5, 2022
    Assignee: ams Sensors Singapore Pte. Ltd.
    Inventors: Bojan Tesanovic, Nicola Spring
  • Patent number: 11296220
    Abstract: A semiconductor device of an embodiment includes: a nitride semiconductor layer including a first GaN region of n-type, a second GaN region of n-type on the first GaN region, a third GaN region of p-type on the first GaN region, a fourth GaN region of p-type sandwiching the second GaN region with the third GaN region, a fifth GaN region of p-type on the third GaN region, a sixth GaN region of p-type sandwiching the second GaN region with the fifth GaN region, a seventh GaN region of n-type on the fifth GaN region, an eighth GaN region of n-type on the sixth GaN region, a trench between the seventh GaN region and the eighth GaN region, the trench having an inclination angle of less than 90 degrees; a gate insulating layer including an aluminum nitride film in the trench; a gate electrode; a first electrode; and a second electrode.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: April 5, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi
  • Patent number: 11296213
    Abstract: According to an embodiment of a power semiconductor device, the device includes: a semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode. The IGBT region includes a plurality of first trenches extending perpendicular to a first main surface of the semiconductor substrate. The diode region includes a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate. An average lateral spacing between adjacent ones of the second trenches is greater than an average lateral spacing between adjacent ones of the first trenches. Additional power semiconductor device embodiments are described herein, as are corresponding methods of production.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: April 5, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Christian Philipp Sandow, Wolfgang Roesner, Matteo Dainese
  • Patent number: 11296191
    Abstract: Dielectric breakdown resistance of a power module including a SiC-IGBT and a SiC diode is improved. The power module includes a SiC-IGBT 110 and a SiC diode 111, and a film thickness of a resin layer 323 covering an upper portion of an electric field relaxation region 320 of the SiC-IGBT 110 is larger than a chip thickness of the SiC-IGBT 110, that is, for example, 200 ?m or more.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 5, 2022
    Assignee: HITACHI, LTD.
    Inventors: Ryuusei Fujita, Naoki Watanabe, Yuan Bu
  • Patent number: 11289513
    Abstract: A thin film transistor and a method for fabricating the same, an array substrate and a display device are provided. The thin film transistor includes an active layer and a protective layer being provided on and in direct contact with the active layer, the protective layer is provided corresponding to a channel region of the thin film transistor; the protective layer is made of an oxygen-enriched metallic oxide insulation material which will not introduce any new element into the active layer. In the thin film transistor and the method for fabricating the same, the array substrate and the display device provided by the present disclosure, the active layer can be protected from being damaged by the etchant for forming the source/drain, and no new element will be introduced into the active layer; thus the characteristics and the stability of the thin film transistor is improved.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: March 29, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ke Wang, Hehe Hu, Xinhong Lu
  • Patent number: 11282928
    Abstract: A semiconductor device including an active structure on a substrate, the active structure including silicon germanium patterns and silicon patterns alternately and repeatedly stacked in a vertical direction perpendicular to an upper surface of the substrate; a semiconductor layer on sidewalls of the active structure that face in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source/drain region; and a gate structure on a surface of the active structure and the substrate, the gate structure extending in a second direction that is perpendicular to the first direction, wherein the silicon germanium patterns are silicon rich-silicon germanium.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keunhwi Cho, Byounghak Hong, Myunggil Kang
  • Patent number: 11282925
    Abstract: A silicon carbide semiconductor device has a gate insulating film, a first gate electrode, a first electrode, a second electrode, and a gate runner. A silicon carbide substrate has a first main surface and a second main surface. The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first main surface is provided with a gate electrode trench and a gate runner trench. The gate electrode trench is defined by a side surface and a bottom surface continuous to the side surface. The gate insulating film is in contact with both the side surface and the bottom surface. The first gate electrode is provided on the gate insulating film. The second gate electrode is provided in the gate runner trench, and is electrically connected to the first gate electrode. The gate runner is provided on the second gate electrode.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: March 22, 2022
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takashi Tsuno
  • Patent number: 11282948
    Abstract: Provided is a technique capable of obtaining sufficient latch-up tolerance and enabling integration. The wide band gap semiconductor device includes: a collector region, a charge storage region having an impurity concentration higher than that of the drift region, a base region, a charge extraction region having an impurity concentration higher than that of the base region, an emitter region, a Schottky electrode, a gate insulating film, a gate electrode, an emitter electrode, and a collector electrode.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: March 22, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yusuke Yamashiro, Kenji Hamada, Kazuya Konishi
  • Patent number: 11276806
    Abstract: A semiconductor device package includes a carrier, a die, an encapsulation layer and a thickness controlling component. The die is disposed on the carrier, wherein the die includes a first surface. The encapsulation layer is disposed on the carrier, and encapsulates a portion of the first surface of the die. The encapsulation layer defines a space exposing another portion of the first surface of the die. The thickness controlling component is disposed in the space.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi Wen Chiang, Kuang-Hsiung Chen, Lu-Ming Lai, Hsun-Wei Chan, Hsin-Ying Ho, Shih-Chieh Tang
  • Patent number: 11276776
    Abstract: A semiconductor device having a metal oxide semiconductor that includes a semiconductor substrate, a first semiconductor layer provided on a the semiconductor substrate, a plurality of second semiconductor layers selectively provided on the first semiconductor layer, a plurality of first semiconductor regions selectively provided in the second semiconductor layers at a surface thereof, a plurality of gate insulating films with a plurality of gate electrodes provided thereon, a plurality of first electrodes provided on the second semiconductor layers and the first semiconductor regions, and a second electrode provided on a back surface of the semiconductor substrate. The MOS structure configures an active region and a current detecting region of the semiconductor device. The semiconductor substrate and the first semiconductor layer are in both the active region and the current detecting region.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: March 15, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Hoshi
  • Patent number: 11276771
    Abstract: A semiconductor device is provided, which includes a semiconductor substrate, a transistor section and a diode section. Each of the transistor and diode sections includes a plurality of trench parts, an insulating portion formed on an inner wall of each trench part, a conductive portion provided in each trench part, a plurality of mesa parts, an interlayer dielectric film having contact holes, and a first electrode in contact with the mesa parts via the contact holes. The mesa parts in the transistor section include T-side mesa parts arranged closest to the diode section, the mesa parts in the diode section include D-side mesa parts arranged closest to the transistor section, and a maximum mesa width of mesa parts electrically connected to the first electrode in the transistor section is greater than both a mesa width of the T-side mesa parts and a mesa width of the D-side mesa parts.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 15, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11264462
    Abstract: A silicon carbide semiconductor device, including a semiconductor substrate having first and second semiconductor regions and a plurality of third semiconductor regions sequentially formed therein, a plurality of trenches penetrating the second and third semiconductor regions, a plurality of gate electrodes provided in the trenches via a gate insulating film, an interlayer insulating film covering the gate electrodes, a plurality of contact holes penetrating the interlayer insulating film, a first electrode provided in the contact holes and at the surface of the interlayer insulating film, and a second electrode electrically connected to the first semiconductor region. The interlayer insulating film has a plurality of recessed parts and protruding parts, to thereby form at least three recesses and protrusions repeatedly at a surface of the interlayer insulating film.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: March 1, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Setsuko Wakimoto
  • Patent number: 11264475
    Abstract: A Metal Oxide Semiconductor (MOS) trench cell includes a plurality of main gate trenches etched in the semiconductor body. In conduction state, the main gate electrode forms vertical MOS channels on the short edges and at least on a portion of the long edges in a mesa of the semiconductor body between neighbouring trenches. The longitudinal direction of the main gate trenches is oriented at an angle between 45 degrees to 90 degrees compared to the longitudinal direction of the first main electrode contacts, in a top plane view. This design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability) and processability (narrow mesa design rules) and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as silicon carbide SiC, zinc oxide (ZnO), gallium oxide (Ga2O3), gallium nitride (GaN), diamond.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: March 1, 2022
    Assignee: MQ SEMI AG
    Inventors: Munaf Rahimo, Iulian Nistor
  • Patent number: 11257898
    Abstract: In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Wei Kuo, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Robert Bogdan Staszewski